NADAR SARASWATHI COLLEGE OF

ENGINEERING AND TECHNOLOGY

VADAPUTHUPATTI, THENI

DEPARTMENT OF ELECTRONICS AND

COMMUNICATION ENGINEERING

MASTER RECORD

CS3351
DIGITAL PRINCIPLES & COMPUTER
ORGANIZATION
(Regulation 2021)
NADAR SARASWATHI COLLEGE OF ENGINEERING AND
TECHNOLOGY
VADAPUTHUPATTI, THENI

DEPARTMENT OF ELECTRONICS AND

COMMUNICATION ENGINEERING

MASTER RECORD
SUBJECT CODE : CS3351
SUBJECT NAME : DIGITAL PRINCIPLES & COMPUTER ORGANIZATION
YEAR : II
DEPARTMENT : AI&DS
SEMESTER : III
REGULATION : 2021
PREPARED BY : MRs.P.Gowthami
ASSISTANT PROFESSOR/ECE
VERIFIED AND : Dr.T.Venish Kumar
APPROVED BY HOD/ECE

STUDENT NAME:

REGISTER NUMBER:

YEAR / DEPT/SEMESTER:
NADAR SARASWATHI COLLEGE OF ENGINEERING AND
TECHNOLOGY
VADAPUTHUPATTI, THENI
VISION

To establish ourselves as a leading technological institution.

MISSION

1. To provide professional, constructive and learner centered education.

2. To make learners contribute to the development of the nation through academic
and industrial excellence.
3. To encourage learners involve in innovative researches with ethics.
4. To produce competitive and confident graduates to face the ever growing
challenges of the labour market.

DEPARTMENT OF ELECTRONICS AND COMMUNICATIN

ENGINEERING

VISION

To become pioneer in creating engineers well –versed in communication

engineering and electronic market.

MISSION

1. To provide quality education as per the requirement of the communication field

using the state -of -art infrastructure.
2. To promote excellence, creativity, nurture the spirit of innovation in the field of
digital technology.
3. To enhance relationship with electronics and communication industries,
professional society, government bodies and alumni.
4. To promote soft skills, leadership qualities and innovative research skills with
ethical values.
NADAR SARASWATHI COLLEGE OF ENGINEERING AND
TECHNOLOGY
DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING

PROGRAMME EDUCATIONAL OBJECTIVES (PEOs)

1. To enable graduates to pursue research, or have a successful career in academia

or industries associated with Electronics and Communication Engineering, or as
entrepreneurs
2. To provide students with strong foundational concepts and also advanced
techniques and tools in order to enable them to build solutions or systems of
varying complexity.
3. To prepare students to critically analyze existing literature in an area of
specialization and ethically develop innovative and research oriented
methodologies to solve the problems identified

PROGRAMME OUTCOMES (POs):

PO Graduate Attribute Programme Outcome

1. Engineering knowledge Apply the knowledge of mathematics, science,
engineering fundamentals, and an engineering
specialization to the solution of complex engineering
problems.
2. Problem analysis Identify, formulate, review research literature, and
analyze complex engineering problems reaching
substantiated conclusions using first principles of
mathematics, natural sciences, and engineering
sciences.
3. Design/development of Design solutions for complex engineering problems
solutions and design system components or processes that meet
the specified needs with appropriate consideration for
the public health and safety, and the cultural, societal,
and environmental considerations.
4. Conduct investigations of Use research-based knowledge and research methods
complex problems including design of experiments, analysis and
interpretation of data, and synthesis of the
information to provide valid conclusions.
5. Modern tool usage Create, select, and apply appropriate techniques,
resources, and modern engineering and IT tools
including prediction and modeling to complex
engineering activities with an understanding of the
limitations.
6. The Engineer and society Apply reasoning informed by the contextual
knowledge to assess societal, health, safety, legal and
cultural issues and the consequent responsibilities
relevant to the professional engineering practice.
7. Environment and Understand the impact of the professional engineering
sustainability solutions in societal and environmental contexts, and
 demonstrate the knowledge of, and need for
sustainable development.
8. Ethics Apply ethical principles and commit to professional
ethics and responsibilities and norms of the
engineering practice.
9. Individual and team Function effectively as an individual, and as a member
work or leader in diverse teams, and in multidisciplinary
settings.
10. Communication Communicate effectively on complex engineering
activities with the engineering community and with
society at large, such as, being able to comprehend and
write effective reports and design documentation,
make effective presentations, and give and receive
clear instructions.
11. Project management and Demonstrate knowledge and understanding of the
finance engineering and management principles and apply
these to one’s own work, as a member and leader in a
team, to manage projects and in multidisciplinary
environments.
12. Life-long learning Recognize the need for, and have the preparation and
ability to engage in independent and life-long learning
in the broadest context of technological change.

PROGRAM SPECIFIC OUTCOMES (PSOs)

On completion of Electronics Communication Engineering program, the student will

have the
following Program Specific Outcomes.

1. To analyze, design and develop solutions by applying foundational concepts of

electronics and communication engineering.
2. To apply design principles and best practices for developing quality products for
scientific and business applications.
3. To adapt to emerging information and communication technologies (ICT) to
innovate ideas and solutions to existing/novel problems.
COURSE OBJECTIVES:
 To analyze and design combinational circuits.
 To analyze and design sequential circuits
List of Experiments:

1. Verification of Boolean theorems using logic gates.

2. Design and implementation of combinational circuits using gates for arbitrary functions.
3. Implementation of 4-bit binary adder/subtractor circuits.
4. Implementation of code converters.
5. Implementation of BCD adder, encoder and decoder circuits
6. Implementation of functions using Multiplexers.
7. Implementation of the synchronous counters
8. Implementation of a Universal Shift register.
9. Simulator based study of Computer Architecture
TOTAL : 30 PERIODS
COURSE OUTCOMES:
At the end of this course, the students will be able to:
 CO1 : Design various combinational digital circuits using logic gates
 CO2 : Design sequential circuits and analyze the design procedures
 INDEX
MARKS FACULTY
S.NO DATE EXPERIMENT NAMES PAGE NO
AWARDED SIGNATURE

10

11

12

13

14
Ex.No.-1a STUDY OF LOGIC GATES

AIM:
To study about logic gates and verify their truth tables.

APPARATUS REQUIRED:

SL.NO. COMPONENT SPECIFICATION QTY

1. AND GATE IC 7408 1
2. OR GATE IC 7432 1
3. NOT GATE IC 7404 1
4. NAND GATE 2 I/P IC 7400 1
5. NOR GATE IC 7402 1
6. X-OR GATE IC 7486 1
7. NAND GATE 3 I/P IC 7410 1
8. IC TRAINER KIT - 1
9. PATCH CORD - 14

THEORY:
Circuit that takes the logical decision and the process are called logic gates.
Each gate has one or more input and only one output.
OR, AND and NOT are basic gates. NAND, NOR and X-OR are known as
universal gates. Basic gates form these gates.

AND GATE:
The AND gate performs a logical multiplication commonly known as AND
function. The output is high when both the inputs are high. The output is low level
when any one of the inputs is low.

OR GATE:
The OR gate performs a logical addition commonly known as OR function.
The output is high when any one of the inputs is high. The output is low level when
both the inputs are low.

NOT GATE:
The NOT gate is called an inverter. The output is high when the input is low.
The output is low when the input is high.

AND GATE:
The NAND gate is a contraction of AND-NOT. The output is high when both
inputs are low and any one of the input is low .The output is low level when both
inputs are high.

NOR GATE:
The NOR gate is a contraction of OR-NOT. The output is high when both
inputs are low. The output is low when one or both inputs are high.
X- OR GATE:
The output is high when any one of the inputs is high. The output is low
when both the inputs are low and both the inputs are high.

PROCEDURE:
(i) Connections are given as per circuit diagram.
(ii) Logical inputs are given as per circuit diagram.
(iii) Observe the output and verify the truth table.

AND GATE

SYMBOL PIN DIAGRAM

OR GATE
 NOT GATE

SYMBOL PIN DIAGRAM

EX-OR GATE

SYMBOL PIN DIAGRAM

 2-INPUT NAND GATE

SYMBOL PIN DIAGRAM

3-INPUT NAND GATE

 NOR GATE

RESULT:

The logic gates are studied and its truth tables are verified.
Ex.No.-1b VERIFICATION OF BOOLEAN
THEOREMS USING DIGITAL LOGIC GATES

AIM:
To verify the Boolean Theorems using logic gates.

APPARATUS REQUIRED:

SL. NO. COMPONENT SPECIFICATION QTY.

1. AND GATE IC 7408 1
2. OR GATE IC 7432 1
3. NOT GATE IC 7404 1
4. IC TRAINER KIT - 1
As per
5. CONNECTING WIRES - required
THEORY:

BASIC BOOLEAN LAWS

1. Commutative Law
The binary operator OR, AND is said to be commutative if,
1. A+B = B+A
2. A.B=B.A

2. Associative Law
The binary operator OR, AND is said to be associative if,
1. A+(B+C) = (A+B)+C
2. A.(B.C) = (A.B).C

3. Distributive Law
The binary operator OR, AND is said to be distributive if,
1. A+(B.C) = (A+B).(A+C)
2. A.(B+C) = (A.B)+(A.C)

4. Absorption Law
1. A+AB = A
2. A+AB = A+B

5. Involution (or) Double complement Law

1. A = A

6. Idempotent Law
1. A+A = A
2. A.A = A
7. Complementary Law
1. A+A' = 1
2. A.A' = 0

8. De Morgan’s Theorem
1. The complement of the sum is equal to the sum of the product of the individual
complements.
A+B = A.B
2. The complement of the product is equal to the sum of the individual complements.
A.B = A+B
Demorgan’s Theorem
a) Proof of equation (1):
Construct the two circuits corresponding to the functions A’. B’and (A+B)’
respectively. Show that for all combinations of A and B, the two circuits give identical
results. Connect these circuits and verify their operations.
b) Proof of equation (2)
Construct two circuits corresponding to the functions A’+B’and (A.B)’ A.B,
respectively. Show that, for all combinations of A and B, the two circuits give identical
results. Connect these circuits and verify their operations.
We will also use the following set of postulates:
P1: Boolean algebra is closed under the AND, OR, and NOT operations.
P2: The identity element with respect to • is one and + is zero. There is no identity
element with respect to logical NOT.
P3: The • and + operators are commutative.
P4: • and + are distributive with respect to one another. That is,
A • (B + C) = (A • B) + (A • C) and A + (B • C) = (A + B) • (A + C).
P5: For every value A there exists a value A’ such that A•A’ = 0 and A+A’ = 1.
This value is the logical complement (or NOT) of A.
P6: • and + are both associative. That is, (A•B)•C = A•(B•C) and (A+B)+C = A+(B+C).
You can prove all other theorems in boolean algebra using these postulates.

PROCEDURE:

1. Obtain the required IC along with the Digital trainer kit.

2. Connect zero volts to GND pin and +5 volts to Vcc .
3. Apply the inputs to the respective input pins.
4. Verify the output with the truth table.

RESULT:
Thus the above stated Boolean laws are verified.

13
Ex.No.-2 CODE CONVERTOR

AIM:
To design and implement 4-bit
(i) Binary to gray code converter
(ii) Gray to binary code converter
(iii) BCD to excess-3 code converter
(iv) Excess-3 to BCD code converter

APPARATUS REQUIRED:
SL.NO. COMPONENT SPECIFICATION QTY.
1. X-OR GATE IC 7486 1
2. AND GATE IC 7408 1
3. OR GATE IC 7432 1
4. NOT GATE IC 7404 1
5. IC TRAINER KIT - 1
6. PATCH CORDS - 35

THEORY:

The availability of large variety of codes for the same discrete elements of
information results in the use of different codes by different systems. A conversion circuit
must be inserted between the two systems if each uses different codes for same
information. Thus, code converter is a circuit that makes the two systems compatible even
though each uses different binary code.

The bit combination assigned to binary code to gray code. Since each code uses
four bits to represent a decimal digit. There are four inputs and four outputs. Gray code is a
non-weighted code.

The input variable are designated as B3, B2, B1, B0 and the output variables are
designated as C3, C2, C1, Co. from the truth table, combinational circuit is designed. The
Boolean functions are obtained from K-Map for each output variable.

A code converter is a circuit that makes the two systems compatible even though
each uses a different binary code. To convert from binary code to Excess-3 code, the input
lines must supply the bit combination of elements as specified by code and the output lines
generate the corresponding bit combination of code. Each one of the four maps represents
one of the four outputs of the circuit as a function of the four input variables.

14
 A two-level logic diagram may be obtained directly from the Boolean expressions
derived by the maps. These are various other possibilities for a logic diagram that
implements this circuit. Now the OR gate whose output is C+D has been used to
implement partially each of three outputs.

BINARY TO GRAY CODE CONVERTOR

TRUTH TABLE:

Binary Input Gray Code Output

B3 B2 B1 B0 G3 G2 G1 G0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0
1 1 0 1 1 0 1 1
1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0

K-Map for G3

G3 = B3

15
K-Map for G2

K-Map for G1

K-Map for G0

16
 LOGIC DIAGRAM:

GRAY CODE TO BINARY CONVERTOR

TRUTH TABLE:

GRAY CODE BINARY CODE

G3 G2 G1 G0 B3 B2 B1 B0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 1 0 0 1 0
0 0 1 0 0 0 1 1
0 1 1 0 0 1 0 0
0 1 1 1 0 1 0 1
0 1 0 1 0 1 1 0
0 1 0 0 0 1 1 1
1 1 0 0 1 0 0 0
1 1 0 1 1 0 0 1
1 1 1 1 1 0 1 0
1 1 1 0 1 0 1 1
1 0 1 0 1 1 0 0
1 0 1 1 1 1 0 1
1 0 0 1 1 1 1 0
1 0 0 0 1 1 1 1

17
K-Map for B3:

B3 = G3

K-Map for B2:

K-Map for B1:

18
K-Map for B0:

LOGIC DIAGRAM:

19
TRUTH TABLE: BCD TO EXCESS-3 CONVERTOR

| BCD input | Excess – 3 output |

B3 B2 B1 B0 G3 G2 G1 G0

0 0 0 0 0 0 1 1

0 0 0 1 0 1 0 0

0 0 1 0 0 1 0 1

0 0 1 1 0 1 1 0

0 1 0 0 0 1 1 1

0 1 0 1 1 0 0 0

0 1 1 0 1 0 0 1

0 1 1 1 1 0 1 0

1 0 0 0 1 0 1 1

1 0 0 1 1 1 0 0

1 0 1 0 x x x x

1 0 1 1 x x x x

1 1 0 0 x x x x

1 1 0 1 x x x x

1 1 1 0 x x x x

1 1 1 1 x x x X

K-Map for E3:

E3 = B3 + B2 (B0 + B1)
20
K-Map for E2:

K-Map for E1:

K-Map for E0:

21
 EXCESS-3 TO BCD CONVERTOR

TRUTH TABLE:

| Excess – 3 Input | BCD Output |

B3 B2 B1 B0 G3 G2 G1 G0

0 0 1 1 0 0 0 0

0 1 0 0 0 0 0 1

0 1 0 1 0 0 1 0

0 1 1 0 0 0 1 1

0 1 1 1 0 1 0 0

1 0 0 0 0 1 0 1

1 0 0 1 0 1 1 0

1 0 1 0 0 1 1 1

1 0 1 1 1 0 0 0

1 1 0 0 1 0 0 1

LOGIC DIAGRAM:

22
 EXCESS-3 TO BCD CONVERTOR

K-Map for A:

A = X1 X2 + X3 X4 X1

K-Map for B:

K-Map for C:

23
K-Map for D:

EXCESS-3 TO BCD CONVERTOR

PROCEDURE:

(i) Connections were given as per circuit diagram.

(ii) Logical inputs were given as per truth table
(iii) Observe the logical output and verify with the truth tables.

24
RESULT:

Thus the following 4-bit converters are designed and constructed.

(i) Binary to gray code converter

(ii) Gray to binary code converter
(iii) BCD to excess-3 code converter
(iv) Excess-3 to BCD code converter

25
Ex.No.-3 ADDER AND SUBTRACTOR

AIM:
To design and construct half adder, full adder, half subtractor and full
subtractor circuits and verify the truth table using logic gates.

APPARATUS REQUIRED:
SL.NO. COMPONENT SPECIFICATION QTY.
1. AND GATE IC 7408 1
2. X-OR GATE IC 7486 1
3. NOT GATE IC 7404 1
4. OR GATE IC 7432 1
5. IC TRAINER KIT - 1
6. PATCH CORDS - 23

THEORY:

HALF ADDER:
A half adder has two inputs for the two bits to be added and two outputs one from
the sum ‘ S’ and other from the carry ‘ c’ into the higher adder position. Above circuit is
called as a carry signal from the addition of the less significant bits sum from the X-OR
Gate the carry out from the AND gate.

FULL ADDER:
A full adder is a combinational circuit that forms the arithmetic sum of input; it
consists of three inputs and two outputs. A full adder is useful to add three bits at a time but
a half adder cannot do so. In full adder sum output will be taken from X-OR Gate, carry
output will be taken from OR Gate.

HALF SUBTRACTOR:
The half subtractor is constructed using X-OR and AND Gate. The half subtractor
has two input and two outputs. The outputs are difference and borrow. The difference can
be applied using X-OR Gate, borrow output can be implemented using an AND Gate and
an inverter.

FULL SUBTRACTOR:
The full subtractor is a combination of X-OR, AND, OR, NOT Gates. In a full
subtractor the logic circuit should have three inputs and two outputs. The two half
subtractor put together gives a full subtractor .The first half subtractor will be C and A B.
The output will be difference output of full subtractor. The expression AB assembles the
borrow output of the half subtractor and the second term is the inverted difference output
of first X-OR.

26
 HALF ADDER
TRUTH TABLE:

A B CARRY SUM

0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0

K-Map for SUM: K-Map for CARRY:

1
1

SUM = A’B + AB’ CARRY = AB

LOGIC DIAGRAM:

27
 FULL ADDER

TRUTH TABLE:

A B C CARRY SUM

0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1

K-Map for SUM

1 1

1 1

SUM = A’B’C + A’BC’ + ABC’ + ABC

K-Map for CARRY

CARRY = AB + BC + AC
28
LOGIC DIAGRAM:

FULL ADDER USING TWO HALF ADDER

HALF SUBTRACTOR

TRUTH TABLE:
A B BORROW DIFFERENCE

0 0 0 0
0 1 1 1
1 0 0 1
1 1 0 0

K-Map for DIFFERENCE

DIFFERENCE = A’B + AB’

K-Map for BORROW

BORROW = A’B
29
 LOGIC DIAGRAM

FULL SUBTRACTOR

TRUTH TABLE:
A B C BORROW DIFFERENCE

0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 1 0
1 0 0 0 1
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

K-Map for Difference

1 1

1 1

Difference = A’B’C + A’BC’ + AB’C’ + ABC

K-Map for Borrow

30
 Borrow = A’B + BC + A’C

LOGIC DIAGRAM:

FULL SUBTRACTOR USING TWO HALF SUBTRACTOR

PROCEEDURE:

(i) Connections are given as per circuit diagram.

(ii) Logical inputs are given as per circuit diagram.
(iii) Observe the output and verify the truth table.

RESULT:

Thus, the half adder, full adder, half subtractor and full subtractor
circuits are designed, constructed and verified the truth table using logic gates.
31
EXPERIMENT: DESIGN AND IMPLEMENTATION OF 4 BIT BINARY ADDER /
DATE: SUBTRACTOR USING IC 7483

AIM:
To study the 4 bit binary adder/subtractor using IC7483.

REQUIREMENTS:

S.No. Name of the apparatus Specifications Quantity

1 Digital Trainer kit - 1

2 OR gate IC 7432 1

3 AND gate IC 7408 1

4 Binary Adder / Subtractor IC 7483 2

5 Connecting wires - some

THEORY

The full adder/sub tractors are capable of adding/subtracting only two single digit binary
numbers along with a carry input. But in practice we need to add/subtract binary numbers, which are
much longer than just one bit. To add/subtract two n-bit binary numbers we need to use the n-bit parallel
subtractor/adder.

Binary adder: IC type 7483 is a 4-bit binary parallel adder/subtractor .The two 4-bit input binary
numbers are A1 through A4 and B1 through B4. The sum is obtained from S1 through S4. C0 is the
input carry and C4 the output carry. Test the 4-bit binary adder 7483 by connecting the power supply
and ground terminals. Then connect the four A inputs to a fixed binary numbers such as 1001 and the
B inputs and the input carry to five toggle switches. The five outputs are applied to indicator lamps.
Perform the addition of a few binary numbers and check that the output sum and output carry give the
proper values. Show that when the input carry is equal to 1, it adds 1 to the output sum.

Binary subtractor: The subtraction of two binary numbers can be done by taking the 2’s complement
of the subtrahend and adding it to the minuend. The 2’s complement can be obtained by taking the 1’s
complement and adding. To perform A-B, we complement the four bits of B, add them to the four bits
of A, and add 1 through the input carry. The four XOR gates complement the
bits of B when the mode select M=1(because x Θ 0 = x ) and leave the bits of B unchanged when
M=0(because x Θ 0 = x ) .Thus , when the mode select M is equal to 1, the input carry C0 is equal 1
and the sum output is A plus the 2’s complement of B. when M is equal to 0, the input carry is equal to
0 and the sum generates A+B.
Functional symbol for IC 7483:

Operand1 Operand2

B3 B2 B1 B0 A3 A2 A1 A0

Cout 4 bit IC 7483 Cin

Output

Pin Diagram of IC7483:

Circuit Diagram for 4-bit Binary adder/subtractor:

4-BIT BINARY ADDER:

4-BIT BINARY SUBTRACTOR

PROCEDURE:
1. Connections are given as per the circuit diagram.
2. Set mode M =0 such that the circuit will operate in addition mode.
3. Set the Value of inputs A as 1001 and B as 1001 note the sum and output carry.
4. Repeat the same step in step 3 by keeping M=1 such that circuit will operate in subtraction mode.

RESULT:
Thus the 4 bit Binary Adder / Subtractor using IC7483 is been implemented for both addition
and subtraction and the corresponding truth tables are verified.
EXPERIMENT:
DESIGN AND IMPLEMENTATION OF BCD ADDER
DATE:

AIM:
To design and implement the BCD adder by using IC7483.

REQUIREMENTS:

S.NO. Name of the apparatus Specifications Quantity

1 Digital Trainer kit - 1

2 OR gate IC 7432 1

3 AND gate IC 7408 1

4 Binary Adder / Subtractor IC 7483 2

5 Connecting wires - some

THEORY
The full adder/sub tractors are capable of adding/subtracting only two single digit binary
numbers along with a carry input. But in practice we need to add/subtract binary numbers, which are
much longer than just one bit. To add/subtract two n-bit binary numbers we need to use the n-bit parallel
subtractor/adder.
Binary adder: IC type 7483 is a 4-bit binary parallel adder/subtractor. The two 4-bit input binary
numbers are A1 through A4 and B1 through B4. The sum is obtained from S1 through S4. C0 is the
input carry and C4 the output carry. Test the 4-bit binary adder 7483 by connecting the power supply
and ground terminals. Then connect the four A inputs to a fixed binary numbers such as 1001 and the
B inputs and the input carry to five toggle switches. The five outputs are applied to indicator lamps.
Perform the addition of a few binary numbers and check that the output sum and output carry give the
proper values. Show that when the input carry is equal to 1, it adds 1 to the output sum.
Binary subtractor: The subtraction of two binary numbers can be done by taking the 2’s complement
of the subtrahend and adding it to the minuend. The 2’s complement can be obtained by taking the 1’s
complement and adding. To perform A-B, we complement the four bits of B, add them to the four bits
of A, and add 1 through the input carry. The four XOR gates complement the bits of B when the mode
select M=1(because x Θ 0 = x ) and leave the bits of B unchanged when M=0(because x Θ 0 = x ) .Thus
, when the mode select M is equal to 1, the input carry C0 is equal 1 and the sum output is A plus the
2’s complement of B. when M is equal to 0, the input carry is equal to 0 and the sum generates A+B.
Functional symbol for IC 7483:

Operand1 Operand2

B3 B2 B1 B0 A3 A2 A1 A0
Cout 4 bit IC 7483 Cin

Output

Pin Diagram of IC7483:

TRUTH TABLE FOR BCD ADDER:

K MAP

Y = S4 (S3 + S2)
LOGIC DIAGRAM OF BCD ADDER
PROCEDURE:
1. Connections are given as per the circuit diagram.
2. Set mode CE =0 such that the circuit will operate in addition mode.
3. Set the Value of inputs A as 1001 and B as 1001 note the sum and output carry.

RESULT:

Thus the BCD Adder using IC7483 is been implemented for and the corresponding truth tables
are verified.
EXPERIMENT:
DESIGN AND IMPLEMENTATION OF ENCODER
DATE:

AIM:

To construct and verify the 8 X 3 Encoder using logic gates.

REQUIREMENTS:

S. No Components / Equipment’s Specification Quantity

1. Digital IC trainer kit - 1

2. OR Gate IC7432 3

3. Connecting Wires - Sufficient Numbers

THEORY:

Digital Computers, Microprocessors and other digital systems are binary operated whereas our
language of communication is in decimal numbers and alphabetical characters only. Therefore, the need
arises for interfacing between digital system and human operators. To accomplish this task, Encoder is
used
Logic Diagram:

Truth Table:

INPUT OUTPUT

D0 D1 D2 D3 D4 D5 D6 D7 A B C

1 0 0 0 0 0 0 0 0 0 0

0 1 0 0 0 0 0 0 0 0 1

0 0 1 0 0 0 0 0 0 1 0

0 0 0 1 0 0 0 0 0 1 1

0 0 0 0 1 0 0 0 1 0 0

0 0 0 0 0 1 0 0 1 0 1

0 0 0 0 0 0 1 0 1 1 0

0 0 0 0 0 0 0 1 1 1 1

Outputs:
A = D4 + D5 + D6 + D7
B = D2 + D3 + D6 + D7
C = D1 + D3 + D5 + D7

1
PROCEDURE:
1. Construct the circuit as per the diagram
2. Switch on the power supply.
3. Apply the necessary input and observe the outputs to verify the truth table.

RESULTS:

Thus an 8 x 3 encoder is constructed and verified.

1
EXPERIMENT:
DESIGN AND IMPLEMENTATION OF DECODER
DATE:

AIM:
To design, construct the decoder circuits and implement the function F (A,B,C) = ∑(1,2,4,7) using the
decoder ICs and also driver along with seven segment LED display unit and verify the results.

REQUIREMENTS:

S. No. Components / Equipments Specification Quantity

1. Decoder IC 7447 1

2. Seven Segment Display Common Anode 1

3. Resistors 330Ω 7
4. IC Trainer Kit --- 1
5. Connecting Wires --- Required numbers

THEORY:
The process of taking some type of code and determining what it represents in terms of a recognizable
number or character is called decoding. A decoder is a combinational logic circuit that performs the decoding
function, andproduce an output that indicates the (meaning) of the input code. The decoder is an important
part of the system which selects the cells to be read from and write into. This particular circuit is called a
decoder matrix, or simplya decoder, and has a characteristic that for each of the possible 2n binary input
number which can be taken by the n input cells, the matrix will have a unique one of its 2 n output lines
selected.

Block Diagram

n 2n
Input Output

n×2n
Decoder

1
2 X 4 DECODER:
Block Diagram:

W0
2×4
X1 W1

X2 Decoder W2
W3

TRUTH TABLE:

INPUTS OUTPUTS
X2 X1 W0 W1 W2 W3
0 0 1 0 0 0
0 1 0 1 0 0
1 0 0 0 1 0
1 1 0 0 0 1

LOGIC CIRCUIT DIAGRAM:

1
7408 3 W0

2
1 2
X2 7404 4 7408 6
W1
5
3
7404 4 9
X1 7408 8
W2
10
12
7408 11
W3
13
3 X 8 DECODER:
Block Diagram:

Truth Table:
Logic Diagram:

Pin Diagram for 74138:

Truth Table for IC74138:

BCD-to-Seven Segment decoder :
The 7-segment LED display is the most popular display device used in digital systems. To use this device
the data that is in the BCD form has to be changed suitably. For this purpose a BCD to 7-segment decoder
is required. The IC7447 is a BCD to 7-segment pattern converter. The 7447 converts the four input bits
(BCD) to their corresponding 7-segment codes. The outputs of the 7447 are connected to the 7-segment
display.
A seven segment LED display contains 7 LEDs. Each LED is called a segmentand they are identified as
(a, b, c, d, e, f, g) segments.

For example if decimal 9 is to be displayed a, b, c, d, f, g must be 0 and the others must be 1

(For common anode type display units), if decimal 5 is to be displayed then a, f, g, c, d must be 0 and

the others must be 1.

Pin Diagram:

Connection Circuit Diagram:

Truth Table:

PROCEDURE:
1. Connect the circuit as per circuit diagram.
2. Apply the inputs to the IC7447(A, B, C&D).
3. Observe the output and verify the result.

RESULT:
Thus, the decoder, function implementation using decoder and driver unit along with 7
segment display unit is constructed and the results were verified.
EXPERIMENT: DESIGN AND IMPLEMENTATION OF MULTIPLEXER AND
DATE: DEMULTIPLEXER

AIM:
To design and implement multiplexer and demultiplexer using logic gates and implement using
multiplexer ICs.

REQUIREMENTS:

S.No. Name of the apparatus Specification Quantity

1 Digital Trainer kit - 1

2 OR gate IC7432 1

3 AND gate IC7411 1

4 NOT gate IC7404 1

5 Multiplexer ICs 74150, 74151 / 74154 1

6 Connecting wires - -

THEORY:
Multiplexer:
It has a group of data inputs and a group of control inputs. The control inputs are used to select one of
the data inputs and connected to the output terminal. It selects one information out of many information
lines and directed to a single output line.
Demultiplexer:
Demultiplexers perform the opposite function of multiplexers. They transfer a small number of
information units (usually one unit) over a larger number of channels under the control of selection
signals. Fig shows a 1-line to 2-line Demultiplexer circuit. Construct this circuit; connect an LED to
each of the outputs D0 and D1. Set the select signal S to logic 1 or logic 0, and toggle the input I between
logic 1 and logic 0. Which output followed the input when S = 1 and S = 0.
4:1 MULTIPLEXER:

BLOCK DIAGRAM

Circuit Diagram:

Truth Table:
 1:4 DEMULTIPLEXER:
BLOCK DIAGRAM

Circuit Diagram:

Truth Table:
PIN DIAGRAM FOR IC 74150 (16:1 MUX):

TRUTH TABLE:
PIN DIAGRAM FOR IC 74151(8:1MUX):

LOGIC DIAGRAM:

TRUTH TABLE:
PROCEDURE:
1. Connections are given as per in the circuit diagram.
2. Inputs are given through the logic switches.
3. Outputs are noted and verified with truth table

RESULT:
Thus the truth table of multiplexer and demultiplexer was studied and verified using logic gates
also the given Boolean function were implemented successfully.
EXPERIMENT:
DESIGN AND IMPLEMENTATION OF SYNCHRONOUS COUNTER
DATE:
AIM:
To construct and verify the synchronous up/down counters.

REQUIREMENTS:

S. No.Components / Equipments Specification Quantity

1. Digital IC trainer kit ---- 1

2. JK Flip-Flop, AND Gate IC 7473,7408 2,2

3. Connecting wires ---- Sufficient Nos

THEORY:
Synchronous Counter
Clock input is applied simultaneously to all flip-flops. The output of the first FLIP-FLOP is
connected to the input of second FLIP-FLOP and so on.

Design of synchronous counter

Step 1: Find the number of flip-flops required. For an n-bit counter, n- flip-flops is required.
Step 2: Write the count sequence in tabular form.
Step 3: Determine the flip-flop inputs, which must be present for the desired next State from the present
state using excitation table of flip-flops.
Step 4: Prepare K-map for each flip-flop input in terms of flip-flop output as input Variables. Simplify
the K-map and obtain the minimized expressions.
Step 5: Connect the circuit using the flip-flops

CIRCUIT DIAGRAM:
Design of 3-bit synchronous up Counter :
Design of 3-bit synchronous down counter:

Truth Table:

3 Bit Synchronous UP 3 Bit Synchronous DOWN

Counter Counter

Clock Q2 Q1 Q0 Clock Q2 Q1 Q0

0 0 0 0 0 1 1 1

1 0 0 1 1 1 1 0

2 0 1 0 2 1 0 1

3 0 1 1 3 1 0 0

4 1 0 0 4 0 1 1

5 1 0 1 5 0 1 0

6 1 1 0 6 0 0 1

7 1 1 1 7 0 0 0
4 – Bit Synchronous down counter:

Pin Diagram
Truth Table:

4 Bit Synchronous UP 4 Bit Synchronous DOWN

Counter Counter

Clock Q3 Q2 Q1 Q0 Clock Q3 Q2 Q1 Q0

0 0 0 0 0 0 1 1 1 1

1 0 0 0 1 1 1 1 1 0

2 0 0 1 0 2 1 1 0 1

3 0 0 1 1 3 1 1 0 0

4 0 1 0 0 4 1 0 1 1

5 0 1 0 1 5 1 0 1 0

6 0 1 1 0 6 1 0 0 1

7 0 1 1 1 7 1 0 0 0
1
8 1 0 0 0 8 0 1 1
0
9 1 0 0 1 9 0 1 1
1
10 1 0 1 0 10 0 1 0
0
11 1 0 1 1 11 0 1 0
1
12 1 1 0 0 12 0 0 1
0
13 1 1 0 1 13 0 0 1
1
14 1 1 1 0 14 0 0 0
0
15 1 1 1 1 15 0 0 0
PROCEDURE:
1. The connections are made as per the circuit diagram.
2. Switch on the power supply.
3. The input is given at the appropriate terminal and corresponding output is observed and truth
table is verified.

RESULT:
Thus the counters were constructed and their truth tables verified.
EXPERIMENT: IMPLEMENTATION OF SISO, SIPO, PISO AND PIPO SHIFT
DATE: REGISTERS
AIM:
To implement the 4 bit shift register using flip flops and to study the operations in the
following modes.
(i) Serial in serial out
(ii) Serial in parallel out
(iii) Parallel in parallel out
(iv) Parallel in serial out
REQUIREMENTS:
S.No. Name of the apparatus Range Quantity
1 Digital Trainer kit 1
2 D Flip Flop IC 7474 2
3 Connecting wires some

THEORY:
SHIFT REGISTER:
A register is a device capable of storing a bit. The data can be serial or parallel. The register can convert
a data from serial to parallel and vice versa shifting then digits to left and right is the important aspect
for arithmetic operations,
A register capable of shifting its binary information either to the right or to the left is called a
shift register. An N bit shift register consists of N flip-flops and the gates that control the shift operation.
A shift register can be used in four different configurations depending upon the way in which the data
are entered into and taken out of it. These four configurations are:
a. Serial-input, Serial-output
. b. Parallel-input, Serial-output
c. Serial-input, parallel-output
d. Parallel-Input, parallel-output
The serial input is a single line going to the input of the leftmost flip-flop of the register. The serial
output is a single line from the output of the rightmost flip-flop of the register, so that the bits stored in
the register can come out through this line one at a time. The parallel output consists of N lines, one for
each of the flip-flops in the register, so the information stored in the register can be inspected through
these lines all at once.
PIN DIAGRAM:

Logic Diagram for Serial in Serial out:

Truth Table for Serial In Serial Out (SISO):

Logic Diagram for Serial in Parallel Out:

Truth Table for Serial In Parallel Out (SIPO):

Input Data: 1011

Logic Diagram for Parallel In Parallel Out:

Truth Table for Serial In Parallel Out (SIPO):

Logic Diagram for Parallel in Serial out:

TRUTH TABLE FOR PISO SHIFT REGISTER:

PROCEDURE:
1. The flip-flop is connected using connecting wires as shown in the circuit.
2. The flip flop are then reset to zero internally with the help of reset to set inputs.
3. The bits are shifted in by giving suitable clock input.
4. Thus the truth table is then verified.

RESULT:
Thus, the operation of 4 bit shift register for SISO, SIPO, and PIPO was studied and verified.
EXPERIMENT:
IMPLEMENTATION OF MOD-10 RIPPLE COUNTER
DATE:

AIM:
To construct and verify Mod-10 Ripple Counters.
APPARATUS REQUIRED:
S.No. Name of the apparatus SPECIFICATION Quantity

1 Digital Trainer kit 1

2 JK Flip Flop IC 7473 2

3 NAND Gate IC7400 1

4 Connecting wires Some

THEORY:
Counters are a group of flip flops connected together to perform counting operation. According
to the way the flip flops are clocked, there are two types of flip flops,
a. Asynchronous Counter
b. Synchronous Counter
In asynchronous counter, the flip flop is clocked by the external clock pulse. Then each
successive flip flop are clock by Q or Q’ output of the previous flip flop. In 4 bit ripple counter, the total
number of states is 16 (24) and this varies from 00002 to 11112 . If the counters are designed with number
of sequence which is less than 2, then those counters are said to be Mod-N counters where N denotes
number of sequence. Thus in Mod-10 counter, total number of states is 10 and number of flip flops are
4. Similarly in Mod-12 counter, total number of states is 12 and number of flip flops are 4.

CIRCUIT DIAGRAM OF MOD-10 RIPPLE COUNTERS

PROCEDURE:
1. Verify the flip flop.
2. Make the connections as per the circuit diagram.
3. Switch on VCC and apply various combinations of input according to truth table.
4. By applying the clock pulse, all the input combinations are given and the outputs are
verified with the truth table.
RESULT:
Thus the Mod 10 ripple counter was designed and constructed successfully.
EXPERIMENT:
UNIVERSAL SHIFT REGISTER
DATE:

AIM:
To study and verify the load, shift and rotate operation of a 4-bit shift register.

EQUIPMENT/APPARATUS USED:

S. No. Name of the equipment Range/Rating Quantity

1. Digital IC Trainer .... 1
2. IC 74195 ... 1
3. Connecting Wires ... As Required

THEORY:

A register is a group of binary storage cells capable of holding binary information. A group of flip
flops constitutes a register, since each flip-flop can work as a binary cell. An n-bit register, has n flip-flops
and is capable of holding n-bits of information. In addition to flip-flops a register can have a combinational
part that performs data-processing tasks.

SHIFT REGISTER:

A register capable of shifting its binary contents either to the left or to the right is called a shift register.
The shift register permits the stored data to move from a particular locationto some other location within
the register. Registers can be designed using discrete flip-flops (S- R, J-K, and D-type). The data in a shift
register can be shifted in two possible ways: (a) serial shifting and (b) parallel shifting. The serial shifting
method shifts one bit at a time for each clock pulse in a serial manner, beginning with either LSB or MSB.
On the other hand, in parallel shiftingoperation, all the data (input or output) gets shifted simultaneously
during a single clock pulse. Hence, we may say that parallel shifting operation is much faster than serial
shifting operation.
4- bit Universal Shift Register: IC 74195 is a 4-bit TTL MSI having both serial/parallel input and
serial/parallel output capability. The pinout diagram of IC 74195 is shown in Figure 1.
When the SH / LD input is LOW, the data on the parallel inputs, i.e., A, B, C, and D are entered
synchronously on the positive transition of the clock. When SH / LD is HIGH, the stored data willshift right
(QA to QD) synchronously with the clock. J and K are the serial inputs to the first stageof the register (QA);
QD can be used for getting a serial output data. The active low clear is asynchronous.
Example:
Right Shift Operation: :Input data: 1011
Clock QA QB QC QD
0 1 0 1 1
1 0 1 0 1
2 0 0 1 0
3 0 0 0 1
4 0 0 0 0
1 0 0 1 1 0 0 1

0 1 0 0 1 1 0 0
PROCEDURE:
1. Load data using parallel loading
2. Use clock 1(9)
3. Mode Control 6 OFF (0) connect logic input switch
4. Serial input 1 OFF (0) connect logic input switch
5. Press the clock button

Example:
Rotate Right Operation: Input data: 1011

Clock QA QB QC QD
0 1 0 1 1
1 1 1 0 1
2 1 1 1 0
3 0 1 1 1
4 1 0 1 1

1 0 1 1 0 0 0 1
PROCEDURE:

1. Load data using parallel loading

2. Use clock 1(9)
3. Mode Control 6 OFF (0) connect logic input switch
4. Serial input 1 connects to the QD logic output switch
5. Press the clock button

RESULT:
Thus the 4-bit Universal Shift Register was studied successfully.