QIS COLLEGE OF ENGINEERING AND TECHNOLOGY

(AUTONOMOUS)
Permanent Affiliation: JNTU-Kakinada | UGC-Recognized
Vengamukkapalem(V), Ongole, Prakasam dist., Andhra Pradesh-523272

DEPARTMENT OF
ELECTRONICS AND COMMUNICATION ENGINEERING

LABORATORY MANUAL

VLSI DESIGN
for
III year II Semester
A.Y.2024-2025

Prepared by
Dr. A MURALI
M.Tech (IIT-M), M.Tech (JNTU-H), PGDTC (HCU), Ph. D

Assoc Prof in ECE and Assoc Dean (Academics)

QISCET VLSI DESIGN LABORATORY DEPT OF ECE 1

 QIS COLLEGE OF ENGINEERING AND TECHNOLOGY (AUTONOMOUS)
Permanent Affiliation: JNTU-Kakinada | UGC-Recognized
Vengamukkapalem(V), Ongole, Prakasam dist., Andhra Pradesh-523272

DEPARTMENT OF
ELECTRONICS AND COMMUNICATION ENGINEERING

CERTIFICATE

Name of the Faculty : Dr. A. MURALI

Name of the Subject : VLSI DESIGN LAB (Developed/Updated)
Subject Code : 20E05305
Academic Year : 2024-25
Regulation : R-20
Department : Electronics and Communication Engineering
Program : B. Tech
Year : 3rd
Semester : 2nd

IQAC Committee

Signature(s): Signature(s):
Name(s): Name(s):

Faculty signature HOD ECE

QISCET VLSI DESIGN LABORATORY DEPT OF ECE 2

 QIS COLLEGE OF ENGINEERING AND TECHNOLOGY (AUTONOMOUS)
Permanent Affiliation: JNTU-Kakinada | UGC-Recognized
Vengamukkapalem(V), Ongole, Prakasam dist., Andhra Pradesh-523272

Vision of the Institute

To provide high quality education by introducing innovation and creativity in academics and research
with societal commitment and to be the knowledge hub in the region and to produce skilled human
resources with strong leadership capabilities to kindle the knowledge driven economy of the nation and
to make ethically strong citizens.

Mission of the Institute

The college is committed to develop through good governance, resource building, quality teaching-
learning with strong fundamentals high impact research, constructive community engagement, well
trained skilled human power in line with National development, capacity building, knowledge
management and the continuing education programmes.

Vision of the Department

To be a center of high quality education and research in the field of Electronics and Communication
Engineering in order to fulfill the worldwide needs and to produce entrepreneurs with a synthesis of
ethical principles and societal goals.

Mission of the Department

To impart quality education to meet the needs of the industry and research in the field of Electronics
and Communication Engineering
To encourage an environment conducive to innovation, creativity, team spirit and entrepreneurial
leadership in Electronics and Communication Engineering.
To foster networking with Alumni, Software Industries, Institutes and other stakeholders for effective
interaction.
To practice and promote high standards of ethical values through societalcommitment.

QISCET VLSI DESIGN LABORATORY DEPT OF ECE 3

 QIS COLLEGE OF ENGINEERING AND TECHNOLOGY (AUTONOMOUS)
Permanent Affiliation: JNTU-Kakinada | UGC-Recognized
Vengamukkapalem(V), Ongole, Prakasam dist., Andhra Pradesh-523272

PROGRAM EDUCATIONAL OBJECTIVES (PEOs)

PEO 1: LEARN AND INTEGRATE: Graduates must have understanding of applied and fundamental
engineering sciences in order to comprehend engineering principles, which are required to create and
solve problems pertaining to Electronics and Communication Engineering.

PEO 2: THINK AND CREATE: Students graduating from this programme are expected to have
knowledge in the areas of experimentation, analysis, and synthesis pertaining to Electronics and
Communication Engineering. Classes that focus on design, innovation, and the creation of unique
products and solutions to real-world challenges.

PEO 3: PRACTICE CITIZENSHIP: In order to fulfill the requirements of both industry and society,
graduates are expected to have skills in management and entrepreneurship, an ethical and professional
mindset, and a multidisciplinary approach.

PEO 4: EXPERTISE: Graduates are encouraged to pursue more education, participate in research, and
engage in lifelong learning in order to adapt themselves to the rapidly evolving technological
landscape and to increase their chances of finding success in engineering positions around the world.

QISCET VLSI DESIGN LABORATORY DEPT OF ECE 4

 QIS COLLEGE OF ENGINEERING AND TECHNOLOGY (AUTONOMOUS)
Permanent Affiliation: JNTU-Kakinada | UGC-Recognized
Vengamukkapalem(V), Ongole, Prakasam dist., Andhra Pradesh-523272

PROGRAM OUTCOMES (POs) & PROGRAM SPECIFIC OUTCOMES (PSOs)

PO (1). Engineering knowledge: Apply the knowledge of mathematics, science, engineering
fundamentals, and an engineering specialization to the solution of complex engineering problems.
PO (2). Problem analysis: Identify, formulate, review research literature, and analyze complex
engineering problems reaching substantiated conclusions using first principles of mathematics, natural
sciences, and engineering sciences.
PO (3) Design/development of solutions: Design solutions for complex engineering problems and
design system components or processes that meet the specified needs with appropriate consideration
for the public health and safety, and the cultural, societal, and environmental considerations.
PO (4). Conduct investigations of complex problems: Use research-based knowledge and research
methods including design of experiments, analysis and interpretation of data, and synthesis of the
information to provide valid conclusions.
PO (5). Modern tool usage: Create, select, and apply appropriate techniques, resources, and modern
engineering and IT tools including prediction and modeling to complex engineering activities with an
understanding of the limitations.
PO (6) The engineer and society: Apply reasoning informed by the contextual knowledge to assess
societal, health, safety, legal and cultural issues and the consequent responsibilities relevant to the
professional engineering practice.
PO (7). Environment and sustainability: Understand the impact of the professional engineering
solutions in societal and environmental contexts, and demonstrate the knowledge of, and need for
sustainable development.
PO (8). Ethics: Apply ethical principles and commit to professional ethics and responsibilities and
norms of the engineering practice.
PO (9). Individual and team work: Function effectively as an individual, and as a member or leader
in diverse teams, and in multidisciplinary settings.

PO (10). Communication: Communicate effectively on complex engineering activities with the

engineering community and with society at large, such as, being able to comprehend and write

QISCET VLSI DESIGN LABORATORY DEPT OF ECE 5

 effective reports and design documentation, make effective presentations, and give and receive clear
instructions.
PO (11). Project management and finance: Demonstrate knowledge and understanding of the
engineering and management principles and apply these to one’s own work, as a member and leader in
a team, to manage projects and in multidisciplinary environments.
PO (12). Life-long learning: Recognize the need for, and have the preparation and ability to engage in
independent and life-long learning in the broadest context of technological change.
PSO 1: Domain Applied: An ability to design and develop a process to meet the wide range of
applications in electronic and communication engineering domain by applying the fundamental and
applied concepts and as well as other related areas of expertise.
Resource Applied: An ability to fit into any industry, solve problems alone or as a team, and create
jobs for self and others as an entrepreneur.
PSO 2: Research Applied: An ability to handle the cutting-edge technical hardware and software
tools to tackle Electronics and Communication Engineering challenges, taking into account the
requirements of both society and industry.

QISCET VLSI DESIGN LABORATORY DEPT OF ECE 6

 QIS COLLEGE OF ENGINEERING AND TECHNOLOGY (AUTONOMOUS)
Permanent Affiliation: JNTU-Kakinada | UGC-Recognized
Vengamukkapalem(V), Ongole, Prakasam dist., Andhra Pradesh-523272

COURSE OBJECTIVE (S)

CO. No Course Objective (s)

CO 1 To learn the MOS Process Technology
CO 2 To understand the operation of MOS devices
CO 3 Understand and learn the characteristics of CMOS circuit construction.
CO 4 Describe the general steps required for processing of CMOS integrated circuits.
CO 5
CO 6

COURSE OUTCOMES:
After going through this course, the student will be able to

CO. No Course Outcomes (COs)

CO 1 Design and analyse basic logic gates using Standard EDA Tools
CO 2 Design and analyse basic Combinational circuits using Standard EDA Tools
CO 3 Design and analyse basic Sequential circuits using Standard EDA Tools
CO 4 Design and analyse basic Oscillator circuits using Standard EDA Tools
CO 5 Design and analyse registers using Xilinx and SPARTAN 6 FPGA Kit.
CO 6 Design and analyse counters using Xilinx and SPARTAN 6 FPGA Kit.

QISCET VLSI DESIGN LABORATORY DEPT OF ECE 7

 CO-PO MATRICES OF COURSE:

CO – PO Affinity Map

PO PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12 PSO1 PSO2
CO
CO 1 1 1 2 2
CO 2 1 2 2 2
CO 3 1 2 2 2
CO 4 1 1 2 2
CO 5 1 1 2 2 2
CO 6 1 1 2 2 2

3 – Strong, 2 Moderate, 1 –weak

Evaluation and Grading

Internal evaluation (30 Marks) External evaluation (70 Marks)

Component Marks Component Marks
Day-to-day performance 10 Semester End Examination script 30
Record work 5 Conduction of experiment 30
Internal lab exam 5 10
Viva-voce
Conduction of experiment 5
Viva-voce 5
Total 30 Total 70

QISCET VLSI DESIGN LABORATORY DEPT OF ECE 8

 QIS COLLEGE OF ENGINEERING AND TECHNOLOGY (AUTONOMOUS)
Permanent Affiliation: JNTU-Kakinada | UGC-Recognized
Vengamukkapalem(V), Ongole, Prakasam dist., Andhra Pradesh-523272

GENERAL INSTRUCTIONS TO STUDENTS

1. While entering the Laboratory, the students should follow the dress code (Wear shoes, College
uniform, Female students should tie their hair back & Male students should be shirt tuck-in).
2. The students should bring their observation note book, Lab manual, record note book, calculator,
and necessary stationary items.
3. While sitting in front of the system, check all the cable connections and Switch on the computer.
4. If a student notices any fluctuations in power supply, immediately the same thing is to be brought to
the notice of technician/lab in charge.
5. At the end of practical class the system should be switch off safely and arrange the chairs properly.
6. Each program after completion should be written in the observation note book and should be
corrected by the lab in charge on the same day of the practical class.
7. Each experiment should be written in the record note book only after getting signature from the lab
in charge in the observation note book.
8. Record should be submitted in the successive lab session after completion of the experiment.
9. Students will not be permitted to attend the laboratory unless they bring the practical record fully
completed in all respects pertaining to the experiments conducted in the previous session.
10. They should obtain the signature of the staff-in –charge in the observation book after completing
each experiment.
11. Practical record should be neatly maintained.
12. Ask lab Instructor for assistance for any problem.
13. Do not download or install software without the assistance of laboratory Instructor.
14. Do not alter the configuration of system.
15. 100% attendance should be maintained for the practical classes.

QISCET VLSI DESIGN LABORATORY DEPT OF ECE 9

 QIS COLLEGE OF ENGINEERING AND TECHNOLOGY (AUTONOMOUS)
Permanent Affiliation: JNTU-Kakinada | UGC-Recognized
Vengamukkapalem(V), Ongole, Prakasam dist., Andhra Pradesh-523272

DEPARTMENT OF
ELECTRONICS AND COMMUNICATION ENGINEERING
B.TECH : III Year
SEMISTER : II
Academic Year : 2024-25
LABORATORY: VLSI Design
LABORATORY CODE: 20E05305
_________________________________________________________________________________

LIST OF EXPERIMENTS
1. Design and implementation of an inverter
2. Design and implementation of universal gates
3. Design and implementation of full adder
4. Design and implementation of full Subtractor.
5. Design and implementation of RS-latch
6. Design and implementation of D-latch
7. Design and implementation asynchronous counter
8. Design and Implementation of static RAM cell
9. Design and Implementation of differential amplifier
10. Design and Implementation of ring oscillator
11. Design and implementation of UNIVERSAL SHIFT REGISTER on SPARTAN-6 FPGA.
12. Design and implementation of Johnson Counter on SPARTAN-6 FPGA.

Additional Experiments

QISCET VLSI DESIGN LABORATORY DEPT OF ECE 10

 QIS COLLEGE OF ENGINEERING AND TECHNOLOGY (AUTONOMOUS)
Permanent Affiliation: JNTU-Kakinada | UGC-Recognized
Vengamukkapalem(V), Ongole, Prakasam dist., Andhra Pradesh-523272

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

INDEX
S No Date Expt Page Name of the Experiment Faculty Marks Remarks
No No Signature

QISCET VLSI DESIGN LABORATORY DEPT OF ECE 11

 QIS COLLEGE OF ENGINEERING AND TECHNOLOGY (AUTONOMOUS)
Permanent Affiliation: JNTU-Kakinada | UGC-Recognized
Vengamukkapalem(V), Ongole, Prakasam dist., Andhra Pradesh-523272

OVERVIEW OF VLSI DESIGN LAB

INTRODUCTION
This manual is intended to introduce microelectronic designers to the Cadence Design Environment,
and to describe all the steps necessary for running the Cadence tools at the QISCET, Department of
Electronics and Communication Engineering.
Cadence is an Electronic Design Automation (EDA) environment that allows integrating in a single
framework different applications and tools (both proprietary and from other vendors), allowing to
support all the stages of IC design and verification from a single environment. These tools are
completely general, supporting different fabrication technologies. When a particular technology is
selected, a set of configuration and technology-related files are employed for customizing the
Cadence environment. This set of files is commonly referred as a design kit. It is not the objective of
this manual to provide an in-depth coverage of all the applications and tools available in Cadence.
Instead, a detailed introduction to those required for an analog designer, from the conception of the
circuit to its physical implementation, is provided. References to other manuals and information
sources with a deeper treatment of these and other Cadence tools are also provided.

CADENCE
The Cadence Development System consists of a bundle of software packages such as schematic
editors, simulators, and layout editors. This software manages the development process for analog,
digital, and mixed-mode circuits. In this course, we will strictly use the tools associated with analog
circuit design.
All the Cadence design tools are managed by a software package called the Design Framework II.
This program supervises a common database which holds all circuit information including schematics,
layouts, and simulation data. From the Design Framework II also known as the "framework", we can
invoke a program called the Library Manager which governs the storage of circuit data. We can
access libraries and the components of the libraries called cells. Also, from the framework we can
invoke the schematic entry editor called "Composer". Composer is used to draw circuit diagrams and
draw circuit symbols.

QISCET VLSI DESIGN LABORATORY DEPT OF ECE 12

 A program called "Virtuoso Layout Suite" is used for creating integrated circuit layouts. The layout is
used to create the masks which are used in the integrated circuit fabrication process.
Finally, circuit simulation is handled through an interface called Analog Design Environment (ADE).
This interface can be used to invoke various simulators including Hspice, Spectre, and Verilog. We
will be using the Spectre simulator in this course.

ANALOG IC DESIGN FLOW AND REQUIRED TOOLS

Fig. 1 shows the basic design flow of an analog IC design, together with the Cadence tools required
in each step.
First, a schematic view of the circuit is created using the Cadence Composer Schematic Editor.
Alternatively, a text netlist input can be employed. Then, the circuit is simulated using the Cadence
Affirma analog simulation environment. Different simulators can be employed, some sold with the
Cadence software (e.g., Spectre) some from other vendors (e.g., HSPICE) if they are installed and
licensed.
Once circuit specifications are fulfilled in simulation, the circuit layout is created using the Virtuoso
Layout Editor. The resulting layout must verify some geometric rules dependent on the technology
(design rules). For enforcing it, a Design Rule Check (DRC) is performed. Optionally, some electrical
errors (e.g. shorts) can also be detected using an Electrical Rule Check (ERC). Then, the layout
should be compared to the circuit schematic to ensure that the intended functionality is implemented.
This can be done with a Layout Versus Schematic (LVS) check. All these verification tools are
included in the Diva software in Cadence (more powerful Cadence tools can also be available, like
Dracula, or Assura in deep submicron technologies).
Finally, a netlist including all layout parasitics should be extracted, and a final simulation of this
netlist should be made. This is called a Post-Layout simulation, and is performed with the same
Cadence simulation tools.
Once verified the layout functionality, the final layout is converted to a certain standard file format
depending on the foundry (GDSII, CIF, etc.) using the Cadence conversion tools.

QISCET VLSI DESIGN LABORATORY DEPT OF ECE 13

 Cadence Design Environment

Most of the commands in Cadence can be accessed in multiple ways: pull-down menus, shortcut keys,
buttons in toolbars, etc. The shortcut keys can be found from the pull-down menus as well.
List of the frequently used shortcut KEYS
Key Function Key Function

q Edit property of Object i Create Instance

w Add wires r Rotate
m Move c Copy
z Zoom in Z Zoom Out
u Undo b Return
e Display f To see full view
g To see the errors and warnings
Shift e To view the inner circuit Ctrl e To come out of it
The most frequently used key in Cadence is ESC. It is used to cancel on-going commands.

QISCET VLSI DESIGN LABORATORY DEPT OF ECE 14

 CADENCE Tool Quick Start Tutorial
Part –A: CADENCE VIRTUOSO - SIMULATION STEPS

Step by step procedure for simulation and layout design:

1. Restart the windows and select the Redhat OS for opening the cadence software
2. Give the password as “student” to open the software.
3. Make a right click on the Desktop and select the option “Create Folder”
4. Name the folder, for example, we have named it as “----------” and Open the created folder and you
get the window.
FOR INITIALISING csh & SOURCING cshrc:
1. Make a right click and select the option “Open in Terminal”
2. In that terminal Type the command “csh” to initialize shell and source the cshrc file with the
command “source /home/cad/cshrc” or “source /cad/cshrc” or “source /home/install/cshrc”.
INVOKING VIRTUOSO:
3. Next we get a display “Welcome to Cadence Tools Suite”.
CREATE A LIBRARY:
In virtuoso’s top menu, select “Tools” and select “Library Manager”.
1. From the top menu of the Library Manager, select “File -> New -> Library” to create a new library
for a new design and We’ll get a “New Library” form where we can name the library.
2. Select “OK” after the library is named. Select “Technology File...”
3. We get a form “Technology File for New Library”. Select the option “Attach to an existing
technology library”.
4. Select the respective Technology Node from the list of libraries. For example, we have selected
“gpdk045” or “gpdk090” or “gpdk180”
CREATE A CELL:
1. Before creating a cell, make sure that the created library is selected. Only then the created cell can
be viewed under the respective library. To create a Cell View, select File -> New -> Cell View.
2. Now we get a “New File” from as given in Figure-15 and we can name the Cell and check the
Library, View and Type of the respective Cell that is to be created.
3. Next we get the We get the Virtuoso Schematic Editor.
ADD AN INSTANCE:

QISCET VLSI DESIGN LABORATORY DEPT OF ECE 15

 1.To add an instance to the circuit, select “Create -> Instance”. We can also use the bin key ‘I’ or the
icon and We get the “Add Instance”.
2. Select “Browse” option we get the “Library Manager” to choose the transistors required for the
circuit and the type of view for the respective component from the respective Technology Library.
3. After selecting the component, we get its properties like Length, Width, Multipliers, etc.,. Select
“Hide” at the end of the form, we can have a view of the transistor in the Schematic Editor.
4. ADD PIN: To include pins to the circuit, select “Create -> Pin”. We get a form.We can also use
the bin key ‘P’ or the icon.
5. We name the pins and select its direction and Place the pins by a left click on the mouse and the
circuit can be viewed.
6. ADD WIRE: Connect the pins and the components with the help of wire. Select “Create -> Wire”.
We can also use the bin key ‘W’ or the icon.
7. SAVE THE DESIGN: After completing the design, it is mandatory to save the design before we
move ahead to Simulation. We have two options, “Save” and “Check and Save”.
SYMBOL CREATION: To create a symbol for the circuit, select “Create -> Cell view -> From Cell
view”.
1. Check the Library Name, Cell Name, From View Name, To View Name, etc., and select OK.
2. We get the “Symbol Generation Options” window. We are free to decide upon the pin locations
with options like Left Pins, Right Pins, Top Pins and Bottom Pins.
3. After naming the Left, Right, Top and Bottom Pins select OK. The tool opens a “Virtuoso Symbol
Editor” window which shows a temporary view of the symbol based on the pins assigned.
4. The symbol shown can be customized with the help of drawing tools.
5. To create custom symbol, remove the inner rectangle (green) and then using drawing tools, custom
symbol can be created.
6. To remove the inner rectangle (green), place the mouse pointer within the rectangle so that the
entire rectangle gets highlighted make a left click so that the entire rectangle gets selected as in and
click on delete in the keyboard to remove the rectangle so that it is removed.
7. Since Inverter design is taken as an example in this manual, the focus is on creating its symbol. To
create a triangle, use “Create Line” among the drawing tools and the way triangle is created is as
similar as how wiring is done in the schematic.
8. To create a bubble, use “Create Circle” option and decide a point, make a left click to expand the
circle and again make a left click to fix its size.

QISCET VLSI DESIGN LABORATORY DEPT OF ECE 16

 9. After creating the symbol, save the symbol using the “Check & Save”.
TESTBENCH CIRCUIT FOR SIMULATION:
1.To create a testbench circuit, a new Cellview with a different Cell Name should be created.
2. To include the created symbol, use the “Add Instance” option and select the respective library and
cell as using the browse option and then the symbol should appear in schematic editor with the mouse
pointer and Create an output pin.
3. To include supply voltage and input signal sources, “Add Instance” option shall be used. Browse
to the “analogLib” library, select the Cell as “vdc”, View as “symbol” and click on “Tab” key in
the keyboard to get the device properties.
4. Mention the appropriate “DC voltage” based on the specification or technology node. Similarly,
for an input source, (for example) “vpulse” is considered and parameters like Voltage 1, Voltage 2,
Period, Delay time, Rise time, Fall time and Pulse width are mentioned.
5. Similarly, “gnd” terminal shall be included to the circuit and the complete circuit.

FUNCTIONAL SIMULATION:
1. To simulate the design, Launch “ADE L” and We get a window and following options are to be
verified: (1) Simulator – to make sure that Spectre is the simulator selected.
2. (2) Model Libraries & Process Corners – to make sure that “.scs” file of the respective technology
node has been selected.
3. To analyze the circuit, select “Analyses” from the top menu in ADE L and under Analyses, select
“Choose”.
4. To set up a “Transient Analysis”, select “tran” under “Analysis” mention the “Stop Time” and
“Accuracy Defaults” as in and select “OK”.
5. The analyses chosen and the arguments that had been set up can be seen under “Analyses” tab in
the ADE L window. Similarly, rest of the analyses can be performed based on designer’s demands.
6. To setup the simulation, select “Outputs” from the ADE L window and select “Setup” under
Outputs option.
7. We get a “Setting Outputs” window select “From Design” which would bring back the testbench
circuit created for the simulation process.
8. Select the input wire and output wire and in ADE L, they are supposed to be displayed under
“Outputs” option.

QISCET VLSI DESIGN LABORATORY DEPT OF ECE 17

 9. To run the simulation, select “Simulation” from ADE L and select the option “Netlist and Run”.
The design is simulated and waveforms are seen.
10. Input signals and Output signals can be seen separately by selecting “Graph -> Split All Strips”.
11. To save the simulation state, select “Session” under ADE L, select “Save State” we get a
“Saving State” window. Select “Cellview” and select “OK” to save the state.The simulation state
and testbench circuit are viewed.

LAYOUT:
1.Open the schematic through the Library Manager and select “Launch -> Layout XL” and A
“Startup Option” window pops up as in Figure-58. Select “Create New” under Layout tab,
“Automatic” under Configuration tab and select OK.
2. A “New File” window pops up. No changes are to be made, so select OK. Virtuoso Layout Suite
XL Editing window can be seen and to import the circuit components, select “Connectivity ->
Generate -> All From Source”.
3. Select OK in the “Generate Layout” window and the components of the circuit can be seen and
Select “Shift + F” to have a view of all the terminals of the transistors.
4. The blue colored box surrounding the circuit components is the PR (Placement & Routing)
Boundary. PR-Boundary can be shifted using the shortcut “S”.
5. To shift the PR-Boundary, place the mouse pointer close to the respective boundary so that it gets
highlighted and make a left mouse click to select the boundary, use the mouse or arrow (up, down,
left or right) keys to shift the boundary.
6. To attach “Bulk” terminal to the transistors, select the particular transistor by a left mouse click ,
make a right mouse click and select “Properties”.
7. select “Parameter -> Bodytie Type -> Integrated (or) Detached -> Left Tap (or) Right Tap”
and select OK. Bulk terminal of that transistor can be seen. Repeat the above steps for rest of the
transistors to include the Bulk terminal.
8. This is mandatory for PMOS transistors in gpdk090 and gpdk045, but for PMOS transistors in
gpdk180, it has an N-Well by default.
9. To create an N-Well, select the respective layer from the “Layers” tab on the left-hand side of the
Virtuoso Layout Editor.

QISCET VLSI DESIGN LABORATORY DEPT OF ECE 18

 10. Select “R” to create N-Well in the shape of a rectangle surrounding the PMOS transistor and The
PMOS transistor is placed within the N-Well and to complete routing between the components, we
can use “P” which denotes “Path” in the layout and is meant for routing process.
11. When the mouse pointer is taken closer to any of the terminals of the components, the terminal
gets highlighted with a yellow color bold line, make a left click to start the path segment from one
terminal to another.
12. For routing between two different layers, usage of “Via” is mandatory. There are two options to
place a via. Start routing from the layer of interest, make a right-click, select “Via Down To ..” and
select the layer of interest (or) select “Create” from the top menu, select “Via”, select the respective
via under “Via Definition”, make a left mouse click to place the via.
13. For the example used here, “VDD” is at the top and “VSS” is at the bottom. Source & Bulk of
PMOS/NMOS can be routed to VDD/VSS respectively as earlier between other pins and terminals
(or) the entire top layer can be used for VDD and bottom layer for VSS using “Pin Placement”
option.
14. Select “Place -> Pin Placement” a window pops up Under “Pin Planner” tab, “Pin Name,
Attributes & Create” options can be seen.
15. Select “VDD” under “Pin Name”, select “Top” under “Attributes -> Edge”, select “HRail”
under “Create” and select “Apply” under “Attributes” to place VDD at the top layer.
16. Similarly, select “VSS” under “Pin Name”, select “Bottom” under “Attributes -> Edge”, select
“HRail” under “Create” and select “Apply” under “Attributes” to place VSS at the bottom layer.
17. After routing the terminals of PMOS/NMOS terminals with VDD/VSS respectively, save the
layout.
PHYSICAL VERIFICATION:
1.The tool used for Physical Verification is Assura where DRC, LVS of a design are verified and
Parasitics of the design are extracted using QRC for technology nodes like gpdk180, gpdk090 and
gpdk045.
2. PVS is another tool for Physical Verification on designs made using technology nodes like
gpdk045 and below.
PHYSICAL VERIFICATION WITH ASSURA:
3.The first step in Physical Verification is the Technology Library Mapping. Technology Library
Mapping: Select “Assura -> Technology”, an “Assura Technology Lib Select” window can be
seen.

QISCET VLSI DESIGN LABORATORY DEPT OF ECE 19

 4. Select “Browse” so that the “File Selector” can be seen.
5. Two columns, “Directories” and “Files” can be seen. The “Single Dot” under “Directories”
indicates the present working directory, “Double Dot” just below the “Single Dot” is used to go
back to the previous/next directories and “1_inv” indicates the library under which the layout is
saved. Use the “Double Dot” option to browse the library file “assura_tech.lib” based on the
technology node of interest and select OK.
DRC:
1.To perform the DRC check, select “Assura -> Run DRC”.
2.A “Run Assura DRC” window can be seen. Verify the Library, Cell and View in the second row.
Give any name under the “Run Name” option, click on the drop down next to “Technology” and
select the “Technology Node” of interest.
3. The “Run Assura DRC” window after mentioning the options as given.
4. Select OK to run the DRC. A “Progress” tab can be seen at the right-side bottom corner of the
screen.
5. To check the background process or log file, select “Watch Log File” option under the
“Progress” tab.
6. A run completion tab pops-up as in Figure-81(a). Select “Yes” and the DRC run result can be seen.
LVS:
1.To perform the LVS check, select “Assura -> Run LVS”
2. A “Run Assura LVS” window can be seen. Verify the Library, Cell and View for the Schematic
Design Source and Layout Design Source.
3. Give any name under the “Run Name” option, click on the drop down next to “Technology” and
select the “Technology Node” of interest and the “Run Assura LVS” window after mentioning the
options as given.
4. Select OK to run the LVS. A “Progress” tab can be seen at the right-side bottom corner of the
screen similar to Figure-80. To check the background process or log file, select “Watch Log File”
option under the “Progress” tab.
5. A run completion tab pops-up Select “Yes” and the DRC run result can be seen.
QRC:
1. To extract the Parasitics, select “Assura -> Run Quantus QRC” and A “Quantus QRC (Assura)
Parasitic Extraction Run Form” window can be seen.

QISCET VLSI DESIGN LABORATORY DEPT OF ECE 20

 2. Under the “Setup” tab, verify the “Technology”, “Output -> Extracted View” and under
“Extraction” tab, verify “Extraction Type -> RC”, “Ref Node -> vdd! (or) gnd!” Select OK to
extract the Parasitics.
3. A “Progress” tab can be seen at the right-side bottom corner of the screen To check the
background process or log file,select “Watch Log File” option under the “Progress” tab.
4. A run completion tab pops-up Select “Close” and the “av_extracted” view can be seen in the
Library Manager.
5. Make a double click on the “av_extracted” view, a design can be seen Select “Shift+F” on the
keyboard and if zoomed into the design with the help of mouse scroller, the parasitic resistor, its
value and parasitic capacitor, its value can be seen.
PHYSICAL VERIFICATION WITH PVS:
PVS tool is for Physical Verification of circuits designed with Technology nodes of 45nm and below.
The steps to perform DRC, LVS and QRC are as follows.
1. DRC: To perform the DRC check, select “PVS -> Run DRC”.
2. A “PVS DRC Run Submission Form” window can be seen Select “Run Data” tab, browse a
“Run Directory” and Select “Rules” tab, browse the “Technology Mapping File”.
3. select the “Technology” after which the “DRC.rul” can be seen under “Rules” and select
“Submit” and a run completion tab pops-up and the run results can be seen.
4.LVS: To perform the LVS check, select “PVS -> Run LVS” and A “PVS LVS Run Submission
Form” window can be seen.
5. Select “Run Data” tab, browse a “Run Directory” similar to that.Select “Rules” tab, browse the
“Technology Mapping File”, “my.rul” file.
6. select the “Technology” after which the “LVS.rul” and “my.rul” can be seen under “Rules”. The
“my.rul” file should be created manually and saved in the work directory.
7. Select “Input” tab and select “Convert Pin to -> Geometry + Text” Select “Output” tab.
8.enable “Create Quantus QRC Input Data” under “Additional Output” to create the input for
QRC run and select “Submit”.A run completion tab pops-up and the run results can be seen.
9. QRC: To extract the Parasitics, select “QRC -> Run PVS - Quantus QRC”. A “Quantus QRC
(PVS) Parasitic Extraction Run Form” window can be seen.
10. Under the “Setup” tab, verify the “Technology”, “RuleSet”, “Output -> Extracted View”,
“Enable CellView Check” option should be disabled and under “Extraction” tab, verify
“Extraction Type -> RC”, “Ref Node -> vdd! (or) gnd!” .Select OK to extract the Parasitics.

QISCET VLSI DESIGN LABORATORY DEPT OF ECE 21

 11. A “Progress” tab can be seen at the right-side bottom corner of the screen and to check the
background process or log file,select “Watch Log File” option under the “Progress” tab.
12.A run completion tab pops-up and Select “Close” and the “av_extracted” view can be seen in the
Library Manager.
13. Make a double click on the “av_extracted” view, a design can be seen Select “Shift+F” on the
keyboard and if zoomed into the design with the help of mouse scroller, the parasitic resistor, its
value and parasitic capacitor, its value can be seen.
BACKANNOTATION (or) POST LAYOUT SIMULATION: To perform Backannotation, select
the library that was created earlier, select the cell that has the testbench circuit and select schematic as
view.
1.Select “File -> New -> Cell View”, select “Type -> Config” and select OK.
2. A “New Configuration” window pops-up and select “Use Template” option, a “Use Template”
tab pops-up,select “Name -> spectre” under “Template” and select OK.
3. This brings back the “New Configuration” window under “Top Cell”, select “View ->
Schematic” and select OK.
4. A “Virtuoso Hierarchy Editor: New Configuration” window pops-up and select “Tree View”,
now select “I0” folder, make a right click on mouse, select “Set Instance View” and select
“av_extracted”.
5. When we select the “+” sign just before the “I0” folder, we can see the parasitic resistors and
capacitors getting imported to the circuit.
6. Save the configuration and select “Open”, this should bring back the testbench circuit and Open
ADE L by selecting “Launch -> ADE L”, select “Session -> Load State”, load the simulation state
with which we simulated the circuit earlier by selecting “Load State Option -> Cellview” and select
OK. This brings back the “Analyses” and “Input & Output Nets”.
7. Select “Simulation -> Netlist & Run” and re-run the simulation. Compare the results of
PreLayout & Post-Layout Simulation to analyze the impact of parasitic resistors and capacitors.
GDSII:
1.The final step of the Full Custom IC Design flow is the generation of GDS file. To generate GDS
file, open Virtuoso tab, select “File -> Export -> Stream”, this pops-up the “Virtuoso XStream
Out” tab with “View(s) -> layout”.

QISCET VLSI DESIGN LABORATORY DEPT OF ECE 22

 2. This means that the particulars related to layout of the design has to be browsed. In “Virtuoso
XStream Out” tab, select “Library” that was created earlier, select “TopCell(s)” which has the
layout and the “Technology Library” with which the design was created.
3. Now select OK. The “Virtuoso XStream Out” tab can be seen.
4. Select “Translate” and the .gds file will be created and saved in the work directory. The log file
can be seen.

Part –B: XILINX PROCEDURE:

1. Double click on Xilinx Design Suite 14.7 Icon.
2. Select new project in file menu.
3. Enter the project name and location as shown below and press Next.
4. Select the Family, Device, Package and speed as per the requirements and press Next.
5. Create a new source by using new source icon or right click on the device/project folder to
create new source.
6. Select the appropriate source type and enter the file name in New Source Wizard window and
press Next.
7. Enter the architecture name – dataflow/behavioral/structural, port name and select the direction.
This will create .v source file. Press Next and finish the initial project creation.
8. Write complete VHDL/Verilog code implementation and save.
9. Click on implementation and check for syntax using “Check syntax” option under synthesize tab.
If any error, edit and correct VHDL/Verilog code and repeat check syntax until zero errors.
10. Double click on ISIM simulator by selecting simulation mode to complete the functional
simulation of your design.

Part –C: FPGA Hardware Interfacing Procedure:

1. Repeat the steps 1 to 10 from the procedure for software experiments.
2. Make the connection between appropriate FRC’s of the FPGA board and the DIP switch
connector of the GPIOcard-2/
3. Make the connection between appropriate FRC’s of the FPGA board and the LED connector of
the GPIOcard-2.
4. Right click on the device and select “New Source”, Select the option “Implementation constraint

QISCET VLSI DESIGN LABORATORY DEPT OF ECE 23

 File” and provide the file name and click on next and then hit Finish. This creates an .ucf file.
6. Double click on the added .ucf file and assign the pin numbers to inputs and outputs referring to
FRC sheet using the syntax as shown.Save the constraint file.
7. Connect USB programmer for FPGA between FPGA kit and USB port of your computer.
8. Go to process window, select the VHDL or Verilog file and click on “configure target device”.
9. Click OK for the warning below.
10. Select boundary scan to impact the target device.
11. Right click on the impact window to establish a connection between system and FPGA by
selecting “INTIALIZE CHAIN” option.
12. Both prom device and FPGA device gets identified after step 10 and bypass the procedure to
select only FPGA which of main interest.
13. Now choose device 2(FPGA XC3S400) and hit ok to complete the impact.
14. Now right click on the device to assign a new .bit file by selecting an option “ASSIGN NEW
CONFIGURATION FILE”.
15. Select the corresponding .bit file from the project folder and hit Open
16. Press ‘No’ on the following dialog box.
17. Finally right click on the device(XC3S400) and implement the program by choosing an option
“PROGRAM”
18. Once again select the FPGA device (XC3S400) by clicking ok and now the program will be
identified and succeeded.

DESIGN PROCEDURE OF XILINX ISE 14.7

Starting the ISE Software To start the ISE software, double-click the ISE Project Navigator icon on
your desktop, or select Start > All Programs > Xilinx ISE Design Suite 14.7 > ISE Design Tools >
Project Navigator

Creating a New Project

To create a new project using the New Project Wizard, do the following:
From Project Navigator, select File > New Project. The New Project Wizard appears.

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 In the Location field, browse to c:\xilinx\14.7\ISE\ISEexamplesor to the directory in which you
installed the project.
In the Name field, enter name of the project.
Verify that HDL is selected as the Top-Level Source Type, and click Next.

The New Project Wizard—Device Properties page appears

1. Select the following values in the New Project Wizard—Device Properties page:
♦ Product Category: All
♦ Family: Spartan3
♦ Device: XC3S400

♦ Package: FT208
♦ Speed: -5
♦ Synthesis Tool: XST (VHDL/Verilog)
♦ Simulator: ISim (VHDL/Verilog)
♦ Preferred Language: VHDL or Verilog depending on preference. This will determine
the default language for all processes that generate HDL files.

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 Other properties can be left at their default values.
2. Click next, and then finish completing the project creation.
To create the source file, do the following:
1. Select Project > New Source.
The New Source Wizard opens in which you specify the type of source you want to create.
2.In the Select Source Type page, select VHDL Module or Verilog Module.
3.In the File Name field, enter ex.ALU design.

4.Click Next.
5.In the Define Module page, enter two input ports named sig_in and clk and an output port named
sig_out for the ALU design component as follows:
 In the first three Port Name fields, enter sig_in, clk and sig_out.
 Set the Direction field to input for sig_in and clk and to output for sig_out.
 Leave the Bus designation boxes unchecked.

5. Click Next to view a description of the module.

6. Click Finish to open the empty HDL file in the ISE Text Editor. Following is an example
VHDL file.

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 SIMULATION
The simulation processes in the ISE software enable you to run simulation on the design using
ISim.
To locate the ISim processes, do the following:
1. In the View pane of the Project Navigator Design panel, select Simulation, and select Behavioral
from the drop-down list.
2. In the Hierarchy pane, select the test bench file (stopwatch_tb).
3. In the Processes pane, expand ISim Simulator to view the process hierarchy
The following simulation processes are available:
♦ Check Syntax: This process checks for syntax errors in the test bench.
♦ Simulate Behavioral Model: This process starts the design simulation.

Force different values to signals by clicking on force option and run.

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 Design Implementation
Create user constraint file one as follows:
1. In the Hierarchy pane of the Project Navigator Design panel, select the top-level source file
stopwatch.
2. Select Project > New Source.
3. Select Implementation Constraints File.
4. Enter stopwatch.ucf as the file name.
5. Click Next.
6. Click Finish.
To set the implementation properties, do the following:
1. In the View pane of the Project Navigator Design panel, select Implementation.
2. In the Hierarchy pane, select the stopwatch top-level file.
3. In the Processes pane, right-click the Implement Design process, and select Process Properties.
4. Ensure that you have set the Property display level to Advanced. This global setting enables
you to see all available properties.
5. Click the Place & Route Properties category.
6. Change the Place & Route Effort Level (Overall) to High.
Creating Timing Constraints
The User Constraints File (UCF) is a text file and can be edited directly with a text editor. To
facilitate editing of this file, graphical tools are provided to create and edit constraints. The
Constraints Editor and Plan Ahead software are graphical tools that enable you to enter timing and
I/O and placement constraints.
To launch the Constraints Editor, do the following:
1. In the Hierarchy pane of the Project Navigator Design panel, select the stopwatch module.
2. In the Processes pane, expand User Constraints, and double-click Create Timing Constraints.

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 Opening iMPACT from Project Navigator

To start iMPACT from Project Navigator, double-click Manage Configuration Project

(iMPACT)in the Processes pane in the Design panel, as shown in the following figure.

Opening iMPACT Standalone

To open iMPACT without going through an ISE project, use one of the following methods:
• PC only: Click Start> All Programs> Xilinx ISE Design Suite 14.7 > ISE Design Tools >
Tools> iMPACT.

• PC or Linux: Type impactat a command prompt.

Creating an iMPACT New Project File
When iMPACT is initially opened, the iMPACT Project dialog box opens. This dialog box enables
you to load a recent project or to create a new project

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 To create a new project, do the following:
1. In the iMPACT Project dialog box, select create a new project (.ipf).
2. Click the Browse button.
3. Browse to the project directory, and then enter stopwatch in the File Name field.
4. Click Save.
5. Click OK
Using Boundary-Scan Configuration Mode
For this tutorial, you will be using the Boundary-Scan configuration mode. Boundary-Scan
configuration mode enables you to perform Boundary-Scan operations on any chain comprising
JTAG compliant devices. The chain can consist of both Xilinx and non-Xilinx devices; however,
limited operations will be available for non-Xilinx devices. To perform operations, the cable must
be connected and the JTAG pins, TDI, TCK, TMS, and TDO, must be connected from the cable to
the board.
Specifying Boundary-Scan Configuration Mode
After opening iMPACT, you are prompted to specify the configuration mode and the device to
program. To select Boundary-Scan Mode, do the following:
1. Select Configure Devices using Boundary-Scan (JTAG).
2. Ensure that Automatically connect to a cable and identify Boundary-Scan chain is selected.
3. Click Finish.

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 Assigning Configuration Files
After initializing a chain, the software prompts you for a configuration file
The configuration file is used to program the device. There are several types of configuration files:
• Bitstream file (*.bit, *.rbt, *.isc) is used to configure an FPGA.
• JEDEC file (*.jed,*.isc) is used to configure a CPLD.
• PROM file (*.mcs, *.hex) is used to configure a PROM.

When the software prompts you to select a configuration file for the first device (XC3S700A), do the
following:
1. Select the BIT file from your project working directory.
2. Click Open.
You should receive a warning stating that the startup clock has been changed to JtagClk.
Click OK.

When the software prompts you to select a configuration file for the second device
(XCF02S), select the MCS file from your project working directory.
Click Open.
Performing Boundary-Scan Operations
You can perform Boundary-Scan operations on one device at a time. The available Boundary- Scan
operations vary based on the device and the configuration file that was applied to the device. To
see a list of the available options, right-click on any device in the chain. This brings up a window
with all of the available options. When you select a device and perform an operation on that device,
all other devices in the chain are automatically placed in BYPASS or HIGHZ, depending on your
iMPACT Preferences setting. For more information about Preferences, see “Editing Preferences.”
To perform an operation, right-click on a device and select one of the options. In this section, you

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 will retrieve the device ID and run the programming option to verify the first device as follows:

1. Right-click on the XC3S700A device, and select Get Device ID.

2. Right-click on the XC3S700A device, and select Set Programming Properties. The Device
Programming Properties dialog box opens.
3. Select the Verify option.
The Verify option enables the device to beread back and compared to the BIT file using the MSK
file that was created earlier.
4. Click OK to begin programming

5. Right-click on the XC3S700Adevice again, and select Program.

The Programming operation begins and an operation status window appears. At the same time, the
log window reports all of the operations being performed.
When the Program operation completes, a large blue message appears showing that programming
was successful, as shown in the following figure. This message disappears after a few seconds.

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QISCET VLSI DESIGN LABORATORY DEPT OF ECE 33
 EXPERIMENTS

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 EXPT No: 01
Design and Implementation of an Inverter DATE:

Aim: To implement an inverter using 90nm Technology and to verify the functionality of the circuit
by performing Pre-Layout simulation using Cadence Tools and Observe the transient and DC
analysis.
Tool Required:
1. Cadence Virtuoso schematic editor for Schematic design
2. Spectra for Simulation.
Circuit Diagram: Truth table

Vin Vout
0 1
1 0

Vin Vout

Symbol

Procedure:

1. Create Folder & Name the folder.

2. Open the terminal & Invoke virtuoso
3. Create a Library
4. Create a cell and draw the schematic diagram using Cadence Virtuoso schematic editor
5. Create a Symbol for the drawn schematic
6. Call the created symbol and do the simulation setup for performing pre-layout simulation.
7. Perform the pre-layout simulation of the circuit and verify the functionality of the circuit
using Spectra.
8. Observe the transient and DC analysis.

QISCET VLSI DESIGN LABORATORY DEPT OF ECE 35

 Model graph:

Results:
Specifications:
Nmos:
Pmos:
Input Pins:
Output pins:
Simulation Settings:
Vpulse V1 = 1V V2 = 0V Vdd = 1V
td = 20n tr = tf= 50p pulse width=10ns

Setup for transient analysis:

1. Stop time = 100n
Setup for D.C analysis
1. Component to be selected in schematic is_______for d.c analysis
2. Start = 0 Stop = 1

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 Schematic Diagram:

Inverter Schematic Design Inverter Symbol with Test Bench Design

Output waveform:

Conclusion:
Hence an Inverter is implemented using CMOS 90nm technology and the functionality of the circuit is
verified by performing pre-layout simulation using Cadence Tools.

QISCET VLSI DESIGN LABORATORY DEPT OF ECE 37

 EXPT No: 02
Design and Implementation of Universal gates DATE:

Aim: To implement Universal Gates using 90nm Technology and to verify the functionality of the
circuit by performing Pre - Layout simulation using Cadence Tools and Observe the transient and DC
analysis.
Tool Required:
1. Cadence Virtuoso schematic editor for Schematic design
2. Spectra for Simulation.
Circuit Diagram:

Truth table Truth table

NAND Gate Schematic Symbol NOR Gate Schematic Symbol

Procedure:

1. Create Folder & Name the folder.

2. Open the terminal & Invoke virtuoso
3. Create a Library
4. Create a cell and draw the schematic diagram using Cadence Virtuoso schematic editor
5. Create a Symbol for the drawn schematic
6. Call the created symbol and do the simulation setup for performing pre-layout simulation.
7. Perform the pre-layout simulation of the circuit and verify the functionality of the circuit using
Spectra.
8. Observe the transient and DC analysis.

QISCET VLSI DESIGN LABORATORY DEPT OF ECE 38

 Model graph:

NAND Gate waveform

NOR Gate wave form

Results:
Specifications:
nmos
pmos
Input Pins
Output pin
Simulation Settings
Vpulse Va: V1 = V2 = Vdd =
td = tr = tf= ton = T=
Vb: V1 = V2 = Vdd =
td = tr = tf= ton = T=
Setup for transient analysis:
1. Stop time =
Setup for D.C analysis
1. Component to be selected in schematic is_______for d.c analysis
2. Start = Stop =

QISCET VLSI DESIGN LABORATORY DEPT OF ECE 39

 Schematic Diagram:

NAND Gate Schematic Design NAND Gate Symbol with Test Bench Design

Output waveform:

Conclusion:
Hence an Universal Gates (NAND and NOR Gates) are implemented using CMOS 90nm technology
and the functionality of the circuits are verified by performing pre-layout simulation using Cadence
Tools.

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 EXPT No: 03
Design and Implementation of Full adder using NAND Gates DATE:

Aim: To implement a Full-Adder design using 90nm Technology and to verify the functionality of
the circuit by performing Pre - Layout simulation using Cadence Tools and Observe the transient and
DC analysis.
Tool Required:
1. Cadence Virtuoso schematic editor for Schematic design
2. Spectra for Simulation.

Circuit Diagram:

Truth Table:

Truth table of 1bit-Full adder

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 Procedure:

1. Create Folder & Name the folder.

2. Open the terminal & Invoke virtuoso
3. Create a Library
4. Create a cell and draw the schematic diagram using Cadence Virtuoso schematic editor
5. Create a Symbol for the drawn schematic
6. Call the created symbol and do the simulation setup for performing pre-layout simulation.
7. Perform the pre-layout simulation of the circuit and verify the functionality of the circuit using
Spectra.
8. Observe the transient and DC analysis.

Model graph

Results:
Specifications:
nmos
pmos
Input Pins
Output pin
Simulation Settings
Vpulse Va: V1 = V2 = Vdd =
td = tr = tf= ton = T=

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 Vb: V1 = V2 = Vdd =
td = tr = tf= ton = T=
Vc: V1 = V2 = Vdd =
td = tr = tf= ton = T=
Setup for transient analysis:
1. Stop time =
Setup for D.C analysis
1. Component to be selected in schematic is_______for d.c analysis
2. Start = Stop =

Schematic Diagram:

Symbol:

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 Output waveform:

Conclusion:
Hence an Full Adder circuit is implemented using NAND Gates in CMOS 90nm technology and the
functionality of the circuit is verified by performing pre-layout simulation using Cadence Tools.

QISCET VLSI DESIGN LABORATORY DEPT OF ECE 44

 EXPT No: 04
Design and Implementation of Full-Subtractor using NAND Gates DATE:

Aim: To implement a Full - Subtractor design using NAND Gates in 90nm Technology and to verify
the functionality of the circuit by performing Pre - Layout simulation using Cadence Tools and
Observe the transient and DC analysis.
Tool Required:
1. Cadence Virtuoso schematic editor for Schematic design
2. Spectra for Simulation.
Circuit Diagram:

Truth table of Full Subtractor

QISCET VLSI DESIGN LABORATORY DEPT OF ECE 45

 Procedure:

1. Create Folder & Name the folder.

2. Open the terminal & Invoke virtuoso
3. Create a Library
4. Create a cell and draw the schematic diagram using Cadence Virtuoso schematic editor
5. Create a Symbol for the drawn schematic
6. Call the created symbol and do the simulation setup for performing pre-layout simulation.
7. Perform the pre-layout simulation of the circuit and verify the functionality of the circuit using
Spectra.
8. Observe the transient and DC analysis.

Results:
Specifications:
nmos
pmos
Input Pins
Output pin
Simulation Settings
Vpulse Va: V1 = V2 = Vdd =
td = tr = tf= ton = T=
Vb: V1 = V2 = Vdd =
td = tr = tf= ton = T=
Vc: V1 = V2 = Vdd =
td = tr = tf= ton = T=
Setup for transient analysis:
1. Stop time =
Setup for D.C analysis
1. Component to be selected in schematic is_______for d.c analysis
2. Start = Stop =

QISCET VLSI DESIGN LABORATORY DEPT OF ECE 46

 Schematic Diagram:

Symbol:

QISCET VLSI DESIGN LABORATORY DEPT OF ECE 47

 Output waveform:

Conclusion:
Hence a Full Subtractor circuit is implemented using NAND Gates in CMOS 90nm technology and
the functionality of the circuit is verified by performing pre-layout simulation using Cadence Tools.

QISCET VLSI DESIGN LABORATORY DEPT OF ECE 48

 EXPT No: 05
Design and Implementation of SR-Latch DATE:

Aim: To implement a RS-Latch using 90nm Technology and to verify the functionality of the circuit
by performing Pre - Layout simulation using Cadence Tools and Observe the transient and DC
analysis.
Tool Required:
1. Cadence Virtuoso schematic editor for Schematic design
2. Spectra for Simulation.
Circuit diagram:
Logic Diagram and Symbol of SR-Latch
PR
PR

CLR CLR
Truth table of SR-Latch
EN PR CLR S R Q Qb

1 0 1 X X 1 0

1 1 0 X X 0 1

0 1 1 X X NC

1 1 1 0 0 NC

1 1 1 0 1 0 1

1 1 1 1 0 1 0

1 1 1 1 1 *

QISCET VLSI DESIGN LABORATORY DEPT OF ECE 49

 Procedure:

1. Create Folder & Name the folder.

2. Open the terminal & Invoke virtuoso
3. Create a Library
4. Create a cell and draw the schematic diagram using Cadence Virtuoso schematic editor
5. Create a Symbol for the drawn schematic.
6. Call the created symbol and do the simulation setup for performing pre-layout simulation.
7. Perform the pre-layout simulation of the circuit and verify the functionality of the circuit using
Spectra.
8. Observe the transient and DC analysis.

Model graph:

EN

Results:
Specifications:
nmos
pmos
Input Pins
Output pin
Simulation Settings
Vpulse V1 = V2 = Vdd =
td = tr = tf= ton = T=

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 Setup for transient analysis:
1. Stop time =
Setup for D.C analysis
1. Component to be selected in schematic is_______for d.c analysis
2. Start = Stop =
Schematic Diagram:

Conclusion:
Hence an RS Latch is implemented using CMOS 90nm technology and the functionality of the circuit
is verified by performing pre-layout simulation using Cadence Tools.

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 EXPT No: 06
Design and Implementation of D-Latch DATE:

Aim: To implement a D - Latch using 90nm Technology and to verify the functionality of the circuit
by performing Pre - Layout simulation using Cadence Tools and Observe the transient and DC
analysis.
Tool Required:
1. Cadence Virtuoso schematic editor for Schematic design
2. Spectra for Simulation.
Circuit Diagram:

Truth table of D-Latch Block diagram of D-Latch

QISCET VLSI DESIGN LABORATORY DEPT OF ECE 52

 Procedure:

1. Create Folder & Name the folder.

2. Open the terminal & Invoke virtuoso.
3. Create a Library.
4. Create a cell and draw the schematic diagram using Cadence Virtuoso schematic editor.
5. Create a Symbol for the drawn schematic.
6. Call the created symbol and do the simulation setup for performing pre-layout simulation.
7. Perform the pre-layout simulation of the circuit and verify the functionality of the circuit using
Spectra.
8. Observe the transient and DC analysis.
Model graph:

Results:
Specifications:
nmos
pmos
Input Pins
Output pin
Simulation Settings
Vpulse V1 = V2 = Vdd =
td = tr = tf= ton = T=

QISCET VLSI DESIGN LABORATORY DEPT OF ECE 53

 Setup for transient analysis:
1. Stop time =
Setup for D.C analysis
1. Component to be selected in schematic is_______for d.c analysis
2. Start = Stop =

Schematic Diagram:

Conclusion:
Hence a D-Latch is implemented using CMOS 90nm technology and the functionality of the circuit is
verified by performing pre-layout simulation using Cadence Tools.

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 EXPT No: 07
Design and Implementation of Asynchronous counter DATE:

Aim: To implement an Asynchronous Counter using 90nm Technology and to verify the
functionality of the circuit by performing Pre - Layout simulation using Cadence Tools and Observe
the transient and DC analysis.
Tool Required:
1. Cadence Virtuoso schematic editor for Schematic design
2. Spectra for Simulation.
Circuit Diagram:

Block diagram of Asynchronous counter State table of Asynchronous counter

Procedure:

1. Create Folder & Name the folder.

2. Open the terminal & Invoke virtuoso
3. Create a Library
4. Create a cell and draw the schematic diagram using Cadence Virtuoso schematic editor
5. Create a Symbol for the drawn schematic
6. Call the created symbol and do the simulation setup for performing pre-layout simulation.
7. Perform the pre-layout simulation of the circuit and verify the functionality of the circuit using
Spectra.
8. Observe the transient and DC analysis.

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 Model graph:

Results:
Specifications:
nmos
pmos
Input Pins
Output pin
Simulation Settings
Vpulse V1 = V2 = Vdd =
td = tr = tf= ton = T=
Setup for transient analysis:
1. Stop time =
Setup for D.C analysis
1. Component to be selected in schematic is_______for d.c analysis
2. Start = Stop =

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 Schematic Diagram:

NAND Gate Schematic Diagram D-Flip Flop Schematic Diagram

Asynchronous Counter

Output waveform

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 Conclusion:
Hence an Asynchronous counter is implemented using CMOS 90nm technology and the functionality
of the circuit is verified by performing pre-layout simulation using Cadence Tools.

QISCET VLSI DESIGN LABORATORY DEPT OF ECE 58

 EXPT No: 08
Design and Implementation of SRAM cell Using Inverters DATE:

Aim: To implement a Static RAM Cell using 90nm Technology and to verify the functionality of the
circuit by performing Pre - Layout simulation using Cadence Tools and Observe the transient and DC
analysis.
Tool Required:
1. Cadence Virtuoso schematic editor for Schematic design
2. Spectra for Simulation.
Circuit Diagram:

Schematic of SRAM cell

Procedure:

1. Create Folder & Name the folder.

2. Open the terminal & Invoke virtuoso
3. Create a Library
4. Create a cell and draw the schematic diagram using Cadence Virtuoso schematic editor
5. Create a Symbol for the drawn schematic
6. Call the created symbol and do the simulation setup for performing pre-layout simulation.
7. Perform the pre-layout simulation of the circuit and verify the functionality of the circuit using
Spectra.
8. Observe the transient and DC analysis.

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 Results:
Specifications:
nmos
pmos
Input Pins
Output pin
Simulation Settings
Vpulse: WL V1 = V2 = Vdd =
td = tr = tf= ton = T=
BL V1 = V2 = Vdd =
td = tr = tf= ton = T=
BLbar V1 = V2 = Vdd =
td = tr = tf= ton = T=
Setup for transient analysis:
1. Stop time =
Setup for D.C analysis
1. Component to be selected in schematic is_______for d.c analysis
2. Start = Stop =
Schematic Diagram:

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 Output waveform

Conclusion:
Hence a Static RAM Cell is implemented using CMOS 90nm technology and the functionality of the
circuit is verified by performing pre-layout simulation using Cadence Tools.

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 EXPT No: 09
Design and Implementation of differential amplifier DATE:

Aim: To implement a Differential Amplifier circuit using 90nm Technology and to verify the
functionality of the circuit by performing Pre - Layout simulation using Cadence Tools and Observe
the transient and DC analysis.
Tool Required:
1. Cadence Virtuoso schematic editor for Schematic design
2. Spectra for Simulation.
THEORY : The differential amplifier is probably the most widely used circuit building block in
analog integrated circuits, principally op amps. We had a brief glimpse at one back in Chapter 3
section 3.4.3 when we were discussing input bias current. The differential amplifier can be
implemented with BJTs or MOSFETs. A differential amplifier multiplies the voltage difference
between two inputs (Vin+ - Vin- ) by some constant factor Ad, the differential gain. It may have either
one output or a pair of outputs where the signal of interest is the voltage difference between the two
outputs. A differential amplifier also tends to reject the part of the input signals that are common to
both inputs (Vin+ + Vin-)/2 . This is referred to as the common mode signal.

Circuit Diagram:

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 Procedure:

1. Create Folder & Name the folder.

2. Open the terminal & Invoke virtuoso
3. Create a Library
4. Create a cell and draw the schematic diagram using Cadence Virtuoso schematic editor
5. Create a Symbol for the drawn schematic
6. Call the created symbol and do the simulation setup for performing pre-layout simulation.
7. Perform the pre-layout simulation of the circuit and verify the functionality of the circuit using
Spectra.
8. Observe the transient and DC analysis.

Results:
Specifications:
nmos
pmos
Input Pins
Output pin
Simulation Settings
Vpulse V1 = V2 = Vdd =
td = tr = tf= ton = T=
Setup for transient analysis:
1. Stop time =
Setup for D.C analysis
1. Component to be selected in schematic is_______for d.c analysis
2. Start = Stop =

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 Schematic Diagram:

Conclusion:
Hence an Differential Amplifier circuit is implemented using CMOS 90nm technology and the
functionality of the circuit is verified by performing pre-layout simulation using Cadence Tools.

QISCET VLSI DESIGN LABORATORY DEPT OF ECE 64

 EXPT No: 10
Design and Implementation of Ring Oscillator DATE:

Aim: To implement a Ring Oscillator Circuit using 90nm Technology and to verify the functionality
of the circuit by performing Pre - Layout simulation using Cadence Tools and Observe the transient
and DC analysis.
Tool Required:
1. Cadence Virtuoso schematic editor for Schematic design
2. Spectra for Simulation.
Theory:
A ring oscillator is a device composed of an odd number of NOT gates in a ring, whose
output oscillates between two voltage levels, representing true and false. The NOT gates, or inverters,
are attached in a chain and the output of the last inverter is fed back into the first.
The ring oscillator is a combination of inverters connected in a series form with a feedback connection.
And the output of the final stage is again connected to the initial stage of the oscillator. This can be
done through the transistor implementation also. The below figure shows the ring oscillator
implantation with a CMOS transistor.
The s frequency of oscillation formula for this oscillator is

Here T = time delay for single inverter

n = number of inverters in the oscillator

Circuit Diagram:

Ring-Oscillator-diagram

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 Procedure:

1. Create Folder & Name the folder.

2. Open the terminal & Invoke virtuoso
3. Create a Library
4. Create a cell and draw the schematic diagram using Cadence Virtuoso schematic editor
5. Create a Symbol for the drawn schematic
6. Call the created symbol and do the simulation setup for performing pre-layout simulation.
7. Perform the pre-layout simulation of the circuit and verify the functionality of the circuit using
Spectra.
8. Observe the transient and DC analysis.

Results:
Specifications:
nmos
pmos
Input Pins
Output pin
Simulation Settings
Vdc = 1V Cap = 1pf
Setup for transient analysis:
Stop time = 3us
Set initial value = 0
[How to set Initial Value]
Goto Simulation Tab

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 Schematic Diagram:

Output waveform:

Conclusion:
Hence a Ring Oscillator is implemented using CMOS 90nm technology and the functionality of the
circuit is verified by performing pre-layout simulation using Cadence Tools.

QISCET VLSI DESIGN LABORATORY DEPT OF ECE 67

 EXPT No: 11
Design and Implementation of Universal Shift Register on Spartan-6 FPGA DATE:

Aim: Verify the Hardware Implementation of Universal Shift Register on Spartan-6 FPGA and
also verify the functionality of the circuit by performing Pre - Layout simulation using Xilinx Tools.
Tool Required:
1. Xilinx Tool 14.7v
2. Spatan-6 FPGA Board
Procedure:
Simulation:
1. Double click on Xilinx Design Suite 14.7 Icon.
2. Select new project in file menu.
3. Enter the project name and give location and press Next.
4. Select the Family, Device, Package and speed as per the requirements and press Next.
5. Create a new source by using new source icon or right click on the device/project folder to
create new source.
6. Select the appropriate source type and enter the file name in New Source Wizard window
and press Next.
7. Enter the architecture name – dataflow/behavioral/structural, port name and select the
direction. This will create “.v” source file. Press Next and finish the initial project creation.
8. Write complete VHDL/Verilog code implementation and save.
9. Click on implementation and check for syntax using “Check syntax” option under
synthesize tab. If any error, edit and correct VHDL/Verilog code and repeat check syntax until
zero errors.
10. Double click on ISIM simulator by selecting simulation mode to complete the functional
simulation of your design.
FPGA Hardware Interfacing Procedure:
1. Repeat the steps 1 to 10 from the procedure for software experiments.
2. Make the connection between appropriate FRC’s of the FPGA board and the DIP switch
connector of the GPIOcard-2

Design Implementation
a. Create user constraint file one as follows:

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 b. In the Hierarchy pane of the Project Navigator Design panel, select the top-level
source file usr.
c. Select Project > New Source.
d. Select Implementation Constraints File.
e. Enter usr.ucf as the file name.
f. Click Next.
g. Click Finish.
3. Click on Generate Programming file.
4. Configure Target Device.
5. Select boundary scan to impact the target device.
6. Right click on the impact window to establish a connection between system and FPGA by
selecting “INTIALIZE CHAIN” option.
7. Both prom device and FPGA device gets identified.
8. Now choose device 2(FPGA XC3S400) and hit ok to complete the impact.
9. Now right click on the device to assign a new .bit file by selecting an option “ASSIGN
NEW CONFIGURATION FILE”.
10. Select the corresponding .bit file from the project folder and hit Open
11. Press ‘No’ on the following dialog box.
12. Finally right click on the device(XC3S400) and implement the program by choosing an
option “PROGRAM”
13. Once again select the FPGA device (XC3S400) by clicking ok and now the program will
be identified and succeeded.

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 Logic Diagram

Functional Table

Mode Control Register Operation

S1 S0
0 0 No Change
0 1 Shift Right
1 0 Shift Left
1 1 Parallel Load

Verilog Code

module USR(clr, clk, left_in, right_in, sel, par_in, out);

input rst, clk, left_in, right_in;

input [1:0]sel;
input [3:0]par_in;

output reg [3:0]out;

always@(posedge clk)
begin
if(rst)
out = 4`b 0000;
else
begin
case(sel)
2’b00: out = out; //No change
2’b01: out = out = (right_in, out[3:1]); //right shift

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 2’b10: out = out = (left_in, out[2:0]); //left shift
2’b11: out = par_in; //parallel load
endcase
end
end
endmodule

Test Bench
module USR_TB;
reg rst, clk, left_in, right_in;
reg [3:0] par_in;
reg [1:0] sel;

wire [3:0] out;

USR uut(.rst(rst), .clk(clk), .left_in(left_in), .rigjt_in(right_in), .par_in(par_in), .sel(sel), .out(out));

Initial begin
rst = 0;
clk = 0;
left_in = 0;
right_in = 0;
par_in = 0;
sel = 0;
#10;

rst = 1`b1;
#10;

rst = 1`b0;
#40;

right_in = 1`b1;
sel = 2`b01;
#40;

left_in = 1`b0;
sel = 2`b10;
#40;

par_in = 4`b1010;
sel = 2`b11;
end

always #5 clk = ~clk;

endmodule

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 Output Waveforms

Conclusion:
Hence a Universal Shift Register functionality is verified and Implemented on Spartan-3 FPGA board
using Xilinx 14.7 Tools.

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 EXPT No: 12
Design and Implementation of Johnson Counter on Spartan-6 FPGA DATE:
Aim: Verify the Hardware Implementation of Johnson Counter functionality on Spartan-3 FPGA board
using Xilinx Tools.

Tool Required:
1. Xilinx Tool 14.7v
2. Spatan-6 FPGA Board
Procedure:
Simulation:
1. Double click on Xilinx Design Suite 14.7 Icon.
2. Select new project in file menu.
3. Enter the project name and give location and press Next.
4. Select the Family, Device, Package and speed as per the requirements and press Next.
5. Create a new source by using new source icon or right click on the device/project folder to
create new source.
6. Select the appropriate source type and enter the file name in New Source Wizard window
and press Next.
7. Enter the architecture name – dataflow/behavioral/structural, port name and select the
direction. This will create “.v” source file. Press Next and finish the initial project creation.
8. Write complete VHDL/Verilog code implementation and save.
9. Click on implementation and check for syntax using “Check syntax” option under
synthesize tab. If any error, edit and correct VHDL/Verilog code and repeat check syntax until
zero errors.
10. Double click on ISIM simulator by selecting simulation mode to complete the functional
simulation of your design.
FPGA Hardware Interfacing Procedure:
1. Repeat the steps 1 to 10 from the procedure for software experiments.
2. Make the connection between appropriate FRC’s of the FPGA board and the DIP switch
connector of the GPIOcard-2

Design Implementation
a. Create user constraint file one as follows:
b. In the Hierarchy pane of the Project Navigator Design panel, select the top-level
source file usr.

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 c. Select Project > New Source.
d. Select Implementation Constraints File.
e. Enter usr.ucf as the file name.
f. Click Next.
g. Click Finish.
3. Click on Generate Programming file.
4. Configure Target Device.
5. Select boundary scan to impact the target device.
6. Right click on the impact window to establish a connection between system and FPGA by
selecting “INTIALIZE CHAIN” option.
7. Both prom device and FPGA device gets identified.
8. Now choose device 2(FPGA XC3S400) and hit ok to complete the impact.
9. Now right click on the device to assign a new .bit file by selecting an option “ASSIGN
NEW CONFIGURATION FILE”.
10. Select the corresponding .bit file from the project folder and hit Open
11. Press ‘No’ on the following dialog box.
12. Finally right click on the device(XC3S400) and implement the program by choosing an
option “PROGRAM”
13. Once again select the FPGA device (XC3S400) by clicking ok and now the program will
be identified and succeeded.

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 Block Diagram

Functional Table

CP Q1 Q2 Q3 Q4
0 0 0 0 0
1 1 0 0 0
2 1 1 0 0
3 1 1 1 0
4 1 1 1 1
5 0 1 1 1
6 0 0 1 1
7 0 0 0 1
8 0 0 0 0

Verilog Code

module johnson_counter(clk, reset, count_out);

input clk, reset;

output [3:0] count_out;

reg [3:0] count_temp;

always @(posedge clk or posedge reset)

begin
if(reset==1`b1)
count_temp=4`b0000;
end

else if (clk==1`b1)

count_temp=(count_temp[2:0], ~count_temp[3]);
end
end

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 assign count_out=count_temp;
endmodule

Test Bench

module TB_johnson_counter;
reg clk;
reg reset;
wire [3:0] count_out;

johnson_counter uut(.clk(clk), .reset(reset), .count_out(count_out));

initial begin
reset=1`b1;
clk=1`b0;
#20 reset=1`b0;
#100 $stop;
end
always #5 clk=~clk;

endmodule

Output Waveforms

Conclusion:
Hence a Johnson Counter functionality is verified and Implemented on Spartan-3 FPGA board using
Xilinx 14.7 Tool.

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 VIVA QUESTIONS
1. Why don?t we use just one NMOS or PMOS transistor as a transmission gate?
2. What are set up time & hold time constraints? What do they signify?
3. explain Clock Skew?
4. Why is NAND gate preferred over NOR gate fabrication?
5. What is Body Effect?
6. Why is the substrate in NMOS connected to Ground and in PMOS to VDD?
7. What is the fundamental difference between a MOSFET and BJT ?
8. Why PMOS and NMOS are sized equally in a Transmission Gates?
9. What happens when the PMOS and NMOS are interchanged with one another in an
inverter?
10. Why are pMOS transistor networks generally used to produce high signals, while
nMOS networks are used to product low signals?
11. What is Latch Up? Explain Latch Up with cross section of a CMOS Inverter. How do
you avoid Latch Up?
12. Difference between Synchronous and Asynchronous reset.
13. What is DRC ?
14. What is LVS ?
15. What is RCX ?
16. What are the differences between SIMULATION and SYNTHESIS?
17. What is a counter?
18. What are the differences between flipflop and latch?
19. How can you convert JK flipflop into Jk?
20. What are different types of adders?
21. Give the excitation table for JK flipflop?
22. Give the excitation table for SR flipflop?
23. Give the excitation table for D flipflop?
24. Give the excitation table for T flipflop?
25. What is the race arount condition?
26. What is an amplifier?
27. What is an op-amp?
28. What is differential amplifier?
29. What is elaboration?
30. What is transient analysis?
31. What is DC analysis?
32. What is AC analysis?

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