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Ece428 Uart

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17 views13 pages

Ece428 Uart

Uploaded by

shubhamyadavofficial1
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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ECE 428 Programmable ASIC Design

FPGA Implementation of Universal Asynchronous


Receiver and Transmitter (UART)

Haibo Wang
ECE Department
Southern Illinois University
Carbondale, IL 62901

1-1
Serial Data Transfer
‰ Asynchronous v.s. Synchronous
— Asynchronous transfer does not require clock signal. However, it transfers extra bits
(start bits and stop bits) during data communication
— Synchronous transfer does not transfer extra bits. However, it requires clock signal
Frame

Asynchronous data
Data transfer
Start
bit B0 B1 B2 B3 B4 B5 B6 Stop bits
Parity

clk
Synchronous
Data transfer
data
B0 B1 B2 B3 B4 B5

11-2
1-2
Overview of UART and RS-232
Signal swing +10V, -10V
UART
RS232
TxD
Trans.shift
Shift Reg.
D[7:0]
Rec. Shift Reg.
RxD
Ground
Standard logic level
Interface Baud
rate ckt.

DB9 connector (front view)

ƒ Most materials presented here are from “FPGA Prototyping by Verilog Examples” by Pong Chu.
ƒ You can download the UART chapter of the book at: http://academic.csuohio.edu/chu_p/rtl/fpga_vlog.html

1-3
UART Parameters

‰ Signal is 1 (high voltage) when the system is idle


‰ Start bit is placed before the data and, optionally, stop bits are placed at the end of data
Start bit is 0 and stop bits are 1
‰ LSB is first transmitted or received
‰ Baud rate: number of bits per second; frequently used baud rate: 9600, 19,200
‰ Number of Data bits
‰ Stop bits
‰ Whether parity check is enabled?
‰ Multiplication factor for clock, e.g. x8 clk (means baud rate x 8 = system clock freq.)

1-4
How to Assign UART Parameters
‰ Fix the parameters at the design stage (this example)
‰ Make it programmable with using configuration (mode) register
Example: 8251 chip

7 6 5 4 3 2 1 0 Mode register

Number of Baud Rate


Stop bits Parity enable
0: disable 00: Syn. Mode
00: invalid 1: enable 01: x1 clock
01: 1 bit 10: x16 clock
10: 1.5 bits Character length 11: x64 clock
11: 2 bits
00: 5 bits
01: 6 bits
Parity 10: 7 bits
0: odd 11: 8 bits
1: even
1-5
Block Diagram of UART Receiving Subsystem

‰ Assume N data bits, M stop bits and fCLK=16*baud rate

1-6
ASMD of UART Receiving Subsystem
‰FSM (Finite State Machine)
‰ASM Chart (Algorithmic State Machine)
‰FSMD (Finite State Machine with Data Path)
‰ASMD (ASM with data path)

1-7
HDL Coding for UART Receiving Subsystem
‰ The ASMD chart contains four states: idle, start, data, stop

1-8
HDL Coding for UART Receiving Subsystem
‰ Coding for operations within one state

1-9
Clocking Issue of Receiver Design

‰ Should we use s_tick as clock signal or clock enable signal?

Functionally OK Better

1-10
Interface Circuit of UART Receiving Subsystem

1-11
Complete UART Circuit

1-12
Configure HyperTerminal to test UART Circuit

1-13

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