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System Verilog and UVM Mapping UVM ROOT 1711457791

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23 views3 pages

System Verilog and UVM Mapping UVM ROOT 1711457791

Uploaded by

sallachaitanyakrishna
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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@shraddha_pawankar Date:24/03/24

SV ~ UVM TB Mapping & UVM_ROOT

1) System Verilog
• Top module
• Program
• Top_env
• Sub_env
BFM,Generator,Monitor,Coverage
• Reference Model

2) UVM
Top Module
Top(instances of UVM_Root)
Uvm_test_top
Top_env
Sub environments
Agents
Driver,Sequencer,Monitor,Coverage
Scoreboard

SV ~ UVM Mapping:
1) Program → root
2) Sub_env → agent
3) Display → Verbosity/Severity(uvm_info/warning/error/fatal)
4) Generator → Sequencer
5) BFM → Driver
6) Test is a task → test is a component
7) Tx/pkt → item
8) Scenario/sequence → sequence
9) Mailbox → TLM 1.0/TLM2.0(port,imp,export)
10) New method → create/new
11) $finish → user no need to call(uvm_root will use objections to call
$finish automatically)

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@shraddha_pawankar Date:24/03/24

UVM_ROOT:
• The uvm_root class is an implicit top-level class for
all UVM components
• The uvm_root class is like the boss of all the
components in a UVM (Universal Verification
Methodology) environment.
• It's automatically created for you, and you can access
it through a special variable called uvm_top.

Here's what it does in simple terms:


Parent of All: Every component in UVM, like testbenches, tests, or
individual modules, is connected to this uvm_top boss. If a component
doesn't have a specific parent, it automatically becomes a part of
uvm_top.
Phasing Master: It's like a conductor orchestrating when different parts
of your verification code run. It makes sure things happen in the right
order and at the right time.
Component Finder: If you need to find a specific component in your
UVM hierarchy, you can ask uvm_top to help you find it using its find and
find_all methods.
Global Settings: It handles settings that affect everything, like how
verbose your log files should be. For example, if you want all your log
messages to be at a medium level of detail, you can tell uvm_top to
make it so.
Reporting Hub: If you need to report something, like a warning or an
error, you can use uvm_top to make sure your message gets heard. It's
like a loudspeaker system that everyone can access.
So, uvm_root and its buddy uvm_top are like the big bosses of your
verification world, making sure everything runs smoothly and everyone
knows what's happening.

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@shraddha_pawankar Date:24/03/24

• UVM_ROOT is one of the base classes provided as part of uvm_package.


• Starting point of UVM TB.
• Plays the role of program block in SV.
• Singleton class
• Uvm_root functionality starts with user calling run_test method.
• Top.run_test is called
• UVM testbench top is also used to trigger a test using run_test() call.
• When user calls run_test,whole TB functionality starts.
• Maintain the phases of simulation
• It passes that phase to all the TB component method as arguments.
• Function void build_phase(uvm_phase phase);
• Keeps track of objections raised and dropped;based on this it will decide
to end the simulation
• Instantiates test as uvm_test_top
• ahb_wr_rd _test uvm_test_top
• apb_base_test uvm_test_top;
• Starts all the UVM Phases one by one.
• Root also take care of when to end the simulation

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