Microprocessor All units important QA

-Ronish Neupane

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Unit 1: Fundamentals of Microprocessor

1. Bus Organization of 8085 Microprocessor

● Definition: A bus is a collection of wires used for communication between

components of a microprocessor.
● Types of Buses:
○ Data Bus: Transfers data. Width = 8 bits.
○ Address Bus: Carries memory addresses. Width = 16 bits.
○ Control Bus: Manages control signals like Read/Write.

2. Opcode Fetch Machine Cycle for MVI A, 32H

● Opcode Fetch: The process of fetching the operation code (opcode) from memory.
● Timing Diagram:
○ T1: Address placed on the address bus.
○ T2: Memory read signal activated.
○ T3: Opcode fetched from memory into the instruction register.

3. CPU vs. Microprocessor vs. Microcontroller

● CPU (Central Processing Unit): Performs arithmetic and logic operations.

● Microprocessor:
○ Contains only the CPU.
○ Needs external memory and input/output devices.
○ Example: Intel 8085.
● Microcontroller:
○ CPU + Memory + I/O devices integrated on a single chip.
○ Example: Arduino (based on AVR microcontroller).
4. Instruction Cycle and Timing Diagram for MOV A, B

● Instruction Cycle:
○ Time taken to fetch, decode, and execute an instruction.
● Opcode MOV A, B:
○ Opcode (78H) is fetched.
○ Timing includes fetch (T1, T2, T3) and execute cycles (T4).

5. 8085 Interrupts (Short Notes)

● Definition: Signals that pause the current process to handle high-priority tasks.
● Types:
○ Maskable Interrupts: Can be enabled or disabled (e.g., RST 7.5, RST 6.5).
○ Non-Maskable Interrupts: Always recognized (e.g., TRAP).
● Vector Address: Each interrupt corresponds to a specific memory address.

6. Timing Diagram for MVI A, 35H

● MVI A, 35H:
○ Fetch Cycle: Opcode fetched from memory.
○ Execution Cycle: Data (35H) loaded into register A.

7. Mnemonics, Instruction Cycle, and Machine Cycle

● Mnemonics: Shortcodes for instructions (e.g., MVI, MOV).

● Instruction Cycle: Time for fetch, decode, and execute.
● Machine Cycle: Subset of instruction cycle (e.g., Opcode Fetch, Memory Read).

8. Timing Diagram for MOV B

● Transfers the content of one register to another.

● Steps:
○ Fetch Opcode: Retrieve MOV opcode.
○ Execution: Transfer data from source to destination.

9. Timing Diagram for LXI H, 5070H

● LXI H, 5070H:
○ Fetch Cycle: Opcode fetched.
 ○ Memory Read Cycles: Lower byte (70H) and higher byte (50H) loaded into
the HL pair.
●

Unit Complet Congratulation

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Unit 2: Introduction to Assembly Language Programming

1. Explain 8085 Instruction Addressing Modes with Examples [5] [2018], [2020]

● Addressing Modes:
1. The methods by which the operand of an instruction is specified.

2. Immediate Addressing:
■ Operand is directly specified in the instruction.
■ Example: MVI A, 32H (Load A with 32H).
3. Direct Addressing:
■ Address of the operand is given in the instruction.
■ Example: LDA 2000H (Load A with data from memory location
2000H).
4. Register Addressing:
■ Operand is in a register.
■ Example: MOV A, B (Move data from register B to A).
5. Register Indirect Addressing:
■ Address of the operand is in a register pair.
 ■Example: MOV A, M (Load A with data from memory pointed by HL
pair).
6. Implied Addressing:
■ Operand is implied in the instruction.
■ Example: CMA (Complement accumulator).

2. Explain the Functional Block of 8085 Microprocessor [10] [2018]

● Functional Blocks:
1. Arithmetic and Logic Unit (ALU):
■ Performs arithmetic and logical operations.
2. Registers:
■ Temporary storage for data.
■ Includes accumulator, general-purpose registers, and special-purpose
registers (e.g., PC, SP).
3. Timing and Control Unit:
■ Synchronizes operations using clock signals.
■ Generates control signals for instruction execution.
4. Interrupt Control:
■ Handles external interrupts.
5. Instruction Decoder:
■ Decodes and executes instructions.
6. Address and Data Bus:
■ Address Bus: Specifies memory locations.
■ Data Bus: Transfers data between components.

3. Define ALP Using 8085 to Check if a Number at 8080H is Even or Odd [5] [2019]

Assembly Language Program:

LDA 8080H ; Load the number from memory location 8080H

ANI 01H ; Perform AND operation with 01H

JZ EVEN ; Jump to EVEN if zero flag is set

MVI A, 01H ; Load 01H (Odd) into accumulator

STA 8081H ; Store result in 8081H

HLT ; Halt program

EVEN: MVI A, 00H ; Load 00H (Even) into accumulator STA 8081H ; Store result in 8081H
HLT ; Halt program
---

#### 4. **Define Instruction Set and Classify Instructions in 8085 with Examples** [2+8]
[2019]

- **Instruction Set**:

- A set of all instructions that a microprocessor can execute.

- **Classification**:

1. **Data Transfer Instructions**:

- Example: `MOV A, B`, `LDA 2000H`.

2. **Arithmetic Instructions**:

- Example: `ADD B`, `SUB C`.

3. **Logical Instructions**:

- Example: `CMA`, `ANA B`.

4. **Branching Instructions**:

- Example: `JMP 2000H`, `CALL 3000H`.

5. **Control Instructions**:

- Example: `NOP`, `HLT`.

---

#### 5. **Write a Program to Add Two Tables Starting at 3000H and 3020H** [7] [2020]

- **Problem**: Add two tables of 20 bytes and store the sum and carry at 3040H and 3060H
respectively.

- **Program**:
LXI H, 3000H ; Point to the first table LXI D, 3020H ; Point to the second table LXI B, 3040H
; Point to store sum MVI C, 14H ; Counter for 20 bytes LOOP: MOV A, M ; Load value from
first table INX H ; Increment pointer ADD M ; Add value from second table INX D ; Increment
second pointer MOV M, A ; Store sum in memory INX B ; Increment sum pointer DCR C ;
Decrement counter JNZ LOOP ; Repeat until all bytes are added HLT ; End program

---

#### 6. **Explain the Use of Flags and Different Flags of 8085 with Example** [1+4] [2021]

- **Use of Flags**:

- Indicate the status of operations after execution (e.g., zero, carry).

- **Flags**:

1. **Sign Flag (S)**:

- Set if the result is negative.

2. **Zero Flag (Z)**:

- Set if the result is zero.

3. **Auxiliary Carry Flag (AC)**:

- Set if there is a carry from lower nibble.

4. **Parity Flag (P)**:

- Set if result has even parity.

5. **Carry Flag (CY)**:

- Set if there is a carry out from the MSB.

- **Example**:

- Instruction: `ADD B`.

- Result: Accumulator = 05H, Carry = 1 → Carry flag set.

---
#### 7. **Program to Sort 10 Bytes of Data in Ascending Order** [7] [2021 Batch]

- **Program**:

LXI H, 7050H ; Point to the start of the data MVI C, 0AH ; Number of elements SORT: MOV
D, M ; Load the first element INX H ; Point to the next element CMP M ; Compare with the
next element JC SKIP ; Skip if already in order XCHG ; Exchange if out of order SKIP: DCX
H ; Point back to the previous element DCR C ; Decrement counter JNZ SORT ; Repeat for
remaining elements HLT ; Halt program

Unit Complet Congratulation

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Unit 3: Basic Computer Architecture

1. Memory Hierarchy with Diagram [5] [2018]

● Definition: Memory hierarchy is the structure used to organize computer memory

based on speed, cost, and capacity.
● Levels:
○ Registers: Fastest, smallest, directly accessed by CPU.
○ Cache Memory: Small-sized, stores frequently accessed data.
○ Main Memory (RAM): Moderate speed, holds currently used programs/data.
○ Secondary Storage: Slower, high-capacity (e.g., HDD, SSD).
○ Tertiary Storage: Very slow, used for backup (e.g., tapes).
Diagram:
Registers
↑
Cache
↑
RAM
↑
Secondary Storage
↑
Tertiary Storage

2. What is Cache Memory? Explain the Elements of Cache Design [5] [2019]

● Definition: Cache memory is a high-speed memory close to the CPU, storing

frequently accessed data to reduce latency.
● Elements of Cache Design:
○ Cache Size: Affects performance and cost.
○ Block Size: Determines how much data is transferred between cache and
main memory.
○ Mapping Function: How memory addresses are mapped to cache (Direct,
Associative, Set-Associative).
○ Replacement Policy: Determines which cache block to replace (e.g., LRU,
FIFO).
○ Write Policy: Manages updates (Write-Through or Write-Back).

3. Short Notes on Structure of Hard Disk [2.5] [2019]

● Definition: Hard disks are secondary storage devices that store data magnetically on
spinning platters.
● Structure:
○ Platters: Circular disks coated with magnetic material.
○ Spindle: Rotates the platters.
○ Read/Write Head: Reads or writes data.
○ Actuator Arm: Moves the head across the platter surface.
○ Tracks, Sectors, and Cylinders: Logical divisions of the platter for data
organization.

4. Requirement of Common Bus System? Explain with Figure [5] [2021]

● Definition: A common bus system allows multiple components (CPU, memory, I/O
devices) to share a single data communication path.
● Requirements:
○ Efficiency: Reduces the number of connections needed.
○ Control Signals: Coordinates access to the bus (e.g., Read/Write, Select).
○ Data and Address Lines: Separate pathways for data transfer and memory
addressing.
Diagram:
CPU ↔ Bus ↔ Memory
↔ Bus ↔ I/O Devices

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Unit 4: Microprogrammed Control

1. Organization of Microprogrammed Control Unit [5] [2018], [2019]

● Definition: A microprogrammed control unit uses a sequence of microinstructions to

generate control signals for executing instructions.
● Components:
○ Control Memory (CM): Stores microinstructions.
○ Control Address Register (CAR): Holds the address of the current
microinstruction.
○ Control Data Register (CDR): Stores the microinstruction fetched from
control memory.
○ Sequencer: Decides the address of the next microinstruction (based on
conditions).
○ Decoder: Converts microinstructions into control signals.
● Working:
○ Fetch a microinstruction.
○ Decode it into control signals.
○ Execute it.
○ Determine the next address using the sequencer.
● Advantages:
○ Flexibility in design.
○ Easier to modify and debug.
Diagram:
Instruction Register → Control Address Register → Control Memory → Control Data
Register → Decoder → Control Signals

2. Design and Control Logic of Accumulator [10] [2018]

● Accumulator: A special register in the CPU that stores intermediate arithmetic and
logical results.
● Design:
○ Input: Data from memory or ALU.
○ Output: Data sent to ALU or memory.
○ Control Signals:
■ Load: Load data into the accumulator.
■ Clear: Reset the accumulator.
■ Enable: Output data from the accumulator.
● Control Logic:
○ Uses flip-flops and logic gates to manage operations (e.g., ADD, SUB, AND,
OR).
● Example:
○ ADD operation: Accumulator = Accumulator + Operand.

3. Symbolic Microprogram for Instruction FETCH Routine [2+8] [2019]

● Definition: A symbolic microprogram uses human-readable symbols for

microinstructions.
● Instruction FETCH Routine:
○ Steps:
1. Fetch the instruction from memory.
2. Place it in the instruction register.
3. Update the program counter (PC).

Symbolic Microprogram:
T1: MAR ← PC // Load memory address from PC
T2: MDR ← Memory[MAR] // Fetch instruction
T3: IR ← MDR // Load instruction into instruction register
T4: PC ← PC + 1 // Increment PC

4. Organization of Microprogram Sequencer for Control Memory [10] [2019]

● Microprogram Sequencer:
 1. Generates the address of the next microinstruction.
2. Works based on current microinstruction and status flags.
● Components:
1. Address Selection Logic: Determines the next address (e.g., increment,
branch).
2. Branch Logic: Handles conditional branches.
3. Control Memory: Stores microinstructions.

Diagram:
Current Address → Sequencer → Control Memory → Control Data Register → Control
Signals

5. Symbolic Microinstruction and Microinstruction Format [5] [2021]

● Symbolic Microinstruction:
○ A human-readable representation of a microinstruction.
○ Example: ADD A, B means "add contents of A and B and store in A."
● Microinstruction Format:
○ Fields:
■ Opcode Field: Specifies operation.
■ Source Field: Specifies source register.
■ Destination Field: Specifies target register.
■ Address Field: Indicates the next microinstruction.

6. Steps of Address Sequencing and Address Selection for Control Memory [5+5]
[2021]

● Steps of Address Sequencing:

○ Initialize with the starting address.
○ Fetch the current microinstruction.
○ Decode and execute the instruction.
○ Determine the next address (sequential, conditional, or branch).
● Address Selection:
○ Uses multiplexers to choose between:
1. Next sequential address.
2. Branch address.
3. Interrupt address.

Diagram:
Sequencer → MUX → Control Memory

○
7. Control Unit’s Role in Determining Instruction Type [5] [2021]

● Steps:
1. Fetch the instruction.
2. Decode the opcode to determine the type (arithmetic, logical, branch).
3. Generate control signals accordingly.

8. Hardwired vs. Microprogrammed Control Unit [2+3] [2021]

Feature Hardwired Control Unit Microprogrammed Control Unit

Design Uses fixed combinational logic Uses microinstructions stored in memory

Flexibility Difficult to modify Easier to modify/debug

Speed Faster Slower

Cost Higher Lower

9. Structure of Control Unit and Its Requirements [8] [2021]

● Structure:
○ Input: Instruction register, status flags.
○ Output: Control signals for various CPU components.
○ Components:
■ Decoder: Decodes instructions.
■ Sequencer: Determines execution sequence.
■ Control Logic: Generates appropriate signals.
● Requirements:
○ Efficient instruction execution.
○ Flexibility for complex instructions.

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Unit 5: Central Processing Unit (CPU)

1. Define Control Word. Explain the Procedure for Generating Control Word for
Specific Operation [5] [2018]

● Control Word:
1. A binary encoded signal used to control various operations in the CPU, such
as data transfer and arithmetic operations.
2. Specifies micro-operations for components like ALU, memory, and I/O.
● Procedure:
1. Decode the instruction to identify the operation.
2. Determine the required micro-operations.
3. Generate binary codes for each operation (e.g., read, write, ALU operation).
4. Combine these codes into a single control word.

2. Explain Different Data Transfer and Manipulation Instructions with Examples [10]
[2018]

● Data Transfer Instructions:

○ Definition: Move data between registers, memory, and I/O.
○ Examples:
■ MOV A, B: Copies data from register B to A.
■ LDA 2000H: Loads data from memory location 2000H into
accumulator.
■ STA 3000H: Stores accumulator data into memory at 3000H.
● Data Manipulation Instructions:
○ Definition: Perform arithmetic and logical operations.
○ Examples:
■ Arithmetic: ADD B, SUB C.
■ Logical: ANA B (AND), XRA C (XOR).
■ Increment/Decrement: INR A, DCR B.

3. What is Instruction Mapping? Explain How to Convert an Instruction Code to a

Microinstruction Address [2+3] [2020]

● Instruction Mapping:
 1. Translating an instruction's opcode into a microinstruction address in control
memory.
● Conversion Steps:
1. Decode the opcode from the instruction register.
2. Use the decoded opcode as an address or index for control memory.
3. Fetch the microinstructions from the corresponding address.

4. Define Stack. Explain the Stack Organization [1+4] [2020]

● Stack:
○ A Last-In-First-Out (LIFO) data structure used for temporary storage during
program execution.
● Stack Organization:
○ Structure:
■ Operates via a Stack Pointer (SP) register pointing to the top of the
stack.
■ Data is pushed onto or popped from the stack.
○ Operations:
■ Push: Add data to the stack.
■ Pop: Remove data from the stack.

Example:
PUSH B → Store contents of register B on the stack.
POP A → Retrieve top stack value into register A.

5. Typical Characteristics of CISC Instruction Set Architecture [5] [2020]

● Definition: CISC (Complex Instruction Set Computer) architecture uses complex

instructions capable of performing multiple tasks.
● Characteristics:
1. Large Instruction Set: Many instructions available.
2. Variable Instruction Length: Instructions vary in size.
3. Complex Addressing Modes: Supports multiple addressing modes (e.g.,
direct, indirect).
4. Fewer Registers: Relies more on memory.
5. Microprogrammed Control: Instructions executed through microprograms.

6. Stack and Register Stack Organization [1+4] [2021 Batch]

● Stack: (Definition as above)

● Register Stack Organization:
○ Uses a set of CPU registers organized as a stack.
 ○ Faster than memory-based stacks.
○ Structure:
■ Top of stack (TOS) points to the active register.
■ Push/Pop operations move data between registers.
○ Elements:
■ Register Set
■ Stack Pointer (SP)
■ Control Logic.

7. Differences Between Branch Instruction, Call Subroutine, and Program Interrupt [5]
[2021]
Feature Branch Instruction Call Subroutine Program Interrupt

Purpose Transfer control within Call a reusable Handle external/internal

program. code block. events.

Control No Returns to main Resumes interrupted

Return program. program.

Triggered Explicit instruction. Explicit instruction. Hardware/software

By signal.

Example JMP 2000H CALL 3000H Timer interrupt.

8. Define Word Count [2] [2021]

● Word Count:
○ The number of words (fixed-sized data units) in a block of memory or during a
transfer operation.
○ Example: If word size = 16 bits and transfer size = 32 bits, word count = 2.

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Unit 6: Pipeline, Vector Processing, and Multiprocessors

1. Define Instruction Pipeline. Explain the Four-Segment Instruction Pipeline with

Example [5] [2018], [2019]

● Instruction Pipeline:

○ A technique where multiple instructions are overlapped during execution to

improve CPU efficiency.
○ Each instruction is divided into stages and processed simultaneously in a
pipeline.
● Four-Segment Instruction Pipeline:

○ Fetch Instruction (FI): Fetch the instruction from memory.

○ Decode Instruction (DI): Decode the fetched instruction to understand the
operation.
○ Execute Instruction (EI): Perform the operation specified by the instruction.
○ Write Back (WB): Store the result in the destination register/memory.
● Example:

○ While one instruction is in the decode stage, another can be fetched, and
another can be executed, reducing idle time.

2. Explain Arithmetic Pipeline with Example [5] [2020]

● Arithmetic Pipeline:

○ Used to speed up arithmetic operations like addition, multiplication, and

division by breaking them into smaller stages.
○ Example: Floating-point addition is divided into:
1. Compare exponents.
2. Align the mantissas.
3. Perform addition.
4. Normalize the result.
● Advantages:
 ○ Improved performance for repetitive arithmetic tasks.
○ Efficient resource utilization.

3. What is Parallel Processing? Explain Benefits and Classifications by M.J. Flynn

[2+2+6] [2020]

● Parallel Processing:

1. Multiple processors or cores work simultaneously to execute tasks, enhancing

computational speed.
● Benefits:

1. Increased throughput.
2. Reduced execution time.
3. Efficient resource usage.
● Flynn's Classification:

1. SISD (Single Instruction, Single Data): Traditional sequential processors.

2. SIMD (Single Instruction, Multiple Data): Executes the same instruction on
multiple data (e.g., GPUs).
3. MISD (Multiple Instruction, Single Data): Rare, used for fault tolerance.
4. MIMD (Multiple Instruction, Multiple Data): Different processors execute
different instructions on different data (e.g., multiprocessors).

4. What is Pipeline Conflict? Explain Data Dependency and Handling of Branch

Instruction [1+4] [2021 Batch]

● Pipeline Conflict:

1. Occurs when two or more instructions in a pipeline interfere with each other,
causing delays.
● Types of Conflicts:

1. Data Dependency:

■ When one instruction depends on the result of a previous instruction.

■ Example: ADD R1, R2 followed by MOV R3, R1.
2. Handling:

■ Use techniques like operand forwarding or introducing stalls.

3. Control Dependency:

■ Occurs with branch instructions.

■ Solution: Use branch prediction or speculative execution.
5. Discuss Four-Segment Instruction Pipeline with Suitable Diagram [10] [2021 Batch]

● Four-Segment Pipeline:
○ The same as explained earlier under Instruction Pipeline.

Diagram:
Time → | FI | DI | EI | WB |

| FI | DI | EI | WB |

| FI | DI | EI | WB |

○
○ Each stage works on different instructions simultaneously.

6. What Do You Mean by Pipelining Hazards? Explain Briefly [5] [2021]

● Pipelining Hazards:
1. Conditions that prevent the next instruction in the pipeline from executing in
the next cycle.
● Types:
1. Structural Hazard: Resource conflict (e.g., two instructions need the same
hardware).
2. Data Hazard: Dependency between instructions.
3. Control Hazard: Branch instructions altering the control flow.

7. Short Notes on Vector Processing [2.5] [2021]

● Vector Processing:
○ A technique to perform operations on entire arrays or vectors of data in a
single instruction.
○ Used in applications like scientific computing, AI, and graphics processing.
● Features:
○ Operates on multiple data points simultaneously.
○ Uses vector registers and pipelines for efficiency.

Congratulations You have completed all the course

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