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Physical Design Mini Project

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Tara Sharma
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386 views22 pages

Physical Design Mini Project

Uploaded by

Tara Sharma
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Content

• Project Overview
• Physical Design Flow
• Input to Physical Design
• Synthesis
• Floor Planning
• Power Planning
• Placement
• Clock Tree Synthesis
• Routing
• Static Timing Analysis
• Report
Project Overview
Objective: Design and optimize a 1x3 Router on the 32nm technology node
using Synopsys Fusion Compiler.

Key Focus Areas:


1. Efficient floorplan with minimal congestion.
2. Meet timing requirements (setup, hold, clock skew).
3. Power efficiency and reliability optimization.
Physical Design Flow
The Physical Design flow is the Back End where the RTL is converted into GDS II
Input to Physical Design
• Netlist ( .v): A logical representation of the design, typically in formats like Verilog or
VHDL, that specifies the circuit's connectivity.
• Liberty File (.lib): Contains information about the timing, power, and functional
characteristics of standard cells used in the design.
• Design Constraints File (.sdc): Specifies timing, area, and power constraints for the
design.
• Floorplan and Pin Constraints: Defines the chip's physical dimensions, block
placement, and locations of input/output pins.
• Technology File (.tf): Includes details about the manufacturing process, such as metal
layer stack-up, design rules, and parasitic models.
• Design Exchange Format (.def): Describes the design layout, including floorplan, cell
placement, and routing information.
• Power Intent File (.upf): Specifies the power domains and power management
strategies for low-power designs.
• Table Lookup Plus File (.tluplus): These files are crucial in the backend flow of VLSI
physical design, specifically for parasitic extraction and delay calculation. They provide
interconnect resistance and capacitance values.
Inputs to Physical Design cntd
set TECH_FILE "../../ref/tech/saed32nm_1p9m.tf“
set REFLIB "../../ref/CLIBs“
set REFERENCE_LIBRARY [join "
$REFLIB/saed32_hvt.ndm
$REFLIB/saed32_lvt.ndm
$REFLIB/saed32_rvt.ndm
$REFLIB/saed32_sram_lp.ndm"

create_lib -technology $TECH_FILE -ref_libs


$REFERENCE_LIBRARY router_PD.dlib

analyze -format verilog [glob ../rtl/router_*.v]


elaborate router_top
set_top_module router_top

source ../router/rtr_tech_setup.tcl

source ../mcmm/mcmm_router.tcl
Synthesis
Synthesis is the process of converting the RTL into a gate-level netlist, which consists of
WVGtech Cells.

Input Files: Technology files, Verilog files Output Files: GLN netlist, Sdc
Refernce Libraries
Floor Planning
Floor Planning is the Process where the die area, core area will be specified and also the
macros, standard cells and the I/O ports are placed at this stage.

initialize_floorplan -boundary {{0.000 110} {0.000


0.000} { 120 0.000} {120 110} }
-core_offset {8}\
-core_utilization 0.7
shape_block

create_voltage_area_shapes -region {{0.00 0.000}


{101.0800 101.9920}} \
–voltage_areas fifo_mod\
-guard_band {0.25 2 3 0.25}

set_block_pin_constraints -self -allowed_layers


{M3 M4 M5 M6}
place_pins -self
Power Planning
The UPF file defines power-related details such as supply ports, power domains, and
level shifters, where we intent the power details.

• create_supply_net

• create_supply_set

• create_power_domain

• create_supply_port

• connect_supply_net

• set_level_shifter

• add_power_state

load_upf ../router/rtr_upf.upf
Power Planning cntd.
Power Planning cntd.
By using Power Domain Network (PDN) we will distribute equal power to all the

cells in the design.


• connect_pg_net

• create_pg_ring_pattern

• create_pg_mesh_pattern

• create_pg_std_cell_conn_pattern

• set_pg_strategy

• compile_pg

source ../router/rtr_pns.tcl
Power Planning Reports
Reports of Power and Ground Planning
• Check_pg_drc

• Check_pg_connecitivity

• Check_pg_missing_vias
Placement
In Fusion Compiler the Placement of cells will be done by using the command
“Compile_Fusion”. Which will do seven steps. Another command is “Place_opt”.

• Initial_map

• Logic_opto

• Initial_place

• Initial_drc

• Initial_opto

• Final_place

• Final_opto
Placement
Initial_Place Final_opto
Clock Tree Synthesis
Clock Tree Synthesis is a process where we provide the clock to all the sink nodes of the
cells with minimum skew or zero skew. While doing cts we will provide the ndr rules.

set CTS_CELLS [get_lib_cells "*/NBUFF*LVT *


/NBUFF*RVT \*/INVX*_LVT
*/INVX*RVT \*/CGL* */LSUP*
*/DFF* "]

set_dont_touch $CTS_CELLS false


set_lib_cell_purpose -exclude cts [get_lib_cells]
set_lib_cell_purpose -include cts $CTS_CELLS

set_app_options -name clock_opt.flow.enable_ccd


-value false

Clock_opt –from build_clock –to final_opt

Source ../router/rtr_ndr.tcl
Clock Tree Synthesis cntd.
Pre CTS Stage Post CTS Stage
Routing
Routing is the process where the interconnections between all the cells will be made
physically at this stage. By using “Route_auto”.

Route_auto

Route_opt

Route_eco
Routing cntd.
After competing the checks of routing, we generate the gds – II file.
Static Timing Analysis
Static Timing Analysis is a method used to evaluate all the paths in a design to confirm
whether they meet the required timing constraints.

Input Files

• .sdc
• .spef
• Routed netlist
• Libraries

Output Files

• Timing Reports
• Eco Files
Reports
Report_ timing Report_design
Reports
Check_lvs

Check_legality
Reports

Report_congestion

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