FINAL

Advanced
Am27C256 Micro
256 Kilobit (32,768 x 8-Bit) CMOS EPROM Devices

DISTINCTIVE CHARACTERISTICS
■ Fast access time ■ Latch-up protected to 100 mA from –1 V to
— 55 ns VCC + 1 V
■ Low power consumption ■ High noise immunity
— 20 µA typical CMOS standby current ■ Versatile features for simple interfacing
■ JEDEC-approved pinout — Both CMOS and TTL input/output
compatibility
■ Single +5 V power supply
— Two line control functions
■ ±10% power supply tolerance available
■ Standard 28-pin DIP, PDIP, 32-pin TSOP and
■ 100% Flashrite programming
PLCC packages
— Typical programming time of 4 seconds

GENERAL DESCRIPTION
The Am27C256 is a 256K-bit ultraviolet erasable pro- controls, thus eliminating bus contention in a multiple
grammable read-only memory. It is organized as 32K bus microprocessor system.
words by 8 bits per word, operates from a single +5 V AMD’s CMOS process technology provides high speed,
supply, has a static standby mode, and features fast sin- low power, and high noise immunity. Typical power con-
gle address location programming. Products are avail- sumption is only 80 mW in active mode, and 100 µW in
able in windowed ceramic DIP packages as well as plas- standby mode.
tic one time programmable (OTP) PDIP, TSOP, and
PLCC packages. All signals are TTL levels, including programming sig-
nals. Bit locations may be programmed singly, in blocks,
Typically, any byte can be accessed in less than 55 ns, or at random. The Am27C256 supports AMD’s Flashrite
allowing operation with high-performance microproces- programming algorithm (100 µs pulses) resulting in typi-
sors without any WAIT states. The Am27C256 offers cal programming time of 4 seconds.
separate Output Enable (OE) and Chip Enable (CE)

BLOCK DIAGRAM
Data Outputs
VCC
DQ0–DQ7
VSS
VPP
Output Enable
OE Chip Enable Output
CE and Buffers
Prog Logic

Y Y
Decoder Gating

A0–A14
Address 262,144
Inputs X
Bit Cell
Decoder
Matrix

08007H-1

Publication# 08007 Rev. H Amendment /0

2-32 Issue Date: May 1995
 AMD

PRODUCT SELECTOR GUIDE

Family Part No. Am27C256
Ordering Part No:
VCC ± 5% -255
VCC ± 10% -55 -70 -90 -120 -150 -200
Max Access Time (ns) 55 70 90 120 150 200 250
CE (E) Access Time (ns) 55 70 90 120 150 200 250
OE (G) Access Time (ns) 35 40 40 50 50 50 50

CONNECTION DIAGRAMS
Top View
DIP PLCC

A13
A12

A14
VCC
VPP
1 28

DU
VPP VCC

A7
A12 2 27 A14
4 3 2 1 32 31 30
A7 3 26 A13
A6 5 29 A8
A6 4 25 A8 A9
A5 6 28
A5 5 24 A9 A4 7 27 A11
A4 6 23 A11 A3 8 26 NC
A3 7 22 OE (G) A2 9 25 OE (G)
A2 8 21 A10 A1 10 24 A10
A1 9 20 CE (E) A0 11 23 CE (E)
A0 10 19 DQ7 NC 12 22 DQ7

11 18 DQ0 13 21 DQ6
DQ0 DQ6
14 15 16 17 18 19 20
DQ1 12 17 DQ5
DQ1

DQ4
DQ3

DQ5
DQ2

DU
VSS

DQ2 13 16 DQ4

VSS 14 15 DQ3
08007H-2 08007H-3

Notes:
1. JEDEC nomenclature is in parentheses.

Am27C256 2-33
 AMD

CONNECTION DIAGRAM
TSOP*

OE (G) 1 32 NC
A11 2 31 A10
A9 3 30 CE (E)
A8 4 29 DQ7
A13 5 28 DQ6
NC 6 27 DQ5
A14 7 26 DQ4
VCC 8 25 DQ3
VPP 9 24 VSS
NC 10 23 DQ2
A12 11 22 DQ1
A7 12 21 DQ0
A6 13 20 NC
A5 14 19 A0
A4 15 18 A1
A3 16 17 A2

08007H-4
*Contact local AMD sales office for package availability

Standard Pinout

PIN DESIGNATIONS LOGIC SYMBOL

A0–A14 = Address Inputs
CE (E) = Chip Enable
15
DQ0–DQ7 = Data Inputs/Outputs
A0–A14
OE (G) = Output Enable Input
VCC = VCC Supply Voltage
8
VPP = Program Voltage Input DQ0–DQ7
VSS = Ground
DU = Don’t Use CE (E)

OE (G)

08007H-5

2-34 Am27C256
 AMD

ORDERING INFORMATION
UV EPROM Products
AMD Standard products are available in several packages and operating ranges. The order number (Valid Combination) is
formed by a combination of:

AM27C256 -55 D C B

OPTIONAL PROCESSING
Blank = Standard Processing
B = Burn-in

TEMPERATURE RANGE
C = Commercial (0°C to +70°C)
I = Industrial (–40°C to +85°C)
E = Extended Commercial (–55°C to +125°C)

PACKAGE TYPE
D = 28-Pin Ceramic DIP (CDV028)

SPEED OPTION
See Product Selector Guide and Valid Combinations

DEVICE NUMBER
Am27C256
256 Kilobit (32,768 x 8-Bit) CMOS UV EPROM

Valid Combinations Valid Combinations

AM27C256-55 DC, DCB, DI, DIB Valid Combinations list configurations planned to be
supported in volume for this device. Consult the lo-
AM27C256-70
cal AMD sales office to confirm availability of specific
AM27C256-90 valid combinations and to check on newly released
DC, DCB, DI,
AM27C256-120 combinations.
DIB, DE, DEB
AM27C256-150
AM27C256-200
AM27C256-255 DC, DCB, DI, DIB

Am27C256 2-35
 AMD

ORDERING INFORMATION
OTP Products
AMD Standard products are available in several packages and operating ranges. The order number (Valid Combination) is
formed by a combination of:

AM27C256 -55 P C

OPTIONAL PROCESSING
Blank = Standard Processing

TEMPERATURE RANGE
C = Commercial (0°C to +70°C)
I = Industrial (–40°C to + 85°C)

PACKAGE TYPE
P = 28-Pin Plastic DIP (PD 028)
J = 32-Pin Rectangular Plastic Leaded Chip
Carrier (PL 032)
E = 32-Pin TSOP (TS 032)

SPEED OPTION
See Product Selector Guide and Valid Combinations

DEVICE NUMBER
Am27C256
256 Kilobit (32,768 x 8-Bit) CMOS OTP EPROM

Valid Combinations Valid Combinations

AM27C256-55 JC, PC, EC Valid Combinations list configurations planned to be
AM27C256-70 supported in volume for this device. Consult the lo-
cal AMD sales office to confirm availability of specific
AM27C256-90 valid combinations and to check on newly released
JC, PC, EC,
AM27C256-120 combinations.
JI, PI, EI
AM27C256-150
AM27C256-200
AM27C256-255

2-36 Am27C256
 AMD

FUNCTIONAL DESCRIPTION
Erasing the Am27C256 OE High will program that Am27C256. A high-level CE
input inhibits the other Am27C256 devices from
In order to clear all locations of their programmed con-
being programmed.
tents, it is necessary to expose the Am27C256 to an
ultraviolet light source. A dosage of 15 W sec/cm2 is Program Verify
required to completely erase an Am27C256. This dos- A verify should be performed on the programmed bits to
age can be obtained by exposure to an ultraviolet amp— determine that they were correctly programmed. The
wavelength of 2537 A° —with intensity of 12,000 µW/cm2 verify should be performed with OE at VIL, CE at VIH, and
for 15 to 20 minutes. The Am27C256 should be directly VPP between 12.5 V to 13.0 V.
under and about one inch from the source and all filters
should be removed from the UV light source prior Auto Select Mode
to erasure. The auto select mode allows the reading out of a binary
It is important to note that the Am27C256 and similar code from an EPROM that will identify its manufacturer
devices will erase with light sources having wavelengths and type. This mode is intended for use by programming
shorter than 4000 A° . Although erasure times will be equipment for the purpose of automatically matching
much longer than with UV sources at 2537 A° , exposure the device to be programmed with its corresponding
to fluorescent light and sunlight will eventually erase the programming algorithm. This mode is functional in the
Am27C256 and exposure to them should be prevented 25°C ± 5°C ambient temperature range that is required
to realize maximum system reliability. If used in such an when programming the Am27C256.
environment, the package window should be covered To activate this mode, the programming equipment
by an opaque label or substance. must force 12.0 V ± 0.5 V on address like A9 of the
Am27C256. Two identifier bytes may then be se-
Programming the Am27C256 quenced from the device outputs by toggling address
Upon delivery or after each erasure the Am27C256 has line A0 from VIL to VIH. All other address lines must be
all 262,144 bits in the “ONE” or HIGH state. “ZEROs” held at VIL during auto select mode.
are loaded into the Am27C256 through the procedure
of programming. Byte 0 (A0 = VIL) represents the manufacturer code, and
byte 1 (A0 = VIH), the device code. For the Am27C256,
The programming mode is entered when 12.75 V
these two identifier bytes are given in the Mode Select
± 0.25 V is applied to the VPP pin, OE is at VIH, and CE is Table. All identifiers for manufacturer and device codes
at VIL. will possess odd parity, with the MSB (DQ7) defined as
For programming, the data to be programmed is applied the parity bit.
8 bits in parallel to the data output pins.
Read Mode
The Flashrite algorithm reduces programming time by
The Am27C256 has two control functions, both of which
using 100 µs programming pulses and by giving each
must be logically satisfied in order to obtain data at the
address only as many pulses as is necessary in order to
outputs. Chip Enable (CE) is the power control and
reliably program the data. After each pulse is applied to
should be used for device selection. Output Enable (OE)
a given address, the data in that address is verified. If
is the output control and should be used to gate data to
the data does not verify, additional pulses are given until
the output pins, independent of device selection. As-
it verifies or the maximum is reached. This process is re-
suming that addresses are stable, address access time
peated while sequencing through each address of the
(tACC) is equal to the delay from CE to output (tCE). Data
Am27C256. This part of the algorithm is done at
is available at the outputs tOE after the falling edge of
VCC = 6.25 V to assure that each EPROM bit is pro-
OE, assuming that CE has been LOW and addresses
grammed to a sufficiently high threshold voltage. After
the final address is completed, the entire EPROM mem- have been stable for at least tACC–tOE.
ory is verified at VCC = VPP = 5.25 V. Standby Mode
Please refer to Section 6 for programming flow chart The Am27C256 has a CMOS standby mode which re-
and characteristics. duces the maximum VCC current to 100 µA. It is placed in
CMOS-standby when CE is at VCC ± 0.3 V. The
Program Inhibit Am27C256 also has a TTL-standby mode which re-
Programming of multiple Am27C256 in parallel with dif- duces the maximum VCC current to 1.0 mA. It is placed in
ferent data is also easily accomplished. Except for CE, TTL-standby when CE is at VIH. When in standby mode,
all like inputs of the parallel Am27C256 may be com- the outputs are in a high-impedance state, independent
mon. A TTL low-level program pulse applied to an of the OE input.
Am27C256 CE input with VPP = 12.75 V ± 0.25 V, and

Am27C256 2-37
 AMD

Output OR-Tieing System Applications

To accommodate multiple memory connections, a two- During the switch between active and standby condi-
line control function is provided to allow for: tions, transient current peaks are produced on the rising
■ Low memory power dissipation and falling edges of Chip Enable. The magnitude of
these transient current peaks is dependent on the out-
■ Assurance that output bus contention will not occur
put capacitance loading of the device. At a minimum, a
It is recommended that CE be decoded and used as the 0.1-µF ceramic capacitor (high frequency, low inherent
primary device-selecting function, while OE be made a inductance) should be used on each device between
common connection to all devices in the array and con- VCC and VSS to minimize transient effects. In addition, to
nected to the READ line from the system control bus. overcome the voltage drop caused by the inductive ef-
This assures that all deselected memory devices are in fects of the printed circuit board traces on EPROM ar-
low-power standby mode and that the output pins are rays, a 4.7-µF bulk electrolytic capacitor should be used
only active when data is desired from a particular between VCC and VSS for each eight devices. The loca-
memory device. tion of the capacitor should be close to where the power
supply is connected to the array.

MODE SELECT TABLE

Pins
Mode CE OE A0 A9 VPP Outputs

Read VIL VIL X X X DOUT

Output Disable X VIH X X X High-Z

Standby (TTL) VIH X X X X High-Z

Standby (CMOS) VCC + 0.3 V X X X X High-Z

Program VIL VIH X X VPP DIN

Program Verify VIH VIL X X VPP DOUT

Program Inhibit VIH VIH X X VPP High-Z

Manufacturer
Auto Select Code VIL VIL VIL VH X 01H
(Note 3)
Device Code VIL VIL VIH VH X 10H
Notes:
1. VH = 12.0 V + 0.5 V
2. X = Either VIH or VIL
3. A1–A8 = A10–A14 = VIL
4. See DC Programming Characteristics for VPP voltage during programming.

2-38 Am27C256
 AMD

ABSOLUTE MAXIMUM RATINGS OPERATING RANGES

Storage Temperature Commercial (C) Devices
OTP Products . . . . . . . . . . . . . . . –65°C to +125°C Ambient Temperature (TA) . . . . . . . 0°C to +70°C
All Other Products . . . . . . . . . . . . –65°C to +150°C Industrial (I) Devices
Ambient Temperature Ambient Temperature (TA) . . . . . –40°C to +85°C
with Power Applied . . . . . . . . . . . . . –55°C to +125°C
Extended Commercial (E) Devices
Voltage with Respect To VSS Ambient Temperature (TA) . . . . –55°C to +125°C
All pins except A9,VPP,VCC Supply Read Voltages
(Note 1) . . . . . . . . . . . . . . . –0.6 V to VCC + 0.5 V VCC for Am27C256-XX5 . . . . . +4.75 V to +5.25 V
A9 and VPP (Note 2) . . . . . . . . . . –0.6 V to +13.5 V VCC for Am27C256-XX0 . . . . . +4.50 V to +5.50 V
VCC . . . . . . . . . . . . . . . . . . . . . . . –0.6 V to +7.0 V Operating ranges define those limits between which the func-
Notes: tionality of the device is guaranteed.
1. Minimum DC voltage on input or I/O pins is –0.5 V. During
transitions, the inputs may overshoot VSS to –2.0 V for peri-
ods of up to 20 ns. Maximum DC voltage on input andI/O
pins is VCC + 0.5 V which may overshoot to VCC + 2.0 V for
periods up to 20 ns.
2. For A9 and VPP the minimum DC input is –0.5 V. During
transitions, A9 and VPP may overshoot VSS to –2.0 V for
periods of up to 20 ns. A9 and VPP must not exceed 13.5 V
for any period of time.

Stresses above those listed under “Absolute Maximum Rat-

ings” may cause permanent damage to the device. This is a
stress rating only; functional operation of the device at these
or any other conditions above those indicated in the opera-
tional sections of this specification is not implied. Exposure of
the device to absolute maximum rating conditions for ex-
tended periods may affect device reliability.

Am27C256 2-39
 AMD

DC CHARACTERISTICS over operating range unless otherwise specified.

(Notes 1, 2 and 4)
Parameter
Symbol Parameter Description Test Conditions Min Max Unit
VOH Output HIGH Voltage IOH = –400 µA 2.4 V
VOL Output LOW Voltage IOL = 2.1 mA 0.45 V
VIH Input HIGH Voltage 2.0 VCC + 0.5 V
VIL Input LOW Voltage –0.5 +0.8 V
ILI Input Load Current VIN = 0 V to +VCC 1.0 µA
ILO Output Leakage Current VOUT = 0 V to +VCC C/I Devices 1.0
µA
E Devices 5.0
ICC1 VCC Active Current CE = VIL, f = 10 MHz, 25 mA
(Note 3) IOUT = 0 mA
ICC2 VCC TTL Standby Current CE = VIH 1.0 mA
ICC3 VCC CMOS Standby Current CE = VCC ± 0.3 V 100 µA
IPP1 VPP Current During Read CE = OE = VIL, VPP = VCC 100 µA
Notes:
1. VCC must be applied simultaneously or before VPP, and removed simultaneously or after VPP.
2. Caution: The Am27C256 must not be removed from (or inserted into) a socket when VCC or VPP is applied.
3. ICC1 is tested with OE = VIH to simulate open outputs.
4. Minimum DC Input Voltage is –0.5 V. During transitions, the inputs may overshoot to –2.0 V for periods less than 20 ns.
Maximum DC Voltage on output pins is VCC + 0.5 V, which may overshoot to VCC + 2.0 V for periods less than 20 ns.

30 30

25 25
Supply Current

Supply Current
in mA

in mA

20 20

15 15

10 10
1 2 3 4 5 6 7 8 9 10 –75 –50 –25 0 25 50 75 100 125 150
Frequency in MHz Temperature in °C
Figure 1. Typical Supply Current Figure 2. Typical Supply Current
vs. Frequency vs. Temperature
VCC = 5.5 V, T = 25°C VCC = 5.5 V, f = 10 MHz
08007H-6 08007H-7

2-40 Am27C256
 AMD

CAPACITANCE
CDV028 PL 032 PD 028 TS 032
Parameter Parameter Test
Symbol Description Conditions Typ Max Typ Max Typ Max Typ Max Unit

CIN Input Capacitance VIN = 0 8 12 8 12 6 10 10 12 pF

COUT Output Capacitance VOUT = 0 8 12 8 12 8 10 12 14 pF

Notes:
1. This parameter is only sampled and not 100% tested.
2. TA = +25°C, f = 1 MHz.

SWITCHING CHARACTERISTICS over operating range unless otherwise specified

(Notes 1, 3 and 4)
Parameter Am27C256
Symbols
Parameter Test
JEDEC Standard Description Conditions -55 -70 -90 -120 -150 -200 -255 Unit
tAVQV tACC Address to CE = OE = Min – – – – – – –
Output Delay VIL Max 55 70 90 120 150 200 250 ns
tELQV tCE Chip Enable to OE = VIL Min – – – – – – –
Output Delay Max 55 70 90 120 150 200 250 ns
tGLQV tOE Output Enable to CE = VIL Min – – – – – – –
Output Delay Max 35 40 40 50 50 50 50 ns
tEHQZ, tDF Chip Enable HIGH or Min – – – – – – –
tGHQZ (Note 2) Output Enable HIGH, Max 25 25 25 30 30 30 30 ns
whichever comes
first, to Output Float
tAXQX tOH Output Hold from Min 0 0 0 0 0 0 0
Addresses, CE, Max – – – – – – – ns
or OE, whichever
occurred first
Notes:
1. VCC must be applied simultaneously or before VPP, and removed simultaneously or after VPP.
2. This parameter is only sampled and not 100% tested.
3. Caution: The Am27C256 must not be removed from (or inserted into) a socket or board when VPP or VCC is applied.
4. For the -55 and -70:
Output Load: 1 TTL gate and CL = 30 pF
Input Rise and Fall Times: 20 ns
Input Pulse Levels: 0 V to 3 V
Timing Measurement Reference Level: 1.5 V for inputs and outputs
For all other versions:
Output Load: 1 TTL gate and CL = 100 pF
Input Rise and Fall Times: 20 ns
Input Pulse Levels: 0.45 V to 2.4 V
Timing Measurement Reference Level: 0.8 V and 2 V inputs and outputs

Am27C256 2-41
 AMD

SWITCHING TEST CIRCUIT

2.7 kΩ
Device
Under +5.0 V
Test

CL Diodes = IN3064
6.2 kΩ or Equivalent

CL = 100 pF including jig capacitance (30 pF for -55, -70) 08007H-8

SWITCHING TEST WAVEFORM

2.4 V 3V
2.0 V 2.0 V
Test Points 1.5 V Test Points 1.5 V
0.8 V 0.8 V
0.45 V 0V
Input Output Input Output
08007H-9

AC Testing: Inputs are driven at 2.4 V for a logic “1” AC Testing: Inputs are driven at 3.0 V for a logic “1”
and 0.45 V for a logic “0”. Input pulse and 0 V for a logic “0”. Input pulse rise and
rise and fall times are ≤ 20 ns. fall times are ≤ 20 ns for -55 and -70.

2-42 Am27C256
 AMD

KEY TO SWITCHING TEST WAVEFORMS

WAVEFORM INPUTS OUTPUTS

Must Be Will Be
Steady Steady

May Will Be
Change Changing
from H to L from H to L

May Will Be
Change Changing
from L to H from L to H

Don’t Care, Changing

Any Change State
Permitted Unknown

Does Not Center

Apply Line is High
Impedence
“Off” State
KS000010

SWITCHING WAVEFORMS

2.4
2.0 Addresses Valid 2.0
Addresses
0.8 0.8
0.45

CE

tCE

OE
tDF
tOE (Note 2)
tACC tOH
(Note 1)
High Z High Z
Output Valid Output

Notes: 08007H-10
1. OE may be delayed up to tACC–tOE after the falling edge of the addresses without impact on tACC.
2. tDF is specified from OE or CE, whichever occurs first.

Am27C256 2-43