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Eec-703 2013

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20 views1 page

Eec-703 2013

Uploaded by

Priyanka Jain
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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EEC 703

B.Tech
(SEM VII) EXAMINATION 2011
VLSI DESIGN

Time : 2 Hours Total Marks : 50

Note: (1) Attempt all questions


(2) All questions carry equal marks:

1. Attempt any Two parts of the following: 5X2


Write short notes on of the following
(i) VLSI design methodology (Y Chart)
(ii) MOS Scaling
(iii) CAD Tools for VLSI Design
Enlist the classification of CMOS digital logic families
2. (a) Explain the layout design process of CMOS inverter. Draw a stick diagram of CMOS NAND gate.
(b) Consider a CMOS inverter circuits with the following parameters VDD = 3.3V, VTon = 0.6V, VTop = -
0.7V, kn = 200µA/V2, kp= 80µA/V2, kR = 2.5 Calculate the noise margin of the circuits.
(c) Consider a CMOS inverter, with the following device parameters, VDD = 3.V, VTon = 0.6V,
VTop = -0.7V , µnCox = 60µA/V2, µpCox = 20µA/V2, λ= 0. Determine the (W/L) rations of the nMOS and the
pMOS transistors such that the switching threshold is Vth = 1.5V.

(b)Design the circuit described by the Boolean function Y = A .( B+C )( D+E ) using CMOS logic.
Calculate the equivalent CMOS inverter circuit for simultaneous switching of all inputs assuming that

( WL )=5 for pMOS transistor and


( WL )=2 for all nMOS transistor.
(c) Define the terns Controllability and Observability.
4. Attempt any Two parts of the following
Write short notes on of the following
(i) Dynamic CMOS logic families
(ii)
(iii) Low power CMOS VLSI designs Techniques
5. (a)What do you understand from BIST? Explain PRPG and ORA.
(b)Discuss the operation of single stage shift register circuits Design a SR flip-flop using CMOS circuits.
(c) Classify various fault models

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