1960, Monolithic IC 1962 Mut-funcon 24 1964 Complex function 5-20 1967 Medium scale integration (MS') 20-200 1972 Large scale integration (LS) 200-2000 1978 ‘ery large scale integration (VLSI) 2000-20,000, 1989 tra large sea integration (ULSI) ‘Above 20,000 The main target of integrated circuit design and fabrication is to achieve more functionality at higher speed using less power, less area, and low cost. In the’ early 1960s, Intel cofounder Gordon Moore had predicted that the number of devices on ‘single chip will double in every eighteen months, Over the last 50 years it has bbeen found that the semiconductor industry has really followed the prediction of Moore, and henee it has become a law which is famously known as the Moore's law, Figure 1.2 depicts how the microprocessor technology has evolved over the last 40 yearsMe erens BiCMOS—In these ICs, combination of BIT and CMOS transistors are used, MESFET—Metal semiconductor field effect transistors arc used in these ICs, HBT—These ICs use hetero-junction bipolar transistors, HEMT—High clectron mobility transistors are used in these ICs, 1.4 Design Methodology VLSI design is a Sequential process of generating the physical layout of an IC starting from the specification of that circuit. It ean be fully or semi-automated ‘using muimerous softwares called electronic design automation (EDA) of computer tided design (CAD) tools. The designers first get an idea of a new system or device for a particular application. This new idea i8 translated in the form of an integrated circuit chip using the VLSI design flow. The concept or idea is first documented in a formal language and then translat- ed into register transfer level (RTL) using hardware description languages (HDL) such as Verilog and VHDL. The RTL netlist is then complied and tested to check if the functionality expected is correctly described. Usually, an iterative process is used to describe the circuit behaviour in the RTL netlist. Once the behavioural clist is finalized, the constraints are imposed on the design. Some major c straints are less area, low power, and high speed. Taking the behavioural netlist and design constraints, different synthesis styles have come up with optimum1.5 Design Domains—Y-Chart The IC design can be described in the following three domains: © Behavioural = Structural = Physical In the Behavioural domain, a circuit is MeSeribed Tully by its behaviour without describing its physical implementation of structure. In the structural domain, a circuit is described by its components and their interconnections. The physical 6 s1Desgn domain deals with actual geometry of the citcuit and describes the shape, size, and locations of its components. The three design domains are represented pictorially by a chart called the ¥-chart (Fig. 1.4) introduced by Gajski-Kubn.«domain deals with actual geometry of the circuit and describes the sh locations of its components. The three design domains ate represented pictorially by a chart called the Ychart (Fig. 14) introduced by Gajski=Kubn. Refister Gate S807 Boolean exigesion Physical, Fig. 1.4 Goiski-Kutn Yocart41.6.4 Regularity, Modularity, and Locality The large complexity of the VLSI design is handled by the hierarchical decomposi- tion of a system into several functional blocks. While hierarchically decomposing a large system regularity must be followed. ofa regular structure. Regularity avoids of different blocks to be designed and verified and can be maintained at all levels of abstraction. is another important aspect of hierarchical decomposition. It of the functional1.15 CAD Tools for VLSI Design Computer-aided design (CAD) tools are the programs that fully or partly automate the VLSI design steps. With the integration density of devices in a chip increased from thousands to millions or even billions today, CAD tools are inevitable in the VLSI design process. Just to understand the necessity of CAD tools, let us consider a simple example of solving a set of linear equations. To find out the voltage or cur rent in a circuit with three loops, we need to derive three independent linear equa tions and solve them. However, wit the set containing more and more independent equations, the problem becomes harder and impossible for solving a set with more than 10 equations within a reasonable time. Now think of ICs containing millions of eireuit components. The only possible approach is to write a computer program to solve it. This not only reduces the time for getting the solution, but also reduces the chances of human errors and can be used as many times as required, Specific VLSI design styles require specific CAD tools. Also different CAD tools must be there for solving problems in different domains. jure 1.19 illustrates different VLSI design styles and different aspects of VLSI design. For example, a full-custom design style would require a different set ‘FCAD tools as compared to the standard cell-based design. Similarly, the FPGA. based design style requires another different set of CAD tools. Again, the different problem domains require different set of CAD tools. Typically, the VLSI designoeVist dasign . (oe) Cee) ee) a VEST design ayes Leaeee Frilesiom]) [Semaatom] [Sandariest) [Gatearay] [FPGA] [PLD] Fig. 149 Diferent VLSI design styles and different aspects of VLSI design domain ean be broadly divided into two: the implementation aid the Verification. In the implementation domain, the tools are required to design the circuit, symhesize the circuit, and draw the layout. Inthe verification domain, the tools are requited to verify the functionality ofthe circuit, checking the timing specifications, doing the power analysis, verifying the layout, and checking the design rules, et. In summary, based on the design flows, CAD tools are classified as = Implementation tools seep ancientdomain can be broadly divided into two: the implementation and the verification. In the implementation domain, the tools are required to design the circuit, symhesize the circuit, and draw the layout Inthe verification domain, the tools are required to verify the functionality of the circuit, checking the timing specifications, doing the power analysis, verifying the layout, and checking the design rules, cte In summary, based on the design flows, CAD tools are classified as: = Implementation tools + Logic and physical synthesis + Design for test + Full custom layout + Floorplanning + Place and route = Verification tools + Simulation + Timing analysis Formal verification + Power analysis, + Signal integrity + DRC and LVS Table 1.7 illustrates how the CAD tools have evolved in the last 60 years Table 17 Evolution of VISLCAD to29 MOSFET Scaling ‘The ever-increasing demand of the features of the electronic appliances has forced to put more and more transistors in a small IC chip. The number of devices dou- bles almost in eighteen months, as per the famious Moore's law. The iteration of more devices into a small area has essentially pushed the VLSI process technology to be advanced from micron to submicron, submieron to deep submicron (DSM), and to nanometre regime, As the technology advances, the area occupied by the transistors is just halved per technology node. According to the ITRS roadmap, the shrink factor is almost 0.7 per technology node. When a square is halved, its dimensions are shrunk by If 72 = 0.707. Hence, the reduction of MOSFET dimensions is known as MOSFET sealing. MOSFET dimensions are scaled by a scale factor (S), which is approximately 1.4 per technology node. Table 2.2 shows different technology nodes and scaling with the year. There are two main scaling techniques defined as follows: ‘onstant field scaling or full scaling, = Constant voltage scaling Table 22 Different VLSI technology nodes Technology node Shrink factor Sale factor Cy‘characteristics. Depending on the target application, suitable scaling techniques are used. Typically, combinations of both scaling are used to migrate from one technology to a newer technology node. 29.1 Constant Field Scaling (Full Scaling) In the constant field scaling, the dimensions Of the MOSFET and the terminal voltages are scaled with the same scale factor so that the electric field remains constant, Table 2.3 summarizes the sealing parameters. Scaling of the above-mentioned parameters has an effect on the MOSFET characteristies as illustrated in Table 2.4 Its evident that full scaling significantly effects the power dissipation, It re- iiGes the power dissipation by a factor S* at the cost of reduction in drain current Table 23 Ful scaling parameters Parameter Before scaling ‘Alter scaling Channel length us Channel with wis Gate oxide thickness tad Junction depth aS Power supply voltaePower dissipation Power density Picea’ PiArea 29.2 Constant Voltage Scaling In the constant voltage scaling, the dimensions of the MOSFET are scaled but the terminal voltages are kept constant. This type of scaling increases the electric field. Table 2.5 summarizes the scaling parameters. This type of scaling is used where the signal levels of the IC cannot be scaled to match the signal requirements by other chips in the printed eircuit board where itis used. Otherwise, it will require level shifting buffers at each /O pads of the chip and hence, complicate the design. Scaling of the above-mentioned param- eters has effect on the MOSFET characteristics as illustrated in Table 2.6. CyDram current Power dissipation Power density Picea’ = S° x Pidrea In the constant voltage scaling, 8 Gai is increased by @ factor Of S Which increases the device speed. However, it has significant effect on the power dissipa- tion. It increases the power dissipation by a factor S and power density by 5°. This large power density could exaggerate the reliability issues 2.9.3 Advantages and Disadvantages of MOSFET Scaling Scaling of MOSFET has many advantages and disadvantages. Following are the advantages of scalin; = More transistors can be integrated per chip; means more capability = Improvement in speed © Due to decrease in channel length L, and hence due to decrease in transit times = Increase in current © Hence improved parasitic capacitance charging time = Improved ‘throughput’ of the chip Following are the disadvantages: Cee C 2.9.3 Advantages and Disadvantages of MOSFET Scaling ing of MOSFET has many advantages and disadvantages. Following are the advantages of scaling: = More transistors can be integrated per chip; means more capability "= Improvement in speed «© Due to decrease in channel length Land hence due to decrease in transit times = Increase in current «© Hence improved parasitic capacitance charging time "= Improved ‘throughput’ ofthe chip Following are the disadvantages: = Short channel effects = Complex process technology = Parasitic effects dominate over transistor effects The MOSFET scaling is ultimately limited to the following reasons: © Lithography = Quantum effects = Oxide tunnellingee C 44.4 Stick Diagram A stick diagram isa simple way of representing the layout by using thick lines with their interconnections. A stick diagram is useful in estimating the area and plan- ning the layout before the layout is generated within a shorter cycle time. A stick joon of a layout. Lines using different colours are used to draw different components of the layout. Figure 4.8 illustrates the colours used v Yo po k * tt ix paitt dX contact Colour palate use!Bia i) Layee: CHS aver es PRES All he drawings that are shown in Figs 44-87 ae nt dawn to any sale or as they ae jst illustrations, But the layout rst bed tsing proper scale and with given 444 Stick Diagram ving any design diagram canbe calledC for drawing a stick diagram, and the stick diagrams for the CMOS inverter and two- input NAND gate. The active contact is represented by a cross () drawn in black, Example 4.1 Draw a stick diagram for a CMOS circuit implementing three- input NOR function. Solution The three-input NOR function is given by F = A+B+C. Its stick dia- gram can be implemented as shown in Fig. 4.9. Yon Yow metal = Adi poly Boa ditt cd paitt contact A «| BHL, Colour patate used: a @ o ©. Three-input NOR gate: (a) CMOS logic; (b) colour palate; (c) stick diagram (500 Pate 7)See 44.2. Design Rules of rules are known as design rules. Typical design rules are ‘drawn its width must not be smaller than the minimum width sp ‘when two metal lines are drawn, their spacing should not be lesser than the mini mum spacing specified = Micron rule When the design rules are expressed in absolute values in micron unit, e processing instru ments, For example, if we want to drill ahole on a surface, the diameter ofthe hole is limited to the diameter of the drill bit. Again, while drilling two holes si side, the ‘ain values; otherwise, the gap material will collapse, Similarly, the photolithography process has inherent limitations on the geometry that is patterned on the silicon surface. These limitations are framed as a rule which are known as design rules. Co Pico Tn cl es oe ee noe ne Sco yeTable 4.1. Comparison between A-ule and micron rule ule Scalable design rules Based on a unit A where Aste size of amin mum feature Generic fr al process technology nodes Spectying A partiulrizes the scalable rules For each new process technology Nis reduced, keeping the rules same Parasites are generaly not specie in A nits Layouts are portable—technology migration is easy Key disadvantage is everthing does not scale with he same factor ‘These rules are generally conservative asthe dlimensions are alvays rounded up o nearest integer thats multiples of k Miron ule Absolute design cules Based on absoulecstances (e.9, 0.5 um) “Tuned toa specific process technology node Complex rues, especialy for deep submi- con technology For each new process technology, rules must be generated fresh ‘A geometies are expressed using these ules Layout are not portable—technology migra- tions ict ‘Scaling issue does no arse ‘These ules are most accurate as al the dimensions are specified in absolute value SPCC amiguesyout de in Fig. 44 2 Gaus LEOESCSCsLamIgresve ne % vocPe 445 Design Rule Checking The IC layout isthe collection of patterns drawn on diferent layers, HSS Hence, there i 4 Table 3 Meron es Dinenson Meron1 simon a 101 pase aciveto ret p 103 pase act overapofrpach 104 pradvetonacbe Then the violated pol nun again to verify the layout PePe 6.140). 68 Classification of CMOS Digital Logic Circuit Inthe combinational logic eicuit the output is determined by the present lo inputs, However, inthe sequential logic circuit, the outpt is determined present inputs and past outputs. The examples of combinational logic ciruitsae Inverter, NAND gate, NOR gate, multiplexer, demultiplexer, : half-adder, fulladder, ec. The examples of sequential lathes tes Tere are otier CMOS sive belo = CMOS transaission log = Complementary pas-trnsistor log Dynamic CMOS logic ® Domino CMOS log © NORA CMOS lose 2 Zipper CMOS log PCPs amie69 Combinational Logic Circuit (also explained before). 69.4 Design of Complex Logie Circuit Letus now design a complex Boolean Function219 8 2B cthwhsonh 68 Classification of CMOS fallow In the combinational logic circuit the output is determined by the present loi inpus. However, inthe sequential logic circuit, the output is determined by the present inputs and past outputs. The examples of combinational loge eeuis a NOR gue, multiplexer, demult Je, encoder, ‘ct. The examples of sequential opie eeu are Bip-sops, There are other CMOS design sys as given below asst Dynamic CMOS logic Domina CMOS lo NORA CMOS pper CMOS Io 69 Combinational Logic Circuit HE 2 sue LPOESCSC+amigvesve ae eeee Ther are other CMOS = CMOS transmission og Complementary pass-transstorlogie Dynaaie CMOS logic Domino CMOS logic NORA CMOS log Zipper CMOS log 69 Combinational Logic Circuit also explained before), 6.9.4 Design of Complex Logie Cirult Letus now design a complex Boolean function ¥ =AB¥C}3 DE Pe Ah. LL erra) Scan) Cee ee er The generalized sivcture of sequential eteitis shown in of combinational logie block anda memory circuit in the feedback path SPCCuamigrve a neyee Pe PCPs amie ° a aFg 6a) Tut af to-rout AND gate) As seen fom the tra table, the funtion (Fe evaluate for transistors connected in pall as shown in Fig 6.54(0) 4=0, F=0; (i) when A= 1, = B. This logic ean be realized using two nMOS. ‘nMOS is ON, so the output i ) When A = 0, the lower nMOS is ON, 50 the output is = 0), ies known as pass tans (PTL), This logic uses leser umber of tansistrs tional CMOS loge Th is thatthe logic high ouputis degraded as nMOS cannot pas loge high perf 6.181 Degradation of Logi High Output Level The nMOS transistor cannot pass the logic high lvel perfect. To analyse this degrada consider aPTL circuit as shown in Fig sun an‘The drain current-drain voltage curves shown above reach their peak value for Vg Vos ~ Vay: Beyond this maximum, each curve exhibits a negative differential conductance, whichis not observed in actual MOSFET current-voltage measurements (section shown by the dashed lines). We must remember now thatthe drain current 2) has been derived under the following voltage assumptions, Ves? Vea Voo= Vas —Vos 2 Veo which guarantee thatthe entre channel region between the source and the drain is inverted, This condition corresponds tothe linear operating mode for the MOSFET, ‘hich was examined qualitatively in Section 34. Hence, the current equation (3.32) is MOS Transistor valid onl forthe linear mode operation. Beyond the linear region bound, i.e. for Ving values larger than Vs Vir the MOS transistor wil be assumed to be in saturation. A Afferent curent-voltage expression will be necessary for the MOSFET operating in th region.