ELECTRONICS AND SUBJECT: CEC370

COMMUNICATION LOW POWER IC DESIGN

ENGINEERING

YEAR SEMESTER UNIT NO. : 02

III V LOW-POWER DESIGN
APPROACHES

Downloadable at
Ms.G VIJAYAKUMARI,AP/ ECE
tiny.cc/npsb-elearning
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E-LEARNING CEC370 LOW POWER IC DESIGN

OUTLINE

Low-Power Design through Voltage Scaling: VTCMOS circuits, MTCMOS

circuits, Architectural Level Approach –Pipelining and Parallel Processing
Approaches. Switched Capacitance Minimization Approaches: System Level
Measures, Circuit Level Measures, Mask level Measures.

UNIT 2 LOW-POWER DESIGN APPROACHES Ms. G VIJAYAKUMARI, AP/ ECE 2

 NEW PRINCE DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
E-LEARNING CEC370 LOW POWER IC DESIGN

Low-Power Design through Voltage Scaling

• The switching power dissipation in CMOS digital integrated circuits is a strong

function of the power supply voltage.
• Reduction of VDD emerges as a very effective means of limiting the power
consumption.
• Given a certain technology, the circuit designer may utilize on- chip DC- DC
converters and/or separate power pins to achieve this goal.
• The savings in power dissipation comes at a significant cost in terms of increased
circuit delay.
• Reduction of the power supply voltage with a corresponding scaling of threshold
voltages, in order to compensate for the speed degradation.

UNIT 2 LOW-POWER DESIGN APPROACHES Ms. G VIJAYAKUMARI, AP/ ECE 3

 NEW PRINCE DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
E-LEARNING CEC370 LOW POWER IC DESIGN

Low-Power Design through Voltage Scaling

UNIT 2 LOW-POWER DESIGN APPROACHES Ms. G VIJAYAKUMARI, AP/ ECE 4

 NEW PRINCE DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
E-LEARNING CEC370 LOW POWER IC DESIGN

Variable-Threshold CMOS (VTCMOS) Circuits

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 NEW PRINCE DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
E-LEARNING CEC370 LOW POWER IC DESIGN

Variable-Threshold CMOS (VTCMOS) Circuits

• The threshold voltage VT of an MOS transistor is a function of its source-

to-substrate voltage VSB.
• In conventional CMOS logic circuits, the substrate terminals of all nMOS
transistors are connected to ground potential, while the substrate terminals
of all pMOS transistors are onnected to VDD.
• The VTCMOS technique can also be used to automatically control the
threshold voltages of the transistors in order to reduce leakage currents, and
to compensate for process-related fluctuations of the threshold voltages.
• This approach is also called the Self-Adjusting Threshold-Voltage Scheme
(SATS).

UNIT 2 LOW-POWER DESIGN APPROACHES Ms. G VIJAYAKUMARI, AP/ ECE 6

 NEW PRINCE DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
E-LEARNING CEC370 LOW POWER IC DESIGN

Variable-Threshold CMOS (VTCMOS) Circuits

Block diagram of a
typical low-power
chip.

• An on-chip DC-DC voltage converter generates the low internal supply voltage VDDL,
which is used by the internal circuitry.
• Two signal swing converters (level converters) are used to reduce the voltage swing of
the incoming input signals, and to increase the voltage swing of the outgoing output
signals, respectively.
• The internal low-voltage circuitry can be designed using VTCMOS techniques, where
the threshold voltage control unit adjust the substrate bias in order to suppress leakage
currents.
UNIT 2 LOW-POWER DESIGN APPROACHES Ms. G VIJAYAKUMARI, AP/ ECE 7
 NEW PRINCE DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
E-LEARNING CEC370 LOW POWER IC DESIGN

Multiple-Threshold CMOS (MTCMOS) Circuits

In the active mode, the high-VT transistors are
turned on and the logic gates consisting of low-
VT transistors can operate with low switching
power dissipation and small propagation delay.
When the circuit is driven into stand-by mode,
on the other hand, the high-VT transistors are
turned off and the conduction paths for any sub-
threshold leakage currents that may originate
from the internal low-VT circuitry are effectively
cut off.
The critical signal propagation path from the
input to the output consists exclusively of low-
VT transistors, while a cross-coupled inverter pair
consisting of high- VT transistors is used for
preserving the data in the stand-by mode.

UNIT 2 LOW-POWER DESIGN APPROACHES Ms. G VIJAYAKUMARI, AP/ ECE 8

 NEW PRINCE DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
E-LEARNING CEC370 LOW POWER IC DESIGN

Multiple-Threshold CMOS (MTCMOS) Circuits

• The MTCMOS technique does not require a
twin-well or triple-well CMOS process; the
only significant process-related overhead of
MTCMOS circuits is the fabrication of MOS
transistors with different threshold voltages on
the same chip.
• One of the disadvantages of the MTCMOS
circuit technique is the presence of series-
connected stand-by transistors, which increase
the overall circuit area and also add extra Low-power/low-voltage D-latch circuit
parasitic capacitance. designed with MTCMOS technique.
• While the VTCMOS and MTCMOS circuit
techniques can be very effective in designing
low-power/low-voltage logic gates, they may
not be used as a universal solution to low-
power CMOS logic design.

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 NEW PRINCE DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
E-LEARNING CEC370 LOW POWER IC DESIGN

Pipelining Approach

Single-stage implementation of a logic function and its simplified timing diagram

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 NEW PRINCE DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
E-LEARNING CEC370 LOW POWER IC DESIGN

Pipelining Approach

N-stage pipeline structure realizing the same logic function as shown in Fig.
The maximum pipeline stage delay is equal to the clock period, and the
latency is N clock cycles.

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 NEW PRINCE DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
E-LEARNING CEC370 LOW POWER IC DESIGN

Pipelining Approach

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 NEW PRINCE DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
E-LEARNING CEC370 LOW POWER IC DESIGN

Parallel Processing Approach (Hardware Replication)

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 NEW PRINCE DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
E-LEARNING CEC370 LOW POWER IC DESIGN

Parallel Processing Approach (Hardware Replication)

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 NEW PRINCE DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
E-LEARNING CEC370 LOW POWER IC DESIGN

Reduction of Switched Capacitance

System-Level Measures
At the system level, one approach to reduce the switched capacitance is to limit
the use of shared resources.
A simple example is the use of a global bus structure for data transmission
between a large number of operational modules .
If a single shared bus is connected to all modules as in fig. this structure results
in a large bus capacitance due to
(i) the large number of drivers and receivers sharing the same transmission
medium, and
(ii) (ii) the parasitic capacitance of the long bus line.

Using a single global bus structure for connecting a large

number of modules on chip results in large bus capacitance
and large dynamic power dissipation

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 NEW PRINCE DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
E-LEARNING CEC370 LOW POWER IC DESIGN

SYSTEM LEVEL MEASURE

Using smaller local buses reduces the amount of switched capacitance, at

the expense of additional chip area.

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E-LEARNING CEC370 LOW POWER IC DESIGN

Circuit-Level Measures
• The type of logic style used to implement a digital circuit also affects the
output load capacitance of the circuit.
• The capacitance is a function of the number of transistors that are required
to implement a given function.
• For example, one approach to reduce the load capacitance is to use transfer
gates (pass-transistor logic) instead of conventional CMOS logic gates to
implement logic functions.
• Pass-gate logic design is attractive since fewer transistors are required for
certain functions such as XOR and XNOR. Therefore, this design style has
emerged as a promising alternative to conventional CMOS, for low power
design.

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 NEW PRINCE DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
E-LEARNING CEC370 LOW POWER IC DESIGN

Mask-Level Measures

• The amount of parasitic capacitance that is switched (i.e. charged up or

charged down) during operation can be also reduced at the physical design
level, or mask level.
• The parasitic gate and diffusion capacitances of MOS transistors in the circuit
typically constitute a significant amount of the total capacitance in a
combinational logic circuit.
• Hence, a simple mask-level measure to reduce power dissipation is keeping
the transistors (especially the drain and source regions) at minimum
dimensions whenever possible and feasible, thereby minimizing the parasitic
capacitances.

UNIT 2 LOW-POWER DESIGN APPROACHES Ms. G VIJAYAKUMARI, AP/ ECE 18