DEGITAL DESIGN AND COMPUTER ORGANIZATIONNotes-BCS302 (Module-4)

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DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING

LECTURE NOTES – MODULE 4

SUBJECT : DEGITAL DESIGN AND COMPUTER ORGANIZATION

SUBJECT CODE: BCS302
SEMESTER : III

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MODULE:4
Input/output Organization: Accessing I/O Devices, Interrupts – Interrupt Hardware, Enabling and
Disabling Interrupts, Handling Multiple Devices, Direct Memory Access: Bus Arbitration, Speed, size
and Cost of memory systems. Cache Memories – Mapping Functions.
Text book 2: 4.1, 4.2.1, 4.2.2, 4.2.3, 4.4, 5.4, 5.5.1

Q Draw the arrangement of a single bus structure and brief about memory mapped I/O.
ACCESSING I/O-DEVICES
The components of a computer system communicate with each other through an interconnection
network, as shown in Figure 3.1. The interconnection network consists of circuits needed to
transfer information between the processor, the memory unit, and a number of I/O devices.
• A single bus-structure can be used for connecting I/O-devices to a computer (Figure 4.1).
• Each I/O device is assigned a unique set of address.
• Bus consists of 3 sets of lines to carry address, data & control signals.
• When processor places an address on address-lines, the intended-device responds to the
command.
• The processor requests either a read or write-operation.
• The requested-data are transferred over the data-lines.

Figure 4.1 Single bus structure

• There are 2 ways to deal with I/O-devices: 1) Memory-mapped I/O & 2) I/O-mapped I/O.
(Isolated I/O)

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1) Memory-Mapped I/O
Memory and I/O-devices share a common address-space.
Any data-transfer instruction (like Move, Load) can be used to exchange information. For
example,
Move DATAIN, R0; This instruction sends the contents of location DATAIN to register R0.
Here, DATAIN address of the input-buffer of the keyboard.
2) I/O-Mapped I/O (Isolated I/O)
Memory and I/0 address-spaces are different.
A special instruction named IN and OUT are used for data-transfer. Advantage of separate I/O
space: I/O-devices deal with fewer address-lines.
IN 19H, R0 ; This instruction stores the data in R0 from the I/O port 19H
Here, 19H refers to I/O Port.
Q-Comparison - Memory-mapped vs I/O-mapped

Memory-mapped IO I/O-mapped IO
Same address bus to address memory and I/O Different address spaces for memory
devices and I/O devices
Access to the I/O devices using regular Uses a special class of CPU instructions
instructions to access I/O devices
Most widely used I/O method x86 Intel microprocessors - IN and OUT
instructions

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I/O Interface for an Input
Device
An I/O device is connected to the interconnection network by using a circuit, called the
device interface, which provides the means for data transfer and for the exchange of status
and control information needed to facilitate the data transfers and govern the operation of the
device. The interface includes some registers that can be accessed by the processor. One
register may serve as a buffer for data transfers, another may hold information about the
current status of the device, and yet another may store the information that controls the
operational behavior of the device.

1) Address Decoder: enables the device to recognize its address when this address appears
on the address-lines (Figure 7.2).
2) Status Register: contains information relevant to operation of I/O-device.
3) Data Register: holds data being transferred to or from processor. There are 2
types:
i) DATAIN - Input-buffer associated with keyboard.
ii) DATAOUT -Output data buffer of a display/printer.
MECHANISMS USED FOR INTERFACING I/O-
DEVICES
1) Program Controlled I/O
Consider a task that reads characters typed on a keyboard, stores these data in the memory, and
displays the same characters on a display screen. A simple way of implementing this task is to
write a program that performs all functions needed to realize the desired action. This method is
known as program-controlled I/O.

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• Processor repeatedly checks status-flag to achieve required synchronization b/w
processor & I/O device.
Main drawback:
The processor wastes time in checking status of device before actual data-transfer takes place.
2) Interrupt I/O
• I/O-device initiates the action instead of the processor.
• I/O-device sends an INTR signal over bus whenever it is ready for a data-transfer operation.
• Like this, required synchronization is done between processor & I/O device.
3) Direct Memory Access (DMA)
• Device-interface transfer data directly to/from the memory w/o continuous involvement by the
processor.
• DMA is a technique used for high speed I/O-device.
Q Define and explain briefly the following with example i) interrupt
INTERRUPTS
• There are many situations where other tasks can be performed while waiting for an I/O
device to become ready.
• A hardware signal called an Interrupt will alert the processor when an I/O device becomes
ready.
• Interrupt-signal is sent on the interrupt-request line.
• The processor can be performing its own task without the need to continuously check the
I/O-device.
• The routine executed in response to an interrupt-request is called ISR.
• The processor must inform the device that its request has been recognized by sending INTA
signal.
(INTR: Interrupt Request, INTA :Interrupt Acknowledge, ISR :Interrupt Service Routine)
• For example, consider COMPUTE and PRINT routines (Figure 3.6).

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• The processor first completes the execution of instruction i.

• Then, processor loads the PC with the address of the first instruction of the ISR.
• After the execution of ISR, the processor has to come back to instruction i+1.

• Therefore, when an interrupt occurs, the current content of PC is put in temporary storage
location.
• A return at the end of ISR reloads the PC from that temporary storage location.
• This causes the execution to resume at instruction i+1.
• When processor is handling interrupts, it must inform device that its request has been
recognized.
• This may be accomplished by INTA signal.
• The task of saving and restoring the information can be done automatically by the processor.
• The processor saves only the contents of PC & Status register.
• Saving registers also increases the Interrupt Latency.
• Interrupt Latency is a delay between
→ time an interrupt-request is received and
→ start of the execution of the ISR.
• Generally, the long interrupt latency in unacceptable.
Difference between Subroutine & ISR

INTERRUPT HARDWARE (Single interrupt-request (IR) line)

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• Most computers have several I/O devices that can request an interrupt.
• A single interrupt-request (IR) line may be used to serve n devices (Figure 4.6).
• All devices are connected to IR line via switches to ground.
• To request an interrupt, a device closes its associated switch.
• Thus, if all IR signals are inactive, the voltage on the IR line will be equal to Vdd.
• When a device requests an interrupt, the voltage on the line drops to 0.
• This causes the INTR received by the processor to go to 1.
• The value of INTR is the logical OR of the requests from individual devices.
INTR=INTR1+ INTR2+ .......... +INTRn
• A special gates known as open-collector or open-drain are used to drive the INTR line.
• The Output of the open collector control is equal to a switch to the ground that is
→ open when gates input is in ”0‟ state and
→ closed when the gates input is in “1‟ state.

• Resistor R is called a Pull-up Resistor because

it pulls the line voltage up to the high-voltage state when the switches are open.

Q Discuss the different schemes available to disable and enable the interrupts
Q Discuss the different schemes available to disable and enable the interrupts(8M)
ENABLING & DISABLING INTERRUPTS
• The facilities provided in a computer must give the programmer complete control over
the events that take place during program execution.
• The arrival of an interrupt request from an external device causes the processor to
suspend the execution of one program and start the execution of another. Because

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interrupts can arrive at any time, they may alter the sequence of events from that
envisaged by the programmer.
• Hence, the interruption of program execution must be carefully controlled. A
fundamental facility found in all computers is the ability to enable and disable such
interruptions as desired.
• All computers fundamentally should be able to enable and disable interruptions as desired.
• The problem of infinite loop occurs due to successive interruptions of active INTR signals.
• There are 3 mechanisms to solve problem of infinite loop:
• At the device end: To avoid interruption by the different device during the execution of
an interrupt service routine:
o First instruction of an interrupt service routine can be Interrupt-disable.
o Last instruction of an interrupt service routine can be Interrupt-enable
• At the processor end: The processor automatically disables interrupts before starting the
execution of the interrupt-service routine.
o After saving value of PC and processor status register (PS) on the stack, the processor
executes interrupt-disable instruction by clearing the interrupt-enable bit to 0.
o When a return-from-interrupt instruction is executed, the contents of PS are restored from
stack, setting the interrupt-enable bit to 1.
• Edge Triggered Interrupts: The processor has a special interrupt-request line for which the
Interrupt-handling circuit responds only to the leading edge of the signal. Such a line is said
to be edge-triggered.
o Processor receives only one request regardless of how long the line is activated.
o No need to explicitly disable interrupt requests.
Sequence of events involved in handling an interrupt-request:
1) The device raises an interrupt-request.
2) The processor interrupts the program currently being executed.
3) Interrupts are disabled by changing the control bits in the processor status register (PS).
4) The device is informed that its request has been recognized. In response, the device
deactivates the interrupt-request signal.
5) The action requested by the interrupt is performed by the interrupt-service routine.
6) Interrupts are enabled and execution of the interrupted program is resumed.
HANDLING MULTIPLE DEVICES
While handling multiple devices, the issues concerned are:
1) How can the processor recognize the device requesting an interrupt?
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2) How can the processor obtain the starting address of the appropriate ISR?
3) Should a device be allowed to interrupt the processor while another interrupt is being serviced?
4) How should 2 or more simultaneous interrupt-requests be handled?
1) POLLING
• Interrupt service routine can poll the I/O devices connected to the bus.
• When a device raises an interrupt-request, it sets IRQ bit to 1 in its status-register
• KIRQ and DIRQ are the interrupt-request bits for keyboard & display.
• Simplest way to identify interrupting device is to have ISR poll all I/O devices connected to bus.
•The first device encountered with its IRQ bit set is the device that should be serviced. After servicing
this device, next requests may be serviced.
Main advantage: Simple & easy to implement.
Main disadvantage: More time spent polling IRQ bits of all devices (that may not be requesting
any service).
DIRQ Interrupt-request for display.
KIRQ Interrupt-request for keyboard.
KEN keyboard enable.
DEN Display Enable.
SIN, SOUT status flags.
The polling scheme is easy to implement. Its main disadvantage is the time spent interrogating the
IRQ bits of all the devices that may not be requesting any service. An alternative approach
is to use vectored interrupts, which we describe
next.

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Q Define and explain briefly the following

i)vectored interrupt
2) VECTORED INTERRUPTS
• A device requesting an interrupt identifies itself by sending a special-code to processor over bus.
• Then, the processor starts executing the ISR.
• The special-code indicates starting-address of ISR.
• The special-code length ranges from 4 to 8 bits.
• The location pointed to by the interrupting-device is used to store the starting address to ISR.
• The starting address to ISR is called the interrupt vector.
• Processor
→ loads interrupt-vector into PC &
→ executes appropriate ISR.
• When processor is ready to receive interrupt-vector code, it activates INTA line.
• Then, I/O-device responds by sending its interrupt-vector code & turning off the INTR
signal.
• The interrupt vector also includes a new value for the Processor Status Register.
CONTROLLING DEVICE REQUESTS
• Following condition-codes are used:
KEN Keyboard Interrupt Enable.
DEN Display Interrupt Enable.
KIRQ/DIRQ Keyboard/Display unit requesting an interrupt.

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Q. Define and explain briefly the followingi) interrupt nesting
3) INTERRUPT NESTING
• A multiple-priority scheme is implemented by using separate INTR & INTA lines for
each device
• I/O devices are organized in a priority structure:
o An interrupt request from a high-priority device is accepted while the processor is executing the
interrupt service routine of a low priority device.
• A priority level is assigned to a processor that can be changed under program control.
• Priority level of a processor is the priority of the program that is currently being executed.
o When the processor starts executing the interrupt service routine of a device, its priority is
raised to that of the device.
o If the device sending an interrupt request has a higher priority than the processor, the
processor accepts the interrupt request.
o Thus, interrupts from devices at the same level of priority or lower are disabled.
• Processor’s priority is encoded in a few bits of the processor status register.
O Priority can be changed by instructions that write into the processor status register.
O Usually, these are privileged instructions, or instructions that can be executed only in the
supervisor mode.
O Privileged instructions cannot be executed in the user mode.
O Prevents a user program from accidentally or intentionally changing the priority of
the processor.
• If there is an attempt to execute a privileged instruction in the user mode, it causes a special
type of interrupt called as privilege exception.
• Prevents a user program from accidentally or intentionally changing the priority of the processor

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• Each device has a separate interrupt-request and interrupt-acknowledge line.
• Each interrupt-request line is assigned a different priority level.
• Interrupt requests received over these lines are sent to a priority arbitration circuit in the
processor.
• If the interrupt request has a higher priority level than the priority of the processor, then the
request is accepted.
This example suggests that I/O devices should be organized in a priority structure. An interrupt request
from a high-priority device should be accepted while the processor isservicing another request from a
lower-priority device. A multiple-level priority organization means that during execution of an
interrupt-service routine, interrupt requests will be accepted from some devices but not from others,
depending upon the device’s priority. To implement this scheme, we can assign a priority level to the
processor that can be changed under program control.
The priority level of the processor is the priority of the program that is currently being executed. The
processor accepts interrupts only from devices that have priorities higher than its own. The processor’s
priority is usually encoded in a few bits of the processor status word.It can be changed by program
instructions that write into the PS.
These are privileged instructions, which can be executed only while the processor is running in the
supervisor mode. The processor is in the supervisor mode only when executingoperating system
routines. It switches to the user mode before beginning to execute application programs. Thus, a user
program cannot accidentally, or intentionally, change the priority of the processor and disrupt the
system’s operation. An attempt to execute a privileged instruction while in the user mode leads to a
special type of interrupt called a privileged instruction.
A multiple-priority scheme can be implemented easily by using separate interrupt-request and interrupt-
acknowledge lines for each device, as shown in figure. Each of the interrupt-request lines is assigned a
different priority level. Interrupt requests received over these lines are sent to a priority arbitration
circuit in the processor. A request is accepted only if it has a higher priority level than that currently
assigned to the processor.

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Q.Explain in with the help of a diagram the working of daisy chain with multiple priority levels
and multiple devices in each level .
4) SIMULTANEOUS REQUESTS
• The processor must have some mechanisms to decide which request to service when
simultaneous requests arrive.
• INTR line is common to all devices (Figure 4.8a).
• INTA line is connected in a daisy-chain fashion.
• INTA signal propagates serially through devices.
• When several devices raise an interrupt-request, INTR line is activated.
• Processor responds by setting INTA line to 1. This signal is received by device 1.
• Device-1 passes signal on to device 2 only if it does not require any service.
• If device-1 has a pending-request for interrupt, the device-1
→ blocks INTA signal &
→ proceeds to put its identifying-code on data-lines.
• Device that is electrically closest to processor has highest priority.

• Advantage: It requires fewer wires than the individual connections.

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Arrangement of Priority Groups
• Here, the devices are organized in groups & each group is connected at a different priority
level.
• Within a group, devices are connected in a daisy chain. (Figure 4.8b).

• Devices are connected to form a daisy chain.

• Devices share the interrupt-request line, and interrupt-acknowledge line is connected to
form a daisy chain.
• When devices raise an interrupt request, the interrupt-request line is activated.
• The processor in response activates interrupt-acknowledge.
• Received by device 1, if device 1 does not need service, it passes the signal to device 2.
• Device that is electrically closest to the processor has the highest priority.
When I/O devices were organized into a priority structure, each device had its own interrupt-
request and interrupt-acknowledge line.
When I/O devices were organized in a daisy chain fashion, the devices shared and interrupt-
request line, and the interrupt-acknowledge propagated through the devices.
• A combination of priority structure and daisy chain scheme can also use.
• Devices are organized into groups.
• Each group is assigned a different priority level.
All the devices within a single group share an interrupt-request line, and are connected to form a
daisy chain

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Q Define and explain briefly the followingi)an exception and give two examples
Q: Write a note on DMA
DIRECT MEMORY ACCESS (DMA)
• The transfer of a block of data directly b/w an external device & main-memory w/o continuous
involvement by processor is called DMA.
• DMA controller
→ is a control circuit that performs DMA transfers (Figure )
→ is a part of the I/O device interface.
→ performs the functions that would normally be carried out by processor.
• While a DMA transfer is taking place, the processor can be used to execute another
program.

DMA interface has three registers

1) First register is used for storing starting-address.
2) Second register is used for storing word-count.

3) Third register contains status- & control-flags.

The R/W bit determines direction of transfer.

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If R/W=1, controller performs a read-operation (i.e. it transfers data from memory to I/O),
Otherwise, controller performs a write-operation (i.e. it transfers data from I/O to memory).
• If Done=1, the controller
→ has completed transferring a block of data and
→ is ready to receive another command. (IE Interrupt Enable).
• If IE=1, controller raises an interrupt after it has completed transferring a block of data.
• If IRQ=1, controller requests an interrupt.
• Requests by DMA devices for using the bus are always given higher priority than processor
requests.
• There are 2 ways in which the DMA operation can be carried out:
1) Processor originates most memory-access cycles.
DMA controller is said to "steal" memory cycles from processor. Hence, this technique is
usually called Cycle Stealing.
2) DMA controller is given exclusive access to main-memory to transfer a block of data without
any interruption. This is known as Block Mode (or burst mode).

Q Define Bus arbitration. Explain two bus arbitration schemes.

BUS ARBITRATION
• The device that is allowed to initiate data-transfers on bus at any given time is called bus-
master.
• There can be only one bus-master at any given time.
• Bus Arbitration is the process by which
→ next device to become the bus-master is selected &
→ bus-mastership is transferred to that device.
• The two approaches are:
1) Centralized Arbitration: A single bus-arbiter performs the required arbitration.
2) Distributed Arbitration: All devices participate in selection of next bus-master.
• A conflict may arise if both the processor and a DMA controller or two DMA controllers try to use
the bus at the same time to access the main-memory.
• To resolve this, an arbitration procedure is implemented on the bus to coordinate the activities
of all devices requesting memory transfers.
• The bus arbiter may be the processor or a separate unit connected to the bus.

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Q Explain with a block diagram
1. CENTRALIZED ARBITRATION
• A single bus-arbiter performs the required arbitration (Figure: 4.20).
• Normally, processor is the bus-master.
• Processor may grant bus-mastership to one of the DMA controllers.
• A DMA controller indicates that it needs to become bus-master by activating BR line.
• The signal on the BR line is the logical OR of bus-requests from all devices connected to it.
• Then, processor activates BG1 signal indicating to DMA controllers to use bus when it
becomes free.
• BG1 signal is connected to all DMA controllers using a daisy-chain arrangement.
• If DMA controller-1 is requesting the bus,
Then, DMA controller-1 blocks propagation of grant-signal to other devices. Otherwise, DMA
controller-1 passes the grant downstream by asserting BG2.
• Current bus-master indicates to all devices that it is using bus by activating BBSY line.
• The bus-arbiter is used to coordinate the activities of all devices requesting memory transfers.
Arbiter ensures that only 1 request is granted at any given time according to a priority scheme.
(BR : Bus-Request, BG : Bus-Grant, BBSY : Bus Busy).

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• The timing diagram shows the sequence of events for the devices connected to the processor.
• DMA controller-2
→ requests and acquires bus-mastership and
→ later releases the bus. (Figure: 4.21).
• After DMA controller-2 releases the bus, the processor resources bus-mastership.

Q Explain with a block diagram

2. DISTRIBUTED ARBITRATION
• All device participates in the selection of next bus-master (Figure 4.22).
• Each device on bus is assigned a 4-bit identification number (ID).
• When 1 or more devices request bus, they
→ assert Start-Arbitration signal &
→ place their 4-bit ID numbers on four open-collector lines ARB0 through ARB3.
• A winner is selected as a result of interaction among signals transmitted over these lines.
• Net-outcome is that the code on 4 lines represents request that has the highest ID number.
• Advantage:
This approach offers higher reliability since operation of bus is not dependent on any single device.

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For example:
Assume 2 devices A & B have their ID 5 (0101), 6 (0110) and their code is 0111. Each device compares
the pattern on the arbitration line to its own ID starting from MSB. If the device detects a difference at
any bit position, it disables the drivers at that bit position. Driver is disabled by placing ”0” at the input
of the driver.
In e.g. “A” detects a difference in line ARB1, hence it disables the drivers on lines ARB1 & ARB0.
This causes pattern on arbitration-line to change to 0110. This means that “B” has won contention.

Q With figure analyses the memory hierarchy in terms of speed cost and size.
SPEED, SIZE COST

• The main-memory can be built with DRAM (Figure 8.14)

• Thus, SRAM‟s are used in smaller units where speed is of essence.
• The Cache-memory is of 2 types:
1) Primary/Processor Cache (Level1 or L1 cache)
It is always located on the processor-chip.
2) Secondary Cache (Level2 or L2 cache)
It is placed between the primary-cache and the rest of the memory.
• The memory is implemented using the dynamic components (SIMM, RIMM, DIMM).
• The access time for main-memory is about 10 times longer than the access time for L1
cache.

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Q Write a note on cache memory

CACHE MEMORIES
• The effectiveness of cache mechanism is based on the property of „Locality of Reference’.
Locality of Reference
• Many instructions in the localized areas of program are executed repeatedly during some time
period
• Remainder of the program is accessed relatively infrequently (Figure 8.15).
• There are 2 types:
1) Temporal
The recently executed instructions are likely to be executed again very soon.
2) Spatial
Instructions in close proximity to recently executed instruction are also likely to be executed soon.
• If active segment of program is placed in cache-memory, then total execution time can be reduced.
• Block refers to the set of contiguous address locations of some size.
• The cache-line is used to refer to the cache-block.

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• The Cache-memory stores a reasonable number of blocks at a given time.
• This number of blocks is small compared to the total number of blocks available in main-
memory.
• Correspondence b/w main-memory-block & cache-memory-block is specified by mapping-
function.
• Cache control hardware decides which block should be removed to create space for the new
block.
• The collection of rules for making this decision is called the Replacement Algorithm.
• The cache control-circuit determines whether the requested-word currently exists in the
cache.
• The write-operation is done in 2 ways: 1) Write-through protocol & 2) Write-back protocol.
Write-Through Protocol
Here the cache-location and the main-memory-locations are updated simultaneously.
Write-Back Protocol
This technique is to
→ update only the cache-location &
→ mark the cache-location with associated flag bit called Dirty/Modified Bit.
The word in memory will be updated later, when the marked-block is removed from cache.
During Read-operation
• If the requested-word currently not exists in the cache, then read-miss will occur.
• To overcome the read miss, Load–through/Early restart protocol is used.
Load–Through Protocol
The block of words that contains the requested-word is copied from the memory into cache.
After entire block is loaded into cache, the requested-word is forwarded to processor.
During Write-operation
• If the requested-word not exists in the cache, then write-miss will occur.
1) If Write Through Protocol is used, the information is written directly into main-memory.
2) If Write Back Protocol is used,
→ then block containing the addressed word is first brought into the cache &
→ then the desired word in the cache is over-written with the new information.
Cache hit
• Existence of a cache is transparent to the processor. The processor issues Read and Write
requests in the same manner.
• If the data is in the cache, it is called a Read or Write hit.

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• Read hit: The data is obtained from the cache.
• Write hit: Cache has a replica of the contents of the main memory.
Contents of the cache and the main memory may be updated simultaneously. This is the write- through
protocol. Update the contents of the cache, and mark it as updated by setting a bit known as the dirty
bit or modified bit. The contents of the main memory are updated when this block is replaced. This is
write-back or copy-back protocol.

Cache miss
• If the data is not present in the cache, then a Read miss or Write miss occurs.
• Read miss: Block of words containing this requested word is transferred from the memory. After
the block is transferred, the desired word is forwarded to the processor. The desired word may also
be forwarded to the processor as soon as it is transferred without waiting for the entire block to be
transferred. This is called load-through or early-restart.
• Write-miss: Write-through protocol is used, and then the contents of the main memory are
updated directly. If write-back protocol is used, the block containing the addressed word is first
brought into the cache. The desired word is overwritten with new information.
Cache Coherence Problem
• A bit called as “valid bit” is provided for each block.
• If the block contains valid data, then the bit is set to 1, else it is 0.
• Valid bits are set to 0, when the power is just turned on.
• When a block is loaded into the cache for the first time, the valid bit is set to1.
• Data transfers between main memory and disk occur directly bypassing the cache.
• When the data on a disk changes, the main memory block is also updated.
• However, if the data is also resident in the cache, then the valid bit is set to 0.
• What happens if the data in the disk and main memory changes and the write-back protocol is
being used?
• In this case, the data in the cache may also have changed and is indicated by the dirty bit.
• The copies of the data in the cache, and the main memory are different. This is called the cache
coherence problem.
One option is to force a write-back before the main memory is updated from the disk.

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Q With diagram ,explain three cache mapping function
MAPPING-FUNCTION
• Mapping functions determine how memory blocks are placed in the cache.
• A simple processor example:
➢ C a c h e consisting of 128 blocks of 16 words each.
➢ Total size of cache is 2048 (2K) words.
➢ Main memory is addressable by a 16-bit address.
➢ Main memory has 64K words.
➢ Main memory has 4K blocks of 16 words each.
• Here we discuss about 3 different mapping-function:
1) Direct Mapping
2) Associative Mapping
3) Set-Associative Mapping
DIRECT MAPPING
• The block-j of the main-memory maps onto block-j modulo-128 of the cache (Figure 8.16).
• When the memory-blocks 0, 128, & 256 are loaded into cache, the block is stored in cache-
block 0.
Similarly, memory-blocks 1, 129, 257 are stored in cache-block 1.
• The contention may arise when
1) When the cache is full.
2) When more than one memory-block is mapped onto a given cache-block position.
• The contention is resolved by
allowing the new blocks to overwrite the currently resident-block.
• Memory-address determines placement of block in the cache.

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• The memory-address is divided into 3 fields:

1) Low Order 4 bit field
Selects one of 16 words in a block.
2) 7 bit cache-block field
7-bits determine the cache-position in which new block must be stored.
3) 5 bit Tag field
5-bits memory-address of block is stored in 5 tag-bits associated with cache-location.
• As execution proceeds, 5-bit tag field of memory-address is compared with tag-bits associated
with cache-location. If they match, then the desired word is in that block of the cache.
Otherwise, the block containing required word must be first read from the memory.
And then the word must be loaded into the cache.
ASSOCIATIVE MAPPING
• The memory-block can be placed into any cache-block position. (Figure 8.17).
• 12 tag-bits will identify a memory-block when it is resolved in the cache.
• Tag-bits of an address received from processor are compared to the tag-bits of each block of
cache.
• This comparison is done to see if the desired block is present.
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• It gives complete freedom in choosing the cache-location.

• A new block that has to be brought into the cache has to replace an existing block if the cache
is full.
• The memory has to determine whether a given block is in the cache.
• Advantage: It is more flexible than direct mapping technique.
• Disadvantage: Its cost is high.
SET-ASSOCIATIVE MAPPING
• It is the combination of direct and associative mapping. (Figure 8.18).
• The blocks of the cache are grouped into sets.
• The mapping allows a block of the main-memory to reside in any block of the specified set.
• The cache has 2 blocks per set, so the memory-blocks 0, 64, 128…….. 4032 maps into cache
set „0‟.
• The cache can occupy either of the two block position within the set.6 bit set field Determines
which set of cache contains the desired block.6 bit tag field The tag field of the address is

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compared to the tags of the two blocks of the set. This comparison is done to check if the desired
block is present.

• The cache which contains 1 block per set is called direct mapping.
• A cache that has „k‟ blocks per set is called as “k-way set associative cache‟.
• Each block contains a control-bit called a valid-bit.
• The Valid-bit indicates that whether the block contains valid-data.
• The dirty bit indicates that whether the block has been modified during its cache residency.
Valid-bit=0 When power is initially applied to system.
Valid-bit=1 When the block is loaded from main-memory at first time.
• If the main-memory-block is updated by a source & if the block in the source is already exists
in the cache, then the valid-bit will be cleared to “0‟.
• If Processor & DMA uses the same copies of data then it is called as Cache Coherence
Problem.
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 Computer Organization and Architecture Notes- (Module-4)
• Advantages:
1) Contention problem of direct mapping is solved by having few choices for block placement.
2) The hardware cost is decreased by reducing the size of associative seT

Question bank
1. List out the difference between I/O mapped I/O and memory mapped I/O.

2. Explain with neat diagram I/O interface of an input device.

3. What is an interrupt? Explain its concepts with an example.

4. Explain interrupt hardware with neat diagram.

5. In a situation where multiple devices capable of initiating interrupts are connected to processor,
explain the implementation of interrupt priority, using individual INTER and INTA and a common INTER
line to all devices.

6.Define the terms cycle stealing and block modes.

7. What is bus arbitration? Explain the different approaches to bus arbitration.
8. Explain how interrupt requests from several IO devices can be communicated to a processor through a
single INTR line.
9. What are the different methods of DMA? Explain them in brief
10. What is an interrupt? Explain its concepts and the hardware used to realize it.
11. What is the necessity of DMA? Explain the two modes in which DMA interface operates to transfer
data?
12. With the sketches explain various methods for handling multiple interrupts requests )Daisy chain
2)vectored interrupts 3)Interrupt nesting 4) Simultaneous Requests 5)Priority interrupt 6)polling
13. Explain input/output interface circuit.
14. List out the functions of an I/O interface
15. Discuss in detail any one feature of memory design that leads to improve performance of computer.
16. Explain Bus Arbitration. Explain 2 approaches.
17 .Explain Speed, size and Cost of memory systems.
18. Explain Cache Memories – Explain 3 Mapping Functions.

19.Explian enabling and disabling interrupts

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