QPCODE: 24102024 Reg No:
SRIRAM ENGINEERING COLLEGE, PERUMALPATTU
SCHOOL OF ELECTRICAL AND ELECTRONICS ENGINEERING/ PROGRAM:EEE
EE3022 / VLSI DESIGN
III YEAR / V SEMESTER
INTERNAL ASSESSMENT TEST 2
TIME: 9.00 AM – 10.30 AM MAXIMUM MARKS: 60
PART A (10x2=20 marks)
ANSWER ALL THE QUESTIONS
1. Define a Programmable Array Logic (PAL) device.
2. List two advantages of using CPLDs over traditional discrete logic devices.
3. Explain the term 'logic density' in the context of CPLDs.
4. How does a PAL achieve programmability?
5. Describe the concept of ‘in-system programmability’ in CPLDs.
6. Define an FPGA and explain its primary function.
7. List two advantages of using FPGAs in digital design.
8. What is a look-up table (LUT) in the context of FPGA architecture?
9. What is the purpose of the interconnect network in an FPGA?
10. Name one common application of FPGAs in embedded systems.
PART B (2X13=26 marks)
11. a. Discuss the architecture of a Programmable Logic Array (PLA) and explain how it
implements logic functions. Include a diagram to support your explanation.
or
b. Describe the programming methods used for PALs and PLAs. Compare and contrast
these methods, highlighting their advantages and disadvantages.
12. a. Analyze the role of FPAA in reconfigurable computing. Discuss its architecture and
applications, comparing it with FPGA technology.
Or
b. Discuss the architecture of an FPGA in detail, including its basic components and their
functions. Illustrate your answer with a diagram.
Part C (1X14 marks)
13. Illustrate the architecture of a Complex Programmable Logic Device (CPLD) and discuss its
various functional blocks. How does this architecture benefit digital design?
Faculty Incharge SCHOOL HEAD/EEE
QPCODE: 24102024 Reg No:
SRIRAM ENGINEERING COLLEGE, PERUMALPATTU
SCHOOL OF ELECTRICAL AND ELECTRONICS ENGINEERING/ PROGRAM:EEE
EE3022 / VLSI DESIGN
III YEAR / V SEMESTER
INTERNAL ASSESSMENT TEST 2
TIME: 9.00 AM – 10.30 AM MAXIMUM MARKS: 60
PART A (10x2=20 marks)
ANSWER ALL THE QUESTIONS
1. What is the primary difference between a PAL and a PLA?
2. What are the main components of a Programmable Logic Array (PLA)?
3. What is the function of the OR array in a PLA?
4. Name one application of CPLDs in modern electronics.
5. What role do input and output pins play in the functionality of a CPLD?
6. What are the main components of an FPGA architecture?
7. Explain the concept of reconfigurability in FPGAs.
8. Describe the role of the configuration memory in an FPGA.
9. Briefly explain the term ‘FPAA’ and its relation to FPGAs.
10. What is the significance of design tools in FPGA-based application development?
PART B (2X13=26 marks)
11. a. Explain the differences in internal architecture and functionality between PALs and
CPLDs. Provide examples of applications where each might be preferred.
Or
11. b. Analyze the impact of programmable logic devices on modern digital design practices.
Discuss how these devices have transformed circuit design in terms of flexibility and
efficiency.
12. a. Compare and contrast FPGAs and traditional ASICs in terms of flexibility,
performance, and design complexity. Provide examples of applications where each
would be preferable.
Or
12. b. Describe the programming and configuration methods used in FPGAs. Discuss how
these methods impact design iterations and deployment.
Part C (1X14 marks)
13. Explain the process of FPGA-based application development, from design entry to
implementation. Highlight key tools and methodologies used in this process.
Faculty Incharge SCHOOL HEAD/EEE
QPCODE: 24102024 Reg No:
SRIRAM ENGINEERING COLLEGE, PERUMALPATTU
SCHOOL OF ELECTRICAL AND ELECTRONICS ENGINEERING/ PROGRAM:EEE
EE3022 / VLSI DESIGN
III YEAR / V SEMESTER
INTERNAL ASSESSMENT TEST 2
TIME: 9.00 AM – 10.30 AM MAXIMUM MARKS: 60
PART A (10x2=20 marks)
ANSWER ALL THE QUESTIONS
1. What is the primary difference between a PAL and a PLA?
2. What are the main components of a Programmable Logic Array (PLA)?
3. What is the function of the OR array in a PLA?
4. Name one application of CPLDs in modern electronics.
5. What role do input and output pins play in the functionality of a CPLD?
6. What are the main components of an FPGA architecture?
7. Explain the concept of reconfigurability in FPGAs.
8. Describe the role of the configuration memory in an FPGA.
9. Briefly explain the term ‘FPAA’ and its relation to FPGAs.
10. What is the significance of design tools in FPGA-based application development?
PART B (2X13=26 marks)
11. a. Explain the differences in internal architecture and functionality between PALs and
CPLDs. Provide examples of applications where each might be preferred.
Or
11. b. Analyze the impact of programmable logic devices on modern digital design practices.
Discuss how these devices have transformed circuit design in terms of flexibility and
efficiency.
12. a. Compare and contrast FPGAs and traditional ASICs in terms of flexibility,
performance, and design complexity. Provide examples of applications where each
would be preferable.
Or
12. b. Describe the programming and configuration methods used in FPGAs. Discuss how
these methods impact design iterations and deployment.
Part C (1X14 marks)
13. Explain the process of FPGA-based application development, from design entry to
implementation. Highlight key tools and methodologies used in this process.
Faculty Incharge SCHOOL HEAD/EEE
