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VLSI Lab Exp - No.1

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50 views10 pages

VLSI Lab Exp - No.1

Uploaded by

rama.panchal.0077
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Experiment:1

Introduction to Cadence & Inverter Static Characteristics

1.1 Lab conduction procedures


1.1.1 Access to accounts

User ID and Password:


User ID: <GroupName(X)(Y)>user<UserNumber(zZ)>
Password: ec<GroupName(X)(Y)><UserNumber(ZZ)>
Example: For “A1 group – user13”.
a1user13
eca113

Access to Account:
Now the Remote Desktop Viewer window will appear as shown in Figure 1-1 .
Follow the steps as given in the order.

Figure 1-1 Configuring SSH protocol

The above steps would open up the Terminal window as shown in Figure 1-2.

Figure 1-2 Login screen for SSH protocol


Now type in your password, followed by which enter the following command;
./startterm
This command will invoke the GUI environment for your login. Note down the
number which is followed after “172.16.24.5” IP address and a semi-colon “:”.

Figure 1-3 Example: SSH login

Now we are into the Second step of login. Now once again click on “Connect” button
at the top left corner and then, select “VNC” protocol.

Figure 1-4 Configuring VNC protocol


1.1.2 Design procedure for Inverter static characteristics:

Tool invocation
Open a Terminal window and type
cd Database/
Now change the shell from Bash to c shell using the following command
csh
Now set the UNIX environmental variables to access the Cadence package
source cshrc
Now change the directory to “cadence_analog_labs_613”
cd cadence_analog_labs_613/
Now invoke cadence analog package “virtuoso” by typing the following command.
Note, use “&” to enable switching between the tool window and active prompt window.
virtuoso &
This will load Cadence. The Command Interpreter Window (CIW) will now load as
shown in Figure 1-5.

Figure 1-5 The cadence CIW

Creating a Design cell


“File → New → Library”. Name the library “ec64” (without quotes) and select
“Attach to an existing techfile” (Figure 1-6) and select OK. In the next window make sure
that “gpdk180” is selected and select OK.
Figure 1-6 Creating a Library and Attaching a Tech Library

Creating a Schematic
Click “File → New → Cellview” and Select library “ec64”. Name your cell
INVERTER. The tool you want to use here is Virtuoso Schematic Editor as seen in Figure
1-7.

Figure 1-7 Creating a new cell view

To add PMOS & NMOS


1. “Create → Instance” or by pressing “i” on the keyboard.
2. “Add Instance” should pop up.
3. Select the library “gpdk180”.
4. Select “nmos” from cell and then “symbol” from view.
5. Go back to the schematic and place the NMOS transistor.
6. Go back to the “Add Instance” and select “pmos”. Add this transistor to your
schematic.
7. Hit ESC to exit the Add Instance mode.
To connect components
1. Select Add → Wire or use the “w” hotkey.
To create I/O pins
1. Click Add → Pin or use the “p” hotkey.
2. Pin names and directions must be consistent between the symbol, schematic, and
layout.
To change the property
1. Use Edit → Properties → Objects or use the “q” hotkey.
2. Define the width of the PMOS transistor from its default value, say 2u, to a variable
“wp”.
Design schematic
Completed schematic should resemble Figure 1-8.

Figure 1-8 Inverter Schematic

Select “File → Check and Save” to save your schematic and make sure that there are
no errors or warnings.

Creating a Symbol
“Create → Cell View → From Cell View”

Figure 1-9 Symbol Creation

The final symbol you create should resemble that shown in Figure 1-10.
Figure 1-10 Inverter Symbol

Creating a Test cell


Select library “ec64”, and then “File → New → Cellview”. Name your cell
“INVERTER_TEST”.
To simulate the design, add the inverter symbol, signal sources, power supplies, and
loads as illustrated in Figure 1-11.

1 2
1

Figure 1-11 Inverter test schematic

DC Analysis
“Launch → ADE L”.
“Variables → Copy From Cellview”. Define “2u” for the wp variable.
In the ADE window select “Analyses → Choose”. Select “dc” and then “Component
Parameter”.
Select “Select Component” and then click on the input voltage source, V2, in the
schematic to sweep. Select “dc” as the variable to sweep when the popup window opens.
Specify sweep range: -900m into “Start” and 900m into “Stop”. Select OK.
In the ADE window select “Outputs → To be plotted” and select the wires (1,2) as
shown in Figure 1-11.
Select “Simulation → Netlist and Run” or click on the green light in the bottom right
corner.

Figure 1-12 Inverter output plot

Switching voltage
From the DC plot shown in Figure 1-12, select “Tools → Calculator”.

Figure 1-13: calculator showing cross function for VM.

In the calculator window, select “wave” radio button and go back to the wave window
and select the wave.
Now from the “special function”, select “cross”. Mirror the setting as shown in Figure
1-13.
Click Ok. Click the “Evaluate buffer” button.
VM plot
Go to ADE window, select “outputs → Setup” and mirror the settings shown in
Figure 1-14.

Figure 1-14: Switching voltage plot for varitions

Parametric analysis:
In the ADE window, click “Tools→ Parametric Analysis”. Enter the following details
as shown below.

Figure 1-15 Parametric Analysis setting

Figure 1-16 Parametric Result


Figure 1-17: Vm Vs plot

Noise margin Analysis


From the DC plot shown in Figure 1-12, select “Tools → Calculator”.
In the calculator window, select “wave” radio button and go back to the wave window
and select the wave.
Slope extraction:
From “special function” menu, select “deriv” function. This should result in Figure
1-18.

Figure 1-18: Calculator showing Deriv function in the buffer.

Click “Evaluate buffer”, which results in Figure 1-19.

Select this wave

Figure 1-19: DC Plot with derive function.


Now from the “special function”, select “cross”. Mirror the setting as shown in Figure
1-20.

Figure 1-20: Calculator showing cross function for slope calculation

Click Ok. Click the “Evaluate buffer” button. Note down the VIL value.
Just change the “Edge Number” to 2 and click “Evaluate buffer” to measure VIH.

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