Lec 08
Lec 08
• Performance
• Expandability
• Resilience in the face of failure
interrupts
Processor
Cache
° Response time:
• Begins when a task is placed in the queue
• Ends when it is completed by the server
• In order to minimize the response time:
- The queue should be empty
- The server will be idle
cs 152 L19.io.4 DAP Fa97, ? U.CB
Throughput versus Respond Time
Response
Time (ms)
300
200
100
Server
Queue
Producer
Queue Server
Done
Address Lines
BUS Data Lines
Control Lines
I/O Interface
Address Control Data Status Card
Decoder Circuits Register Register
Also Often
Integrated
on
Motherboard
I/O Port
(e.g RS232)
I/O Device
° Memory-mapped I/O:
• Portions of the address space are assigned to I/O device
• Read and writes to those addresses are interpreted
as commands to the I/O devices
• User programs are prevented from issuing I/O operations directly:
- The I/O address space is protected by the address translation
CPU
Is the
data busy wait loop
ready? not an efficient
way to use the CPU
unless the device
Memory yes no is very fast!
IOC
read
data
but checks for I/O
device completion can be
dispersed among
store computation
data intensive code
done? no
° Advantage: yes
• Simple: the processor is totally in control and does all the work
° Disadvantage:
• Polling overhead can consume a lot of CPU time
cs 152 L19.io.10 DAP Fa97, ? U.CB
Interrupt Driven Data Transfer
add
CPU sub user
(1) I/O and program
interrupt or
nop
(2) save PC
Memory
IOC (3) interrupt
service addr
read
store interrupt
device ... : service
(4) rti routine
° Advantage: memory
• User program progress is only halted during actual transfer
Transmitter Receiver
Input
Keyboard
Display
Console
device
DMAC provides handshake
signals for Peripheral
Controller, and Memory
Addresses and handshake
signals for Memory.
CPU IOP D1
main memory D2
Mem bus . . .
Dn
I/O target device
bus where cmnds are
OP Device Address
(1) Issues CPU (4) IOP interrupts
instruction CPU when done
to IOP IOP IOP looks in memory for commands
(2)
Interrupt
Handler
OS
Scheduler
Ready
Queue
Often
Prioritized
cs 152 L19.io.19 DAP Fa97, ? U.CB
Responsibilities of the Operating System
° Disk I/O Benchmarks: I/O rate vs. Data rate vs. latency
Registers
° Purpose:
Cache
Memory
• Long term, nonvolatile storage
Disk
• Large, inexpensive, and slow
• Lowest level in the memory hierarchy
Platters
Track
Sector
° Typical numbers (depending on the disk size):
• 500 to 2,000 tracks per surface
• 32 to 128 sectors per track
- A sector is the smallest unit that can be read or written
° Supercomputer application:
• Large-scale scientific problems => large files
• One large read and many small writes to snapshot computation
• Data Rate: MB/second between memory and disk
° Transaction processing:
• Examples: Airline reservations systems and bank ATMs
• Small changes to large shared software
• I/O Rate: No. disk accesses / second given upper limit for latency
° File system:
• Measurements of UNIX file systems in an engineering environment:
- 80% of accesses are to files less than 10 KB
- 90% of all file accesses are to data with sequential addresses
on the disk
- 67% of the accesses are reads, 27% writes, 6% read-write
• I/O Rate & Latency: No. disk accesses /second and response time
cs 152 L19.io.31 DAP Fa97, ? U.CB
Disk I/O Performance
Request Rate Service Rate
? ?
Disk Disk
Controller
Queue
Processor
Disk Disk
Controller
Queue
° 512 byte sector, rotate at 5400 RPM, advertised seeks is 12 ms, transfer
rate is 4 BM/sec, controller overhead is 1 ms, queue idle so no service
time
° If real seeks are 1/3 advertised seeks, then its 10.6 ms, with rotation delay
at 50% of the time!
Number of arms/box 12 1 1
° Disadvantage:
• It is primarily read-only media
° physically small - the thin serial cable can replace larger and more
expensive interfaces,
° hot pluggable - users can add or remove 1394 devices with the bus
active,
° scalable architecture - may mix 100, 200, and 400 Mbps devices on a
bus,
° fast - even multimedia data can be guaranteed its bandwidth for just-
in-time delivery, and
° non-proprietary
isochronous isochronous
channel #1 channel #1 Time slot available for asynchronous transport
time slot time slot
Timing indicator
° Example: digital video camera can expect to send one 64 byte packet
every 125 µs
• 80 * 1024 * 64 = 5MB/s