Explain memory mapped IO

An interfacing circuit is designed for an I/O device to facilitate data transfer. Input and output devices
are used to enter data as well as to take out data from microprocessor to peripheral. This interfacing
is referred to as the mapping of I/O either by using peripheral devices, i.e. I/O or by memory.

 When the processor, main memory and I/O share a common bus, two modes of addressing
are possible:

1. I/O mapped I/O

2. Memory mapped I/O

 Memory mapped I/O is an interfacing technique in which memory related instructions are
used for data transfer and the device is identified by a 16-bit address. In this type, the I/O
devices are treated as memory locations. The control signals used are MEMR and MEMW.
The interfacing between I/O and microprocessor will be same as single memory location. For
data transfer between I/O device and microprocessor, microprocessor will send address,
generate control signals MEMR and MEMW.

 In MEMR, it accepts data from I/O device while in MEMW it transfers data to I/O device.

Memory mapped I/O scheme is shown in Figure 1.In Figure 1, the left diagram is for the Read control
signal and right diagram is for the Write control signal.

 The address is of 16 bits A0 to A15. Control signals RD and WR are used to control the buffer
latch. Combination of address lines A0-A15 can be done by using NAND gates and then it is
combined with RD or WR signal. For buffer when A0 to A15 are at logic 1, the output of
NAND gate will be low.
  With memory-mapped I/O, there is a single address space for memory locations and I/O
devices. The processor treats the status and data registers of I/O modules as memory
locations and uses the same machine instructions to access both memory and I/O devices.

 For example, with 10 address lines, a combined total of 210 1024 memory locations and I/O
addresses can be supported, in any combination. With memory-mapped I/O, a single read
line and a single write line are needed on the bus.

 Advantage of memory-mapped I/O is that this large stock of instructions can be used,
allowing more efficient programming.

 A disadvantage is that valuable memory address space is used up.

 In memory mapped I/O,

i. I/O and memory, both in combination are treated as memory.

ii. Device address is of 16-bits.

iii. MEMR and MEMW control signals are used and Arithmetic and logical operations are performed.

iv. Memory related instructions are available such as LDA, STA.

v. Data transfer takes place between any register and I/O.It consists of a total of 64K devices.

vi. Decoding 16-bits of address is required, therefore more hardware required.

DMA Modes.
DMA modes are methods computer systems use to transfer data between devices and memory
without involving the CPU. Here are some of the common DMA modes:

 Block mode: Also known as burst mode DMA, this mode allows for transferring multiple data
blocks in a single DMA operation. It reduces overhead by transferring consecutive data
blocks without releasing control of the system bus after each block.

 Demand mode: In this mode, the DMA controller only transfers data when the CPU requests
it. It waits for a request signal from the CPU before initiating data transfer, which helps
reduce unnecessary data transfers and system bus contention.

 Cycle stealing: This mode allows the DMA controller to temporarily take over control of the
system bus from the CPU during data transfer cycles. It steals CPU cycles to perform data
transfers, allowing both the CPU and DMA controller to access the system bus alternately.

 Fly-by: Also known as chain mode DMA, this mode allows continuous data transfer between
devices and memory without CPU intervention. The DMA controller continuously transfers
data from one device to memory and then to another device in a sequential manner
n this section, we will see different addressing modes of the 8051
microcontrollers. In 8051 there are 1-byte, 2-byte instructions and very few 3-byte
instructions are present. The opcodes are 8-bit long. As the opcodes are 8-bit data, there are 256
possibilities. Among 256, 255 opcodes are implemented.

The clock frequency is12MHz, so 64 instruction types are executed in just 1 µs, and rest are just 2 µs.
The Multiplication and Division operations take 4 µsto to execute.

In 8051 There are six types of addressing modes.

 Immediate AddressingMode

 Register AddressingMode

 Direct AddressingMode

 Register IndirectAddressing Mode

 Indexed AddressingMode

 Implied AddressingMode

Immediate addressing mode

In this Immediate Addressing Mode, the data is provided in the instruction itself. The data is provided
immediately after the opcode. These are some examples of Immediate Addressing Mode.

MOVA, #0AFH;

MOVR3, #45H;

MOVDPTR, #FE00H;

In these instructions, the # symbol is used for immediate data. In the last instruction, there is DPTR.
The DPTR stands for Data Pointer. Using this, it points the external data memory location. In the first
instruction, the immediate data is AFH, but one 0 is added at the beginning. So when the data is
starting with A to F, the data should be preceded by 0.

Register addressing mode

In the register addressing mode the source or destination data should be present in a register (R0 to
R7). These are some examples of RegisterAddressing Mode.

MOVA, R5;

MOVR2, #45H;

MOVR0, A;

In 8051, there is no instruction like MOVR5, R7. But we can get the same result by using this
instruction MOV R5, 07H, or by using MOV 05H, R7. But this two instruction will work when the
selected register bank is RB0. To use another register bank and to get the same effect, we have to
add the starting address of that register bank with the register number. For an example, if the RB2 is
selected, and we want to access R5, then the address will be (10H + 05H = 15H), so the instruction
will look like this MOV 15H, R7. Here 10H is the starting address of Register Bank 2.
Direct Addressing Mode

In the Direct Addressing Mode, the source or destination address is specified by using 8-bit data in
the instruction. Only the internal data memory can be used in this mode. Here some of the examples
of direct Addressing Mode.

MOV80H, R6;

MOVR2, 45H;

MOVR0, 05H;

The first instruction will send the content of registerR6 to port P0 (Address of Port 0 is 80H). The
second one is forgetting content from 45H to R2. The third one is used to get data from Register R5
(When register bank RB0 is selected) to register R5.

Register indirect addressing Mode

In this mode, the source or destination address is given in the register. By using register indirect
addressing mode, the internal or external addresses can be accessed. The R0 and R1 are used for 8-
bit addresses, and DPTR is used for 16-bit addresses, no other registers can be used for addressing
purposes. Let us see some examples of this mode.

MOV0E5H, @R0;

MOV@R1, 80H

In the instructions, the @ symbol is used for register indirect addressing. In the first instruction, it is
showing that theR0 register is used. If the content of R0 is 40H, then that instruction will take the
data which is located at location 40H of the internal RAM. In the second one, if the content of R1 is
30H, then it indicates that the content of port P0 will be stored at location 30H in the internal RAM.

MOVXA, @R1;

MOV@DPTR, A;

In these two instructions, the X in MOVX indicates the external data memory. The external data
memory can only be accessed in register indirect mode. In the first instruction if the R0 is holding
40H, then A will get the content of external RAM location40H. And in the second one, the content of
A is overwritten in the location pointed by DPTR.

Indexed addressing mode

In the indexed addressing mode, the source memory can only be accessed from program memory
only. The destination operand is always the register A. These are some examples of Indexed
addressing mode.

MOVCA, @A+PC;

MOVCA, @A+DPTR;
The C in MOVC instruction refers to code byte. For the first instruction, let us consider A holds 30H.
And the PC value is1125H. The contents of program memory location 1155H (30H + 1125H) are
moved to register A.

Implied Addressing Mode

In the implied addressing mode, there will be a single operand. These types of instruction can work
on specific registers only. These types of instructions are also known as register specific instruction.
Here are some examples of Implied Addressing Mode.

RLA;

SWAPA;

These are 1- byte instruction. The first one is used to rotate the A register content to the Left. The
second one is used to swap the nibbles in A.

Serial communication in 8051

Microcontrollers can communicate data in either parallel form or serial form.
in serial communication, data is transferred in bit by bit manner over a single wire. For
example if a microcontroller 1 is transferring data to another microcontroller 2 in serial form
then TXD pin of microcontroller 1 will be connected to RXD pin of microcontroller 2 and data
is transferred from microcontroller 1 to microcontroller 2 in bit by bit manner over a single
wire. If microcontroller 2 wants to send some data to microcontroller 1 then for that TXD
pin of microcontroller 2 must be connected to RXD pin of microcontroller 1 and again data
bits will be transferred over a single wire. So it is clear that for full duplex communication of
data two wires are involved and for simplex communication only one wire will be involved.
Serial communication is preferred when the distance b/w transmitter and receiver is large
and it is required to save the cabling cost and reduce h/w complexity but definitely this
comes at the cost of reduced speed of data transfer.
In serial communication parallel to serial converter and serial to parallel converter module is
required. In 8051 in built UART (Universal Asynchronous Receiver Transmitter) module
performs the job of serial communication of data
Data communication process can be synchronous or asynchronous. The following points
clearly discriminates between these two modes of data transfer-

 Synchronous data transfer: sender and receiver use the same clock signal
 supports high data transfer rate
  needs clock signal between the sender and the receiver
 requires master/slave configuration
 Asynchronous data transfer: sender provides a synchronization signal to the
receiver before starting the transfer of each message
 does not need clock signal between the sender and the receiver
 slower data transfer rate

In 8051 microcontroller serial communication of data is performed with the help of

following special purpose registers-

1. SBUF (Serial buffer register)

2. SCON (serial control register)
3. TMOD (Timer mode register)
4. TCON (Timer control register)
5. TH1 (Timer1 register higher byte)

Addressing Modes in 8085

These are the instructions used to transfer the data from one register to
another
register, from the memory to the register, and from the register to the memory without
any alteration in the content. Addressing modes in 8085 is classified into 5 groups −

Immediate addressing mode

In this mode, the 8/16-bit data is specified in the instruction itself as one of
its
operand. For example: MVI K, 20F: means 20F is copied into register K.

Register addressing mode

In this mode, the data is copied from one register to another. For example: MOV K, B:
means data in register B is copied to register K.

Direct addressing mode

In this mode, the data is directly copied from the given address to the register. For
example: LDB 5000K: means the data at address 5000K is copied to register B.

Indirect addressing mode

In this mode, the data is transferred from one register to another by using the address
pointed by the register. For example: MOV K, B: means data is transferred from the
memory address pointed by the register to the register K.

Implied addressing mode

This mode doesn’t require any operand; the data is specified by the opcode itself. For
example: CMP.

Interrupts in 8085
Interrupts are the signals generated by the external devices to request the
microprocessor to perform a task. There are 5 interrupt signals, i.e. TRAP, RST 7.5,
RST 6.5, RST 5.5, and INTR.
Interrupt are classified into following groups based on their parameter −
Vector interrupt − In this type of interrupt, the interrupt address is known to the
processor. For example: RST7.5, RST6.5, RST5.5, TRAP.
Non-Vector interrupt − In this type of interrupt, the interrupt address is not
known to the processor so, the interrupt address needs to be sent externally by
the device to perform interrupts. For example: INTR.
Maskable interrupt − In this type of interrupt, we can disable the interrupt by
writing some instructions into the program. For example: RST7.5, RST6.5,
RST5.5
Addressing Modes in 8085
These are the instructions used to transfer the data from one register to
another
register, from the memory to the register, and from the register to the memory without
any alteration in the content. Addressing modes in 8085 is classified into 5 groups −
Immediate addressing mode
In this mode, the 8/16-bit data is specified in the instruction itself as one of
its
operand. For example: MVI K, 20F: means 20F is copied into register K.
Register addressing mode
In this mode, the data is copied from one register to another. For example: MOV K, B:
means data in register B is copied to register K.
Direct addressing mode
In this mode, the data is directly copied from the given address to the register. For
example: LDB 5000K: means the data at address 5000K is copied to register B.
Indirect addressing mode
In this mode, the data is transferred from one register to another by using the address
pointed by the register. For example: MOV K, B: means data is transferred from the
memory address pointed by the register to the register K.
Implied addressing mode
This mode doesn’t require any operand; the data is specified by the opcode itself. For
example: CMP.
Interrupts in 8085
Interrupts are the signals generated by the external devices to request the
microprocessor to perform a task. There are 5 interrupt signals, i.e. TRAP, RST 7.5,
RST 6.5, RST 5.5, and INTR.
Interrupt are classified into following groups based on their parameter −
Vector interrupt − In this type of interrupt, the interrupt address is known to the
processor. For example: RST7.5, RST6.5, RST5.5, TRAP.
Non-Vector interrupt − In this type of interrupt, the interrupt address is not
known to the processor so, the interrupt address needs to be sent externally by
the device to perform interrupts. For example: INTR.
Maskable interrupt − In this type of interrupt, we can disable the interrupt by
writing some instructions into the program. For example: RST7.5, RST6.5,
RST5.5
Non-Maskable interrupt − In this type of interrupt, we cannot disable the
interrupt by writing some instructions into the program. For example: TRAP.
Software interrupt − In this type of interrupt, the programmer has to add the
instructions into the program to execute the interrupt. There are 8 software
interrupts in 8085, i.e. RST0, RST1, RST2, RST3, RST4, RST5, RST6, and
RST7.
Hardware interrupt − There are 5 interrupt pins in 8085 used as hardware
interrupts, i.e. TRAP, RST7.5, RST6.5, RST5.5, INTA.
Note − NTA is not an interrupt, it is used by the microprocessor for sending
acknowledgement. TRAP has the highest priority, then RST7.5 and so on.
Interrupt Service Routine (ISR)
A small program or a routine that when executed, services the corresponding
interrupting source is called an ISR.
TRAP
It is a non-maskable interrupt, having the highest priority among all interrupts. Bydefault,
it is enabled until it gets acknowledged. In case of failure, it executes as ISR and sends
the data to backup memory. This interrupt transfers the control to the location 0024H.
RST7.5
It is a maskable interrupt, having the second highest priority among all interrupts. When
this interrupt is executed, the processor saves the content of the PC register into the
stack and branches to 003CH address.
RST 6.5
It is a maskable interrupt, having the third highest priority among all interrupts. When
this interrupt is executed, the processor saves the content of the PC register into the
stack and branches to 0034H address.
RST 5.5
It is a maskable interrupt. When this interrupt is executed, the processor saves the
content of the PC register into the stack and branches to 002CH address.
INTR
It is a maskable interrupt, having the lowest priority among all interrupts. It can be
disabled by resetting the microprocessor.
When INTR signal goes high, the following events can occur −
The microprocessor checks the status of INTR signal during the execution of
each instruction.
When the INTR signal is high, then the microprocessor completes its current
instruction and sends active low interrupt acknowledge signal.
When instructions are received, then the microprocessor saves the address of
the next instruction on stack and executes the received instruction

What is DAA Instruction 8085

The DAA (Decimal Adjust Accumulator ) instruction in the 8085 microprocessor is used for
the addition of BCD (binary-coded Decimal). The addition of BCD is done similarly to the
binary addition using the ADD instruction. DAA is used to convert the result of the BCD sum
which is available in the accumulator into a binary number. This instruction cannot be used
directly to convert binary numbers into BCD numbers.
The DAA instruction is used after instructions like ADD, ADI, ACI, ADC, etc. After the
execution of these instructions, the result is in hexadecimal form (in Accumulator). The DAA
instruction operates on this result and gives the final result in decimal form.
 The DAA instruction is used after instructions like ADD, ADI, ACI, ADC, etc. That adds
two BCD numbers.After the execution of these instructions, the result is in BCD form
in the Accumulator .
 The DAA instruction is executed to adjust the result to a valid BCD number.

 Timing Diagram of DAA Instruction

 The DAA instruction requires 1 Byte and 1 machine cycle
and 4 T-States. So this DAA instruction is used to support
the Binary Coded Decimal addition . This requires 1-Byte ,
1-Machine Cycle(opcode fetch) and 4 T-States for execution
as shown in the timing diagram.


‘
the different types of memory used in a processor include:
 Random access memory (RAM)

A type of volatile memory that temporarily stores data while the CPU is processing other tasks. RAM
is fast, but it loses its data when the power is turned off.

 Read-only memory (ROM)

A type of non-volatile memory that stores programs as read-only data. ROM is used to start up a
computer and retains its data even when the power is turned off.

 Cache memory

Provides faster access to memory functions for the CPU. Cache memory is often consolidated on the
CPU itself.

 Programmable read-only memory (PROM)

A type of ROM that is manufactured without data and can be programmed after the fact.

 Erasable programmable read-only memory (EPROM)

A type of ROM chip that can be written to, erased, and reprogrammed.

 Electrically erasable programmable read-only memory (EEPROM)

A type of non-volatile ROM chip that usually replaces the need for PROM or EPROM chips.

Other types of memory include: Dynamic random access memory (DRAM), Static random access
memory (SRAM), Magnetic tape, and Optical discs.

What is a Timing Diagram of 8085?

A Timing Diagram of 8085 is a graphical representation that shows the relationship between control
signals, status signals, and data signals during various operations in the 8085 microprocessor. It
explains how instructions are fetched and executed in terms of clock cycles, highlighting the
interaction between the CPU and memory or peripheral devices. Timing diagrams are crucial because
they provide detailed insights into the 8085 microprocessor's internal processes. These processes
include fetching, decoding, and executing instructions, and understanding them is critical for system
design and debugging.

Machine Cycle of 8085

In the 8085 microprocessor, a machine cycle refers to the time taken to execute a basic operation,
such as reading or writing from memory or fetching an opcode. Each machine cycle consists of
multiple clock cycles, and understanding these cycles is crucial for interpreting the Timing Diagram of
8085.

The primary machine cycles of the 8085 are:

o Opcode Fetch Cycle

o Memory Read Cycle

o Memory Write Cycle

o I/O Read Cycle

o I/O Write Cycle

Each of these cycles is executed in synchronization with the system clock, and their timing diagrams
provide a visual understanding of how each operation unfolds.

he Opcode Fetch Machine Cycle is the first machine cycle in the execution of any instruction. During
this cycle, the 8085 microprocessor fetches the opcode of the instruction from memory and stores it
in the instruction register. This cycle is longer than other machine cycles because it involves fetching
and decoding the instruction.

Phases of Opcode Fetch:

o T1 (First Clock Cycle): The address of the memory location is placed on the address bus, and
the control signal ALE is activated to latch the lower byte of the address.

o T2 (Second Clock Cycle): The RD signal is activated, and the data from the memory is placed
on the data bus.

o T3 (Third Clock Cycle): The microprocessor reads the opcode from the data bus and stores it
in the instruction register.
Memory Read Machine Cycle of 8085

The Memory Read Machine Cycle is used when the 8085 microprocessor needs to read data from a
memory location. This cycle is initiated after the opcode fetch if the instruction involves reading from
memory.

Phases of Memory Read:

o T1 (First Clock Cycle): The address of the memory location is placed on the address bus, and
ALE is activated to latch the lower byte of the address.

o T2 (Second Clock Cycle): The RD signal is activated, and the data from the memory location is
placed on the data bus.

o T3 (Third Clock Cycle): The microprocessor reads the data from the data bus.

Memory Write Machine Cycle of 8085

The Memory Write Machine Cycle is used when the microprocessor writes data to a specific memory
location. During this cycle, the microprocessor places the data on the data bus and the memory
address on the address bus.

Phases of Memory Write:

o T1 (First Clock Cycle): The address of the memory location is placed on the address bus, and
ALE is activated to latch the lower byte of the address.

o T2 (Second Clock Cycle): The WR signal is activated, and the data is placed on the data bus.

o T3 (Third Clock Cycle): The memory write operation is completed as the data is written to
the memory location.

I/O Read Machine Cycle of 8085

The I/O Read Machine Cycle is used when the microprocessor reads data from an I/O device. The
microprocessor places the address of the I/O device on the lower byte of the address bus and then
activates the RD signal to read the data.

I/O Write Machine Cycle of 8085

The I/O Write Machine Cycle occurs when the microprocessor writes data to an I/O device. Similar to
memory write, the microprocessor places the data on the data bus and the I/O address on the
address bus, then activates the WR signal to write the data.

Applications of Timing Diagram of 8085

The Timing Diagram of 8085 has practical applications in various fields of electrical engineering and
computer science, particularly in embedded system design and hardware development.

Key Applications:

o Microprocessor System Design: Timing diagrams help engineers design systems that
function efficiently by coordinating with the microprocessor's clock cycles.

o Debugging and Optimization: Understanding the timing diagram allows developers to debug
hardware-related issues and optimize the system's speed and efficiency.
 o Embedded System Design: Timing diagrams are crucial for designing embedded systems
where microprocessors and peripheral devices must communicate seamlessly.

 During T1 state, microprocessor uses IO/M(bar), S0, S1 signals are used to instruct microprocessor
to fetch opcode.

 Thus when IO/M(bar)=0, S0=S1= 1, it indicates opcode fetch operation.

 During this operation 8085 transmits 16-bit address and also uses ALE signal for address latching.

 At T2 state microprocessor uses read signal and make data ready from that memory location to
read opcode from memory and at the same time program counter increments by 1 and points next
instruction to be fetched.

 n this state microprocessor also checks READY input signal, if this pin is at low logic level ie. '0' then
microprocessor adds wait state immediately between T2 and T3.

 At T3, microprocessor reads opcode and store it into instruction register to decode it further.
 During T4 microprocessor performs internal operation like decoding opcode and providing
necessary actions.

 The opcode is decoded to know whether T5 or T6 states are required, if they are not required then
µp performs next operation.

STEPPPER MOTOR INTYERFACE 8085