Data Sampling in SystemVerilog

Data sampling is a crucial aspect of functional coverage in SystemVerilog, allowing you to capture
the values of variables or signals at specific points in time during simulation. This ensures that all
relevant scenarios and conditions in the design are tested.

9.7.1 Individual Bins and Total Coverage

Individual Bins:

 Bins are used to categorize the values of a coverpoint. Each bin represents a range or a specific
value of the variable being sampled.
 Individual bins are explicitly defined by the user to cover specific values or ranges of values.
This allows for detailed tracking of how often each value or range is hit during simulation.

Total Coverage:

 Total coverage refers to the overall percentage of bins that have been hit during simulation. It
provides a measure of how thoroughly the design has been tested.
 Achieving high total coverage ensures that all defined scenarios have been exercised, helping
to identify any gaps in the test plan.

9.7.2 Creating Bins Automatically

Automatic Bins:

 Automatic bins (or implicit bins) are created by the simulator for each possible value of the
coverpoint variable. This simplifies the process of defining coverage points, especially for
variables with a large range of values.
 For example, if you have a 4-bit variable, the simulator will automatically create 16 bins (one for
each possible value from 0 to 15).

Here's an example to illustrate automatic bin creation:

bit [3:0] mode;

covergroup cg @(posedge clk);

coverpoint mode {
bins auto_bins[] = {[0:$]}; // Automatically create bins for all values
of mode
}
Endgroup

initial begin
cg cg_inst = new();
cg_inst.sample();
end

In this example:

 Variable mode: A 4-bit variable for which we want to measure coverage.

 Covergroup cg: Defines the coverage model and specifies that sampling occurs on the positive
edge of the clock (@(posedge clk)).
 Coverpoint mode: Uses the bins auto_bins[] = {[0:$]}; statement to automatically
create bins for all possible values of mode (from 0 to 15).

Summary

 Data Sampling: Captures the values of variables at specific points in time to measure coverage.
 Individual Bins: Explicitly defined bins for specific values or ranges.
 Total Coverage: Overall percentage of bins hit during simulation.
 Automatic Bins: Simplifies bin creation by automatically generating bins for all possible values
of a variable.

These concepts are essential for achieving comprehensive functional coverage in SystemVerilog,
ensuring that your design is thoroughly tested and verified.

Would you like more details on any specific aspect of data sampling or bin creation?

9.7.3 Limiting the Number of Automatic Bins Created

In SystemVerilog, you can limit the number of automatic bins created for a coverpoint by using
the option.auto_bin_max setting. This setting specifies the maximum number of bins that can
be automatically created for a coverpoint. If the number of possible values exceeds this limit, the
values are grouped into the specified number of bins.

covergroup cg @(posedge clk);

option.auto_bin_max = 16; // Limit the number of automatic bins to 16
coverpoint mode;
endgroup

9.7.4 Sampling Expressions

Sampling expressions allow you to capture the values of expressions, not just simple variables, at
specific points in time. This is useful for more complex coverage scenarios.

covergroup cg @(posedge clk);

coverpoint (a + b);
endgroup

9.7.5 User-Defined Bins Find a Bug

User-defined bins allow you to specify exact values or ranges of interest. This can help identify
specific scenarios that might cause bugs.
covergroup cg @(posedge clk);
coverpoint mode {

bins specific_values[] = {3, 7, 15};

}
endgroup

9.7.6 Naming the Cover Point Bins

Naming bins helps in identifying and reporting specific coverage scenarios. This makes it easier to
understand coverage reports.

covergroup cg @(posedge clk);

coverpoint mode {
bins low = {0, 1, 2};
bins mid = {3, 4, 5};
bins high = {6, 7, 8};
}
endgroup

9.7.7 Conditional Coverage

Conditional coverage allows you to collect coverage data only when certain conditions are met.
This is useful for focusing on specific scenarios.

covergroup cg @(posedge clk);

coverpoint mode iff (enable);
endgroup

9.7.8 Creating Bins for Enumerated Types

For enumerated types, you can create bins for each enumerated value, ensuring that all possible
states are covered.

typedef enum {IDLE, RUN, STOP} state_t;

state_t state;

covergroup cg @(posedge clk);

coverpoint state;
endgroup

9.7.9 Transition Coverage

Transition coverage tracks changes from one value to another, which is useful for state machines
and other sequential logic.
covergroup cg @(posedge clk);
coverpoint state {

bins transitions[] = (IDLE => RUN, RUN => STOP, STOP => IDLE);
}
endgroup

9.7.10 Wildcard States and Transitions

Wildcard bins allow you to specify ranges or patterns of values, which can simplify coverage for
large or complex state spaces.

covergroup cg @(posedge clk);

coverpoint data {
wildcard bins range[] = {[4'b0000:4'b1111]};
}
endgroup

9.7.11 Ignoring Values

Ignore bins exclude certain values from coverage, which can be useful for values that are not
relevant or should not occur.

covergroup cg @(posedge clk);

coverpoint mode {
ignore_bins invalid = {10, 11, 12};
}
endgroup

9.7.12 Illegal Bins

Illegal bins mark certain values as illegal, causing an error if they are encountered during simulation.
This helps catch unexpected or erroneous behavior.

covergroup cg @(posedge clk);

coverpoint mode {
illegal_bins error_values = {13, 14, 15};
}
endgroup

9.7.13 State Machine Coverage

State machine coverage ensures that all states and transitions in a finite state machine (FSM) are
exercised.
typedef enum {S0, S1, S2} fsm_state_t;
fsm_state_t state;

covergroup cg @(posedge clk);

coverpoint state {

bins states[] = {S0, S1, S2};

bins transitions[] = (S0 => S1, S1 => S2, S2 => S0);
}
endgroup

These concepts and examples help ensure comprehensive coverage in your verification process,
making it easier to identify and address potential issues in your design. If you have any specific
questions or need further details, feel free to ask!