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Module 1 Avlsi Notes

MOD !AVLSI

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20 views24 pages

Module 1 Avlsi Notes

MOD !AVLSI

Uploaded by

Akash
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Structured a Orray Lith O10 (allt) em broded pu _ovroy 4% cooly inGr Connect tr (wstomi 0 4 wustor blOCKs Can be embed) 4 manuf ctaring cod time tm bur THO JOH 9 Two woeees : 1.1.4 Channeled Gate Array Achanneled gate array * Only the interconnect is customized * The interconnect uses predefined spaces between rows of base cells '* Manufacturing lead time is between two days and two weeks [ago oooS cooo Sooo oooooo) DoooCoooooooooooo0o base cell (SleleleTele[efe[s[elelele[s[eTe[=lalelele IGDOoOOoooooooO Goo a 1.1.5 Channelless Gate Array Achannelless gate array (channel-free gate array, sea- of-gates array, or SOG array) * Only some (the top few) mask layers are customized— the interconnect * Manufacturing lead time is between two days and two weeks. 00] (aooooooCooooooC0ou! DooooocoooooCooooo Soo cos eeooooHoooooND) NO OOOO SoHo oooS ooo 1.1.6 Structured Gate Array An embedded gate array or structured gate : 5 embedded array (masterslice or masterimage) block * Only the interconnect is customized * Custom blocks (the same for each design) can be embedded * Manufacturing lead time is between two days and two weeks. array of base cel (not all Oy 13| 13] IG| Io| Ia| Io| Io| Io I3| Io] I5| Ig| Ia Ia] | | | fa fs 10) shown) PoSooHooOOooS OCI 1.1.7 Programmable Logic Devices A programmable logic device (PLD) ‘OoUoooOeGoCoooooo | * No customized mask layers or logic cells aMnnte a BI * Fast design turnaround macrocell Tian | S| * A single large block of programmable intercon- Co: | nect Tn a CZ | * A matrix of logic macrocells that usually consist of ‘ima | i i C=) programmable array logic followed by a flip-flop or aT S| latch programmabie | interconnect fl So CSS ooOO Sooo AeSIaD| exp (culo foltowoinas : i tL Tlo“eus 7 US Catt Compile r(O Celts gho Now OY ‘tnput [Output pe Cus 7 qs OF Pods 1 tronsenittiog & He Thay Axe wy poosib’ © from _Astc v Raiving {Aq fo an a U & boaGions i7 i. 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Pronslaus i teve ) aw! +0 vO high ~ leve } ae (we! _MORS cell enudte into OP tins 20! ow Ad Hol od Ust “foe MAUS! po tte Ubron a ation :- ee op Umi ration Auch os Ove. eda Uming improvement & Pow midimi ration, word dof nett wien ee Str Time Mo~ eh, OTR Prodveivity Alain booth multi pu) Stor-+) jae ©, aio M &MuWG pli card) q Q = sulupl'v Lt tount — c ie free pete i Re ee ers SLE et “te aE Rigid 4, 8 Q., = (pun + & Count) | asset ath clascmate. —<—<—<—<———— 4 booth mui ptin w» an method fo» Mu Cliplaing two Bignta — birory intchns oe i roiGatirathon _4t ~ multip tcant v Stora 4p magic A | The muWip¥ur_» S06 18 & + 7, with on tata pit Q-. St 100, ~ _altumutotor b inital! to 0, j Q- fora Wont= _ttretioo | St ft exominn Kee LUPS | t. ip. Qn Qn 200 oy tl NO acPoob talan | ue “b He bit pws & Ol. tte mui UGod vy “added 0 product | in tp BM pair 10. the mul@PUcand UV Qa S fecha fron Product. 3. 'epeot:- & 4 Yee SUP 2 UStl theoo of ItroGon €9u0N the NO oh bits }o nv WP Un, ~ Carry-Select Adder A carry-select adder is a high-performance adder architecture that significantly reduces the critical path delay compared to a simple ripple-carry adder. It achieves this by pre-computing two possible sums for each block of bits, one assuming a carry-in of O and the other assuming a carry-in of 1. Working Principle: 1. Block Division: The adder is divided into smaller blocks of bits. 2. Parallel Computation: For each block, two ripple-carry adders operate in parallel: * Adder 1: Assumes a carry-in of O. * Adder 2: Assumes a carry-in of 1. 3. Multiplexer Selection: Once the actual carry-in to the block is determined, a multiplexer selects the correct sum and carry-out from the appropriate adder. Diagram: Ripple Carry Adder Aripple carry adder is the simplest and most basic type of digital adder. It's composed of a series of full adders connected in a cascade. Working Principle: 1. Full Adder: The fundamental building block is a full adder. It takes three inputs: two bits to be added (A and B) and a carry-in bit (Cin). It produces two outputs: a sum bit (S) and a carry-out bit (Cout). 2. Cascading: * The first full adder adds the least significant bits (LSBs) of the two input numbers, along with the initial carry-in (which is usually 0). * The carry-out from the first full adder becomes the carry-in for the second full adder, and so on. * This process "ripples" through the chain of full adders, with each stage waiting for the carry-in from the previous stage before it can produce its sum and carry-out. Diagram: Block Diagram Full Full Full Full c, | Adder | c, Adder | c, | Adder | C, Adder | Gr | : | | | wwwwlsiverify.com S3 S, S; So 4-Bit Ripple Carry Adder Carry Lookahead Adder (CLA) A Carry Lookahead Adder is a high-performance adder that significantly speeds up addition Compared to a ripple carry adder. It achieves this by Pre-computing carry signals, eliminating the need to wait for carries to propagate through each stage. Key Concepts: * Corry Generate (G): A signal that indicates whether a particular stage will always produce a carry-out, regardless of the carry-in. Carry Propagate (P): A signal that indicates whether a carry-in to a stage will always propagate to the next stage. Working Principle: 1. Generate and Propagate Signals: * For each stage, the Generate (G) and Propagate (P) signals are calculated based on the input bits (A and B). * G=A"B + P=A@B (where * represents AND and © represents XOR) 2. Carry Calculation: * The carry-out (C) for each stage is determined using the following logic: * Cy=G,+P,*Co * Cz=G, +P, *C,=G, + P2* (G, + Py * Co) = Gi+ P2*G,+P2*P,*Co + Cy=Gs+Ps* C= Gs +Ps* Gr + Ps *Pr* G Ps*P2* Py* Co 3. Sum Calculation: * Once the carry signals are determined, the sum (S) for each stage is calculated using the XOR of the input bits and the corresponding carry-in. 1 - bit Full Adder 1 - bit Full Adder 1 - bit 1 - bit Full Adder Full Adder 1. Carry-Skip Adder * Principle: * Divides the adder into blocks. * Within each block, carries propagate normally. * If a block generates a carry-out, it "skips" to the next block. * Multiplexers select between the propagated carry within a block or the skipped carry from the previous block. Block diagram of Carry skip adder 2. Carry-Select Adder * Principle: * Pre-computes two sums for each block: one assuming a carry-in of O, and another assuming a carry-in of 1. - A multiplexer selects the correct sum based on the actual carry-in. * Diagram: 3. Carry-Save Adder * Principle: * Adds three binary numbers to produce two binary numbers. * The two output numbers represent the sum in a redundant form (carry and sum bits are not combined). * Diagram: sq) ©Elprocus.com 5(0) Carry Save Adder Circuit U. Carry-Bypass Adder * Principle: - Similar to a carry-skip adder, but with a simpler bypass mechanism. * Bypasses blocks only when all bits within the block generate a carry. * Diagram: u-bit carry bypass adder

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