Experiment No: 1

Date: ……. /……. /……………

Verification of logic gates
Aim: To verify the truth table of various logic gates

Equipment and Components Required:

SL.No Equipment/Components Range Quantity
1 IC TRAINER KIT - 1
2 PATCH CORDS - 5
3 AND GATE IC 7408 1
4 OR GATE IC7432 1
5 NOT GATE IC 7404 1
6 NAND GATE IC 7400 1
7 NORGATE IC 7402 1
8 X-OR GATE IC 7486 1

Theory:

Circuits that take the logical decision are called logic gates. Each gate has one or more input and only
one output. OR, AND and NOT are basic gates. NAND and NOR are known as universal gates, since basic
gates can be formed from these gates.

Working principle:

And Gate:

The AND gate performs a logical multiplication commonly known as AND function. The output is
high when both the inputs are high. The output is low level when any one of the inputs is low.

Or Gate:

The OR gate performs a logical addition commonly known as OR function. The output is high
when any one of the inputs is high. The output is low level when both the inputs are low.

Not Gate:

The NOT gate is called an inverter. The output is high when the input is low. The output is
low when the input is high. Here odd numbered pins represents inputs, even numbered pins represents
outputs. Seventh pin represents ground, fourteen pin represents VCC supply voltage.
Nand Gate:

The NAND gate is a contraction of AND-NOT. The output is high when both inputs arelow
and any one of the input is low. The output is low level when both inputs are high.

Nor Gate:

The NOR gate is a contraction of OR-NOT. The output is high when both inputs are low.
The output is low when one or both inputs are high.

X- Or Gate:

The output is high when any one of the inputs is high. The output is low when both theinputs are
low and both the inputs are high.

Experiment Procedure:

• IC is placed in the slot provided on the IC trainer kit.

• IC should be placed on the slot with notch on the topside of the slot.
• The left side of the notch is pin no.1 and sequentially it goes.
• 7th pin is connected to ground and 14th pin to VCC on the kit.
• For input connection, a wire is connected between the input terminal and switch.
• For output connection, a wire is connected between the output terminal and LED.
• Connections are given as per the logic Diagram.
• Power supply is switched on. Input switch positions are changed as per the truth table and output
are verified.
AND GATE:

Fig.2. Symbol for AND gate

Pin Diagram

AND Gate Truth Table

OR GATE:

Fig.1. Symbol for OR Gate

Pin Diagram

OR Gate Truth Table

NOT GATE:

Fig.3. Symbol for NOT gate

Pin Diagram

NOT Gate Truth Table

NAND GATE:

Fig.4. Symbol for NAND gate

NAND Gate Truth Table

NOR GATE:

Fig.5. Symbol for NOR gate

Pin Diagram

NOR GATE TRUTH TABLE

EX-OR GATE:

Fig.4. Symbol for XOR gate

Pin Diagram

XOR Gate Truth Table

Result:

Thus the truth table of all logic gates have been verified.
 Experiment No: 2a
Date: ……. /……. /……………

Design and implementation of Adder and Subtractor

circuits using Logic gates

Aim: To design and implement adder and subtractor circuits using logic gates.

Equipment and Components Required:

SL.No Equipment/Components Range Quantity
1 IC TRAINER KIT - 1
2 PATCH CORDS - -
3 AND GATE IC 7408 1
4 OR GATE IC7432 1
5 NOT GATE IC 7404 1
6 EX-OR GATE IC 7486 1

Theory:

Half Adder:
A half adder has two inputs for the two bits to be added and two outputs one from the sum
‘S’ and other from the carry ‘ c’ into the higher adder position. Above circuit is called asa carry signal
from the addition of the less significant bits sum from the X-OR Gate the carry out from the AND gate.

Full adder:
A full adder is a combinational circuit that forms the arithmetic sum of input; it consists of three
inputs and two outputs. A full adder is useful to add three bits at a time but a half adder cannot do so.
In full adder sum output will be taken from X-OR Gate, carry output will be taken from OR Gate.

Half subtractor:
The half subtractor is constructed using X-OR and AND Gate. The half subtractor has two input
and two outputs. The outputs are difference and borrow. The difference can be applied using X-OR
Gate, borrow output can be implemented using an AND Gate and an inverter.

Full subtractor:
The full subtractor is a combination of X-OR, AND, OR, NOT Gates. In a full subtractor the
logic circuit should have three inputs and two outputs. The two half subtractor put together gives a full
subtractor .The first half subtractor will be C and A B. The output will be difference output of full
subtractor. The expression AB assembles the borrow output of the half subtractor and the second term
is the inverted difference output of first X-OR.
Experiment Procedure:

• IC is placed in the slot provided on the IC trainer kit.

• IC should be placed on the slot with notch on the topside of the slot.
• The left side of the notch is pin no.1 and sequentially it goes.
• 7th pin is connected to ground and 14th pin to VCC on the kit.
• For input connection, a wire is connected between the input terminal and switch.
• For output connection, a wire is connected between the output terminal and LED.
• Connections are given as per the logic Diagram.
• Power supply is switched on. Input switch positions are changed as per the truth table and output
are verified.
 Truth table:
Half adder:

K-map simplification:

Logic diagram:
Full adder:

Truth table:

K-map simplification:

Logic diagram:
 Truth table:

Halfsubtractor:

K-map simplification:

Logic diagram:
 Full subtractor:
Truth table:

K-map simplification:

Logic Diagram:
Logic Diagram:

D-Difference B- Borrow
Result:

Thus the adder and subtractor logic circuits were designed and their outputs were verified.
 Experiment No: 2b
Date: ……. /……. /……………

Design and implementation of Code Converters

Aim: To design and implement Code Converters using logic gates
i. Binary to Gray code converter
ii. Gray to Binary code converter
iii. BCD to Excess 3 code converter
iv. Excess 3 to BCD code converters

Equipment and Components Required:

SL.No Equipment/Components Range Quantity
1 IC TRAINER KIT - 1
2 PATCH CORDS - 15
3 AND GATE IC 7408 1
4 OR GATE IC7432 1
5 NOT GATE IC 7404 1
6 X-OR GATE IC 7486 1

Theory:
The availability of large variety of codes for the same discrete elements of information results
in the use of different codes by different systems. A conversion circuit must be inserted between the two
systems if each uses different codes for same information. Thus, code converter is a circuit that makes
the two systems compatible even though each uses different binary code.

Gray code is a non-weighted code. The input variable are designated as B3, B2, B1, B0 and the
output variables are designated as G3, G2, G1, G0. From the truth table, combinational circuit is
designed. The Boolean functions are obtained from K-Map for each output variable.

To convert from binary code to Excess-3 code, the input lines must supply the bit combination
of elements as specified by code and the output lines generate the correspondingbit combination of
code. Each one of the four maps represents one of the four outputs of the circuit as a function of the four
input variables

A two-level logic diagram may be obtained directly from the Boolean expressions derived by
the maps. These are various other possibilities for a logic diagram that implements this circuit. Now the
OR gate whose output is C+D has been used to implement partially each of three outputs.
 Binary to gray code converter:

Here the input is binary code and the output obtained is gray code. The reflected binary code, also
known as Gray code after Frank Gray, is a binary numeral system where two successive values differ in only
one bit. The design steps are first truth table is given, secondly the K map simplification for thetruth table is
done. Thirdly the logic diagram for the equations is drawn. Gray code differs from binary code as bit patterns
change “10” changed to “11” and “11” changed to “10”.

Practical application:

• Towers of Hanoi
• Due to the Hamming distance properties of Gray codes, they are sometimes used in Genetic
Algorithms
• Gray codes are also used in labeling the axes of Karnaugh maps
• When Gray codes are used in computers to address program memory, the computer uses lesspower
because fewer address lines change as the program counter advances.
• Gray codes are widely used to facilitate error correction in digital communications such as
digital terrestrial television and some cable TV systems
• It is used to indicate angular position of shaft on rotating machinery such as automated lathesand
drill presses.
• Communication between clock domains
• Gray code counters and arithmetic
 Gray code to binary converter :

BINARY code is a way of representing the text or the data generated by the computers and other
devices. Today's digital computer works on discontinuous data i.e. data is not flowing continuously thus it
uses binary code 0(off) and one (on) to indicate when there is a flow and when there is not. In binary coding
the text or the data is represented in a stream of bits of 1's and 0's .Here the input is Gray code and the output
obtained is binary code. The design steps are first truth table is given, secondly the K map simplification for
the truth table is done. Thirdly the logic diagram for the equations is drawn. Gray code differs from binary
code as bit patterns change “10” changed to “11” and “11” changed to “10”.

BCD to Excess-3 converter:

BCD codes:
In computing and electronic systems, binary-coded decimal (BCD) (sometimes called natural
binary-coded decimal, NBCD) or, in its most common modern implementation, packed decimal, is an
encoding for decimal numbers in which each digit is represented by its own binary sequence.

Applications of BCD codes:

• BCD codes allows easy conversion to decimal digits for printing or display, and allows faster decimal
calculations. Its drawbacks are a small increase in the complexity of circuits needed toimplement
mathematical operations
• The BIOS in many personal computers stores the date and time in BCD because the MC6818 real-
time clock chip used in the original IBM PC AT motherboard provided the time encoded inBCD. This
form is easily converted into ASCII for display.

Excess- 3codes:

Excess-3 binary-coded decimal (XS-3) or Stibitz code, also called biased representation or Excess-
N, is a complementary BCD code and numeral system. Excess-3 was used on some older computers as well
as in cash registers and hand held portable electronic calculators of the 1970's, among other uses. It is a way
to represent values with a balanced number of positive and negative numbers using a pre-specified number
N as a biasing value. The primary advantage of XS-3 coding over BCD coding is that a decimal number can
be nines' complemented (for subtraction) as easily as abinary number can be ones' complemented; just invert
all bits.
Applications of EXCESS- 3 codes:

• Excess-3 was used on some older computers as well as in cash registers and hand held
portable electronic calculators of the 1970's, among other uses.

• One very basic use of the Excess3 code is that you can easily compute subtractions involving 9.All
you have to do is invert the bits.

BCD to Excess – 3 convertor:

It is a non-weighted code. In XS-3, numbers are represented as decimal digits, and each digit is
represented by four bits as the digit value plus 3 (the "excess" amount) Here the input is BCD input and the
output obtained is Excess-3 output. One very basic use of the Excess3 code is that you can easily compute
subtractions involving 9; all you have to do is invert the bits. For example, the Excess3code for 5 is 1000.
Suppose you have to find out 9 - 5. The answer should be 4. To execute the subtraction in Excess3, all you
need to do is invert the bits of the Excess3 code for 5. The answer will be 0111 which is the Excess3 code of
4.

Excess-3 to BCD converter:

Here the input is obtained is Excess-3 and output is BCD code. Excess 3 codes are generated by
adding three to binary value. For Example, excess 3 values for 0 is 3, i.e. 0+3 is 3.

Experiment Procedure:

• IC is placed in the slot provided on the IC trainer kit.

• IC should be placed on the slot with notch on the topside of the slot.
• The left side of the notch is pin no.1 and sequentially it goes.
• 7th pin is connected to ground and 14th pin to VCC on the kit.
• For input connection, a wire is connected between the input terminal and switch.
• For output connection, a wire is connected between the output terminal and LED.
• Connections are given as per the logic Diagram.
• Power supply is switched on. Input switch positions are changed as per the truth table and output
are verified.
Binary to gray code converter:

Truth table:

Binary input Gray code output

B3 B2 B1 B0 G3 G2 G1 G0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0
1 1 0 1 1 0 1 1
1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0
 K-map Simplification:

K-Map for G3: K-Map for G2:

G3 = B 3

K-Map for G1 K-Map for G0

Logic diagram

:
Gray code to binary code converter:
Truth table:

Gray Code Binary Code

G3 G2 G1 G0 B3 B2 B1 B0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 1 0 0 1 0
0 0 1 0 0 0 1 1
0 1 1 0 0 1 0 0
0 1 1 1 0 1 0 1
0 1 0 1 0 1 1 0
0 1 0 0 0 1 1 1
1 1 0 0 1 0 0 0
1 1 0 1 1 0 0 1
1 1 1 1 1 0 1 0
1 1 1 0 1 0 1 1
1 0 1 0 1 1 0 0
1 0 1 1 1 1 0 1
1 0 0 1 1 1 1 0
1 0 0 0 1 1 1 1
K-map Simplification:

K-Map for B3: K-Map for B2:

B3 = G3

K-Map for B1: K-Map for B0:

Logic Diagram:
BCD to Excess 3 code converters:
Truth table:

BCD input Excess – 3 outputs

B3 B2 B1 B0 E3 E2 E1 E0
0 0 0 0 0 1 1
0 0 0 1 0 1 0 0
0 0 1 0 0 1 0 1
0 0 1 1 0 1 1 0
0 1 0 0 0 1 1 1
0 1 0 1 1 0 0 0
0 1 1 0 1 0 0 1
0 1 1 1 1 0 1 0
1 0 0 0 1 0 1 1
1 0 0 1 1 1 0 0
1 0 1 0 x x x x
1 0 1 1 x x x x
1 1 0 0 x x x x
1 1 0 1 x x x x
1 1 1 0 x x x x
1 1 1 1 x x x x
 K-map Simplification:

K-Map for E3: K-Map for E2:

E3 = B3 + B2 (B0 + B1)

K-Map for E1: K-Map for E0:

Logic diagram:

Excess 3 to BCD code converter:

Truth table:
Result:

Thus the code converters were designed and their truth table were verified.
Experiment No: 2c
Date: ……. /……. /……………

Design of 4-bit binary adder/subtractor and BCDAdder

Aim: To design and implement 4-bit adder /subtractor and BCD Adder
using IC 7483.

Equipment and Components Required:

SL.No Equipment/Components Range Quantity
1 IC TRAINER KIT - 1
2 PATCH CORDS - 15
3 AND GATE IC 7408 1
4 OR GATE IC7432 1
5 4 BIT FULL ADDER IC 7483 2
6 X-OR GATE IC 7486 1
Theory:

4 – Bit adder/subtractor:

The addition and subtraction operation can be combined into one circuit with one common
binary adder. The mode input M controls the operation. When M=0, the circuit is adder circuit.
When M=1, it becomes subtractor.

BCD Adder:

Computers or calculators that perform arithmetic operations directly in the decimal number
system represent decimal numbers in binary – coded form. A BCD adder is a circuitthat adds two
BCD digits in parallel and produces a sum digit in BCD and a carry. BCDadder must include
correction logic in its internal construction. A BCD digit can have any of the ten possible four-bit
binary representations, that is, 0000, 0001, , 1001, the equivalent
of decimal numbers 0, 1, , 9. When we set out to add two BCD digits and we assume that
there is an input carry too, the highest binary number that we can get is the equivalent of decimal
number 19 (9+9+1).

Steps for BCD Addition:

• Add the two BCD numbers, using the rules for binary addition
• If a 4-bit sum is equal to or less than 9, it is a valid BCD number.
• If a 4-bit sum is greater than 9, or if a carry out of the 4-bit group is generated, it is an
invalid result. Add 6 (0110) to the 4-bit sum in order to skip the six invalid states and
return the code to 8421. If a carry results when 6 is added, simply add the carry to the
next 4-bit group.
Working principle:

4- bit parallel adder/ subtractor:

• The circuit performs addition as well as subtraction .When‘s’ input is low the circuit
performs addition.
• The EX-OR gate acts as a controlled inverter (i.e., it inverts input when control is
high; otherwise it passes the input to the output).
• The output of EX-OR gate is same as the ‘Y’ input When‘s’ input is low.
• The output of the circuit is sum of two input numbers when‘s’ input is low.
• When‘s’ input is HIGH the EX-OR gate acts as inverter and its output is the complement
of input.
• The carry input of the first full adder is ‘1’.The output of the circuit is the sum A,
complement of B and 1.
• This performs 2’s complement subtraction .The output of the circuit is in true magnitude
form if the A>B .The output of the circuit is in 2’scomplement form if the A<B.
Working principle: BCD Adder:
• The two decimal digits, together with the input carry, are first added in the top 4-bitadder
to produce the binary sum.
• When the output carry is equal to zero, nothing is added to the binary sum.
• When it is equal to 1, binary 0110 is added to the binary sum through the bottom4-bit
adder.
• A decimal parallel adder that adds n decimal digits needs n BCD adder stages.
• The output carry from one stage must be connected to the input carry of the next
higher-order stage.

Experiment Procedure for 4 – bit binary adder/subtractor:

• The connection is given as per the circuit diagram.

• Power supply is switched ON
• If the control pin M = 0, it performs addition process. The two 4 bit input data’s are
given and the truth table is verified.
• If the control input M = 1, it performs subtraction process. The two 4 bit input dataare
given and the truth table is verified.

Experiment Procedure for BCD Adder:

• The connection is given as per the circuit diagram.

• Power supply is switched ON
• Logic inputs are given and output is verified.
5- Binary adder/subtractor:

Pin diagram for IC7483

Logic diagram:
Truth Table of 4 – bit adder/subtractor:
BCD Adder:

Logic diagram:

Truth Table for BCD Adder:

SL.NO A4 A3 A2 A1 B4 B3 B2 B1 C S4 S3 S2 S1
1 0 0 0 1 0 0 1 0 0 0 0 1 1

2 0 1 1 0 1 0 0 0 1 0 1 0 0

3 1 0 0 1 1 0 1 0 1 1 0 0 1
Result:

Thus the 4 bit parallel adder/Subtractor, BCD Adder circuits were designed and
their function tables were verified.
Experiment No: 3
Date: ……. /……. /……………

Design and implementation of Multiplexer and

Demultiplexers

Aim: To design and implement 4:1Multiplexer and 1:4 Demultiplexer circuits using
logic gates.

Equipment and Components Required:

SL.No Equipment/Components Range Quantity
1 IC TRAINER KIT - 1
2 PATCH CORDS - 15
3 AND GATE-3 Input IC 7411 2
4 OR GATE IC7432 1
5 NOT GATE IC 7404 1

Theory:

Digital computers process and transfer a tremendous amount of digital signals. It would be
prohibitive to make separate straight – wire connections for the transfer of all the data within the
computer or to a peripheral device. With a procedure called multiplexing, onewire is used to replace
many wires for transferring signals between multiple sources. Multiplexing and demultiplexing are
used to perform multiplexing. One of the first applications of multiplexing was the transmission of
telephone signals. This method enabled several telephone conversations to be sent simultaneously
over the same wire.

In electronics, a multiplexer or mux or data selector is a device that selects one of several
analog or digital input signals and forwards the selected input into a single line. A multiplexer of 2 n
inputs has n select lines, which are used to select which input line to send to the output. An electronic
multiplexer can be considered as a multiple-input, single-output switch i.e. digitally controlled multi-
position switch. The digital code applied at the select inputs determines which data inputs will be
switched to output.

Demultiplexer (or demux) or data distributor is a device taking a single input signal and
selecting one of many data-output-lines, which is connected to the single input. A multiplexer is
often used with a complementary demultiplexer on the receiving end. A demultiplexer is a single-
input, multiple-output switch. Demultiplexer is logic circuit that receives information on a single
input and transmits the same information over one of several (2n) output lines. Demultiplexers
take one data input and a number of selection inputs, and they have several outputs. They forward
the data input to one of the outputs depending on the values of the selection inputs.
Working principle of 4:1multiplexer:

Timing Diagram for 4:1 Multiplexer

• A multiplexer of 2n inputs has n select lines, which are used to select which input line
to send to the output.
• A selector chooses a single data input and passes it to the MUX output
• Multiplexer has one output selected at a time.
• 4:1 multiplexer has 4 i/p lines, one output line and 2 select lines.
• 2 select lines can have four combinations.
• If the select lines AB =00 then i0 is selected
• If the select lines AB =01 then i1 is selected
• If the select lines AB =10 then i2 is selected
• If the select lines AB =11 then i3 is selected

Working principle of 1:4 demultiplexer :

 Timing diagram of 4:1 demultiplexer

• A DEMUX is a digital switch with a single input (source) and a multiple

outputs(destinations).
• The select lines determine which output the input is connected to.
• 1:4 demultiplexers have single input line, 4 output lines and 2 select lines.
• If the select lines AB=00, then output w is connected to input.
• If the select lines AB=01, then output x is connected to input.
• If the select lines AB=10, then output y is connected to input.
• If the select lines AB=11, then output z is connected to input.
• Thus depending on the select lines output line is selected.
Experiment Procedure:

• IC is placed in the slot provided on the IC trainer kit.

• IC should be placed on the slot with notch on the topside of the slot.
• The left side of the notch is pin no.1 and sequentially it goes.
• 7th pin is connected to ground and 14th pin to VCC on the kit.
• For input connection, a wire is connected between the input terminal and switch.
• For output connection, a wire is connected between the output terminal and LED.
• Connections are given as per the logic Diagram.
• Power supply is switched on. Input switch positions are changed as per the truth table and
output are verified.
 Multiplexer:

Block diagram for 4:1 multiplexer

Function Table:

Selection line Values Output

S1 S0 Y
0 0 D0
0 1 D1
1 0 D2
1 1 D3
Y=D0S1’S0’+D1S1’S0+D2S1S0’+D3S1S0
Logic diagram for multiplexer:
De-multiplexer:

Block Diagram - 1:4 Demultiplexer:

Function table:
Selection line Values Output

S1 S0 D0 D1 D2 D3
0 0 I/P 0 0 0
0 1 0 I/P 0 0
1 0 0 0 I/P 0
1 1 0 0 0 I/P
Pin diagram of IC 7411

Logic Diagram for Demultiplexer:

Result:

Thus 4:1 Multiplexer and 1:4 Demultiplexer were designed and their function tables were verified.
Experiment No: 4
Date: ……. /……. /……………

Design and Implementation of Encoder and Decoder

Aim: To design and implement Encoder and Decoder combinational circuits

usinglogic gates.

Equipment and Components Required:

SL.No Equipment/Components Range Quantity
1 IC TRAINER KIT - 1
2 PATCH CORDS - 15
3 AND GATE- 3 inputs IC 7411 2
4 OR GATE IC7432 2
5 NOT GATE IC 7404 1

Theory:
In digital electronic projects, the encoder and decoder play an important role. It is used to convert the data
from one form to another form. Generally, these are frequently used in the communication systems like
telecommunication, networking, and transfer the data from one end to the other end. In the same way, it
is also used in the digital domain for easy transmission of data, placed with the codes, and then transmitted.
At the end of the receiver, the coded data are collected from the code and then processed to display.
An encoder in digital electronics is a one-hot to binary converter. That is, if there are 2n input lines, and
at most only one of them will ever be high, the binary code of this 'hot' line is produced on the n-bit
output lines. A binary encoder is the dual of a binary decoder.
For example, a 4-to-2 simple encoder takes 4 input bits and produces 2 output bits.
A decoder is a multiple-input, multiple-output combinational logic circuit..Decoder is a combinational
circuit that has 'n' input lines and maximum of 2n output lines. One of these outputs will be active
High based on the combination of inputs present, when the decoder is enabled. That means decoder
detects a particular code.
Experiment Procedure:

• IC is placed in the slot provided on the IC trainer kit.

• IC should be placed on the slot with notch on the topside of the slot.
• The left side of the notch is pin no.1 and sequentially it goes.
• 7th pin is connected to ground and 14th pin to VCC on the kit.
• For input connection, a wire is connected between the input terminal and switch.
• For output connection, a wire is connected between the output terminal and LED.
• Connections are given as per the logic Diagram.
• Power supply is switched on. Input switch positions are changed as per the truth table and
outputs are verified.
Encoder:

Octal to Binary Encoder:

8:3

Truth Table:
Inputs Outputs
Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 A2 A1 A0
1 0 0 0 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 1 0
0 0 0 1 0 0 0 0 0 1 1
0 0 0 0 1 0 0 0 1 0 0
0 0 0 0 0 1 0 0 1 0 1
0 0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 0 1 1 1 1

Pin Diagram of IC7411:

Logic Circuit:

Decoder:
Block diagram:

2 to 4 Decoder:
Truth Table:

Inputs outputs
Enable(E) A B Y0 Y1 Y2 Y3
0 X X 0 0 0 0
1 0 0 1 0 0 0
1 0 1 0 1 0 0
1 1 0 0 0 1 0
1 1 I 0 0 0 1

Logic Circuit:
Result:

Thus Encoder and Decoder combinational circuits were designed and their truth table were verified.
Experiment No:54 c
Experiment No:
Date:…….
Date: /…….
……. /……. /………… …
/……………

Design of Magnitude Comparator

Aim: To design and implement

• 2 bit magnitude comparator using logic gates
• 4-bit magnitude comparator using IC7485.

Equipment and Components Required:

SL.No Equipment/Components Range Quantity
1 IC TRAINER KIT - 1
2 PATCH CORDS - 15
3 AND GATE- 3 inputs IC 7411 2
4 OR GATE IC7432 2
5 NOT GATE IC 7404 1
6 EX-OR GATE IC 7486 1
7 4 Bit Magnitude IC 7485 2
Comparator

Theory:

Comparator is a basic and useful arithmetic component in the VLSI Design,

which detects whether one input is equal to or greater than or less than the other input. A 64-
bit microprocessor requires a 40- bit tag comparator due to 50-bit physical address, which
has been increasing every generation. An individual, high-performance, 128-bit hardware
comparator core plays an important role on many computing applications. For example, each
equipment on the internet, such as computer cell phone, must be allocatedan IP address in
order to communicate with other equipments.IPv6 implements a new addressing system
which uses 128 –bit address allowing 3.4x1038 addresses. Moreover, compare and swap
elements of data are vital for sorting .and hence comparator play an important role in
computer applications.

Working principle:

A magnitude comparator is a combinational circuit that compares two given

numbers (i.e., A & B) and determines whether one is equal to, less than or greater than the
other. The output is in the form of three binary variables representing the conditions A = B,
A>B and A<B. Depending upon the relative magnitude of these two numbers, the relevant
output will change state
 The 74F85 is a 4-bit magnitude comparator that can be expanded to almost any length. It
compares two 4-bit binary, BCD, or other monotonic codes and presents the three possible
magnitude results at the outputs. The 4-bit inputs are weighted (A0–A3) and (B0– B3) where
A3and B3 is the most significant bits. The operation of the74F85 is described in the Function
Table, showing all possible logic conditions.
H = High Voltage.
L= Low Voltage.
X= Don’t Cares.

The upper part of the table describes the normal operation under all conditions that will
occur in a single device or in a series expansion scheme. In the upper part of the table the three
outputs are mutually exclusive. In the lower part of the table, the outputs reflect the feed-forward
conditions that exist in the parallel expansion scheme.
The expansion inputs I A>B, and I A=B and I A<B are the least significant bit positions.
When used for series expansion, the A>B, A=B and A<B outputs of the lease significant word
are connected to the corresponding I A>B, I A=B and I A<B inputs of the next higher stage. Stages
can be added in this manner to any length, but a propagation delay penalty of about 15ns is
added with each additional stage.

Experiment Procedure:

• IC is placed in the slot provided on the IC trainer kit.

• IC should be placed on the slot with notch on the topside of the slot.
• The left side of the notch is pin no.1 and sequentially it goes.
• 8th pin is connected to ground and 16th pin to VCC on the kit.
• For input connection, a wire is connected between the input terminal and switch.
• For output connection, a wire is connected between the output terminal and LED.
• Connections are given as per the logic Diagram.
• Power supply is switched on. Input switch positions are changed as per the truth table and
output are verified.
 2 Bit Magnitude Comparator:

Truth Table:
( A=B) = E = (A0 EX-NOR B0) (A1 XE-NOR B1)
Logic Circuit:

Pin diagram o f IC7485:

 4-bit magnitude comparator using IC7485:
Logic diagram:

Truth Table:
Observation table:

Cascading Inputs Input A Input B Output

I(A<B) I(A>B) I(A =B) A3 A2 A1 A0 B3 B2 B1 B0 A>B A<B A=B

0 0 1 1 0 0 0 0 0 1 1 1 0 0

0 0 1 0 1 0 1 1 1 0 0 0 1 0

0 0 1 1 0 0 1 1 0 0 1 0 0 1
Result:

Thus the magnitude comparator was designed and truth table was verified.
 Experiment No: 6a
Date: ……. /……. /……………

Design and Implementation of SynchronousCounters

Aim: To design and implement
3 bit synchronous u p counters.
3 bit synchronous u p do w n counters
3 bit synchronous u p/ down counters

Equipment and Components Required:

SL.No Equipment/Components Range Quantity

1 IC TRAINER KIT - 1
2 PATCH CORDS - 15
3 JK FLIPFLOP IC7476 2
4 AND GATE IC 7408 2
5 OR GATE IC7432 2
6 NOT GATE IC 7404 1

Theory:

A counter is a register capable of counting number of clock pulse arriving at its clockinput.
Counter represents the number of clock pulses arrived. A specified sequence ofstates appears as
counter output. This is the main difference between a register and a counter. There are two types
of counter, synchronous and asynchronous.
In synchronous common clock is given to all flip flop and in asynchronous first flip flop is
clocked by external pulse and then each successive flip flop is clocked by Q or Q output of previous
stage. A soon the clock of second stage is triggered by output of first stage.

An up/down counter is one that is capable of progressing in increasing order or decreasing

order through a certain sequence. An up/down counter is also calledbidirectional counter. Usually
up/down operation of the counter is controlled by up/down signal. When this signal is high counter
goes through up sequence and when up/down signal is low counter follows reverse sequence.
Because of inherent propagation delay time all flip flops are not activated at same time
which results in asynchronous operation.
 Bidirectional counters, also known as Up/Down counters, are capable of counting ineither
direction through any given count sequence and they can be reversed at any point within their
count sequence by using an additional control input.

Working Principle:

3 Bit Synchronous Up/Down Counter:

The circuit is of a simple 3-bit Up/Down synchronous counter using JK flip-flops

configured to operate as delay or D-type flip-flops giving a maximum count of zero (000) to
seven (111) and back to zero again. Then the 3-Bit counter advances upward in sequence
(0,1,2,3,4,5,6,7) or downwards in reverse sequence (7,6,5,4,3,2,1,0) but generally, bidirectional
counters can be made to change their count direction at any point in the counting sequence. An
additional input determines the direction of the count, either up or down and the timing diagram
gives an example of the counters operation as this Up/Down input changes state.

Experiment Procedure:

• IC is placed in the slot provided on the IC trainer kit.

• IC should be placed on the slot with notch on the topside of the slot.
• The left side of the notch is pin no.1 and sequentially it goes.
• 13th pin is connected to ground and 5th pin to VCC on the kit.
• For input connection, a wire is connected between the input terminal and switch.
• For output connection, a wire is connected between the output terminal and LED.
• Connections are given as per the logic Diagram.
• Power supply is switched on. Clock pulse is applied and output is verified.
3 Bit Synchronous Up Counter:

State Diagram: Excitation Table:

IC 7476 (JK Flip Flop) Pin Diagram:

 Logic Diagram:

Truth Table:

Clock
Pulse Q1 Q2 Q3
(CP)
0
0 0 0
1
1 0 0
0
2 0 1
1
3 0 1
0
4 1 0
1
5 1 0
6 1 1 0

7 1 1 1

8 0 0 0
3 Bit Synchronous down Counter:

Logic Circuit:
Truth Table:

Clock
Pulse Q1 Q2 Q3
(CP)
0
0 0 0
1
1 1 1
0
2 1 1
1
3 1 0
0
4 1 0
1
5 0 1
0
6 0 1
1
7 0 0
0
8 0 0

3 bit Synchronous Up/Down counter:

Result:

Thus 3 Bit Synchronous Counter was designed and the truth table was verified.
 Experiment No: 6B
Date: ……. /……. /……………

Design and Implementation of AsynchronousCounters

Aim: To design and implement
• 3 bit Asynchronous u p counters.
• 3 bit Asynchronous u p do w n counters
• 3 bit Asynchronous u p/ do wn counters
• MOD 10 Cou n t e r

Equipment and Components Required:

SL.No Equipment/Components Range Quantity

1 IC TRAINER KIT - 1
2 PATCH CORDS - 15
3 JK FLIPFLOP IC7476 2
4 AND GATE IC 7408 2
5 OR GATE IC7432 2
6 NOT GATE IC 7404 1
7 NAND GATE IC7400 1

Theory:

A ripple counter is an asynchronous counter where only the first flip-flop is clockedby an
external clock. All subsequent flip-flops are clocked by the output of the preceding flip-flop.
Asynchronous counters are also called ripple-counters because of the way the clock pulse ripples
it way through the flip-flops.
The MOD of the ripple counter or asynchronous counter is 2n if n flip-flops are used. For
a 4-bit counter, the range of the count is 0000 to 1111 (24-1). A counter may count upor count
down or count up and down depending on the input control. The count sequence usually repeats
itself. When counting up, the count sequence goes from 0000, 0001, 0010, ...1110 , 1111 , 0000,
0001, ... etc. When counting down the count sequence goes in the opposite manner: 1111, 1110,
... 0010, 0001, 0000, 1111, 1110, ... etc.
The complement of the count sequence counts in reverse direction. If the
uncomplemented output counts up, the complemented output counts down. If the uncomplemented
output counts down, the complemented output counts up.
There are many ways to implement the ripple counter depending on thecharacteristics of
the flip flops used and the requirements of the count sequence.
 • Clock Trigger: Positive edged or Negative edged
• JK or D flip-flops
• Count Direction: Up, Down, or Up/Down

Experiment Procedure:

• IC is placed in the slot provided on the IC trainer kit.

• IC should be placed on the slot with notch on the topside of the slot.
• The left side of the notch is pin no.1 and sequentially it goes.
• 13th pin is connected to ground and 5th pin to VCC on the kit.
• For input connection, a wire is connected between the input terminal and switch.
• For output connection, a wire is connected between the output terminal and LED.
• Connections are given as per the logic Diagram.
• Power supply is switched on. Clock pulse is applied and output is verified.
IC 7476 Pin Diagram:

3 bit Asynchronous up counter:

Truth Table:

Clock
Pulse Q2 Q1 Q0
(CP)
0
0 0 0
1
1 0 0
0
2 0 1
1
3 0 1
0
4 1 0
1
5 1 0
0
6 1 1
1
7 1 1
0
8 0 0

3 Bit Asynchronous down counter:

Truth Table:

Clock
Pulse Q2 Q1 Q0
(CP)
0
0 0 0
1
1 1 1
0
2 1 1
1
3 1 0
0
4 1 0
1
5 0 1
0
6 0 1
1
7 0 0
0
8 0 0

3 Bit Asynchronous Up/Down Counter:

MOD – 10 Asynchronous up counter:

Logic diagram:

Truth table:
Result:

Thus Asynchronous Counter was designed and truth table was verified.
Experiment No: 7
Date: ……. /……. /……………

Design and Implementation of Shift Registers

Aim:
To design, implement and verify the functioning of shift right registers
using D flip-flop.
Equipment and Components Required:

SL.No Equipment/Components Range Quantity

1 IC TRAINER KIT - 1
2 PATCH CORDS -
3 D FLIP FLOP IC7474 2
4 AND GATE IC 7408 2
5 OR GATE IC7432 2
6 NOT GATE IC 7404 1

Theory:
A register that is used to store binary information is known as a memory register.
A register capable of shifting binary information either to the right or the left is called a
shift register. Shift registers are classified into four types,
1. Serial-in Serial-out (SISO)
2. Serial-in Parallel-out (SIPO)
3. Parallel-in Serial-out (PISO)
4. Parallel-in Parallel-out (PIPO)
Serial-in Serial-out (SISO):
This type of shift registers accepts data serially, i.e., one bit at a time on a single
input line. It produces the stored information on its single output and the output also in
serial form. Data may be shifted left (from low to high order bits) using shift-left register
or shifted right (from high to low order bits) using shift-right register.
Serial-in Parallel-out (SIPO):
It consists of one serial input, and outputs are taken from all the flip-flop
simultaneously in parallel. In this register, data is shifted in serially but shifted out in
parallel. In order to shift the data out in parallel, it is necessary to have all the data available
at the outputs at the same time. Once the data is stored, each bit appears on its respective
output line and all the bits are available simultaneously, rather than on a bit by bit basis as
with the serial output
Parallel-in Serial-out (PISO):
This type of shift register accepts data parallel, i.e., the bits are entered
simultaneously into their respective flip-flops rather than a bit-by-bit basis on one line.

Parallel-in Parallel-out (PIPO):

In this type of register, data inputs can be shifted either in or out of the registerin
parallel.
Procedure:
1. Connections are made as per the circuit/logic diagram.
2. The ICs are enabled by giving the suitable Vcc and groundconnections.
3. Logic inputs and clock pulse are applied to the appropriate terminals of the ICs.
4. Output are verified for different inputs.
Pin Diagram:

Circuit Diagram: Serial IN Serial OUT shift Register

Circuit Diagram: Serial in Parallel out shift Register
Circuit Diagram: Parallel-in Serial-out shift Register

Circuit Diagram: Parallel -in Parallel -out shift Register

Verification Table:

Serial In Serial Out Shift Register:

Serial Input
CLK Serial Output

1 1 0

2 0 0

3 0 0

4 1 1

5 X 0

6 X 0

7 X 1

Serial In Parallel Out Shift Register:

DATA OUTPUT
CLK
QA QB QC QD
1 1 1 0 0 0

2 0 0 1 0 0

3 0 0 0 1 1

4 1 1 0 0 1

Parallel In Serial Out Shift Register:

CLK Q3 Q2 Q1 Q0 OUTPUT

0 1 0 0 1 1

1 0 0 0 0 0

2 0 0 0 0 0

3 0 0 0 0 1
Parallel In Parallel Out Shift Register:

CLK DATA INPUT OUTPUT

DA DB DC DD QA QB QC QD
1 1 0 0 1 1 0 0 1

2 1 0 1 0 1 0 1 0
Result:

Thus Shift registers are designed and their functions were verified.