MODULE 1

1. Define negative logic and Write the equivalent negative logic for positive NAND
gate.
2. Implement the Boolean function F = yz + z'y'+ x'z With NAND and inverter gates.
3. Simplify the following using K-Map technique and find the Essential Prime
Implicants.

(i)P= f (w, x, y, z) = ∑(7,9,12,13,14,15) + Σd(4,11)

(ii)Y = f(a,b,c,d) = (0,1,2,6,7,9,10,12)+d(3,5). Verify the result using K-map.

(iii) f (A, B, C, D) = 6. Describe the three bus organization of the datapath and describe
in detail. 7. Describe how an ALU perform on arithmetic and logic operation along
with input gating diagrams. (0,1,2,3,10,11,12,13,14,15)

(iv) f (W,X,Y,Z) = ∑(1,3,6,7,8,9,10,12,13,14)

4.. Simplify the following expressions using Karnaugh map.

Implement the simplified circuit using the gates as indicated:

(i) f (w, x, y, z) = m(1,5,7,9,10,13,15)+d(8,11,14) using NAND gates.

(ii) f (A, B, C, D) = пм (0,1,2,4,5,6,8,9,12,13,14) using NOR gates.

5. Express the function F=x+yz as the sum of its minterms and product of maxterms.

6. Obtain a minimum product of sums with a Karnaugh map.

F(w, x, y, z) = x'z' + wyz + w' y z + xy.

7. Write the verilog code for the given expression using dataflow and behavioral model
where Y=(AB' + A'B) (CB + AD) (AB'C + AC).

8***.What are universal gates why are they called so ,also write the rule of a obtaining
the a) NAND logic

b) NOR logic [implement from a Boolean function

9**.State and prove DeMorgains therom

10**.Simplify the problems on Boolean function using Karnaugh map(k map)

Like a) F(A,B,C,D) = ∑m(3,7,11,13,14,15)

b)F(x,y,z) = ∑m(0,1,4,5,6)+d(2,5,7)

11**.Explain don’t care condition with an example .

12**.Explain map method (k map method).

13** what are the types of digital logic gated explain with truth table.
14** Verilog module of a simple circuit
 MODULE 2

1. What is Latch? With neat diagram, explain S-R latch using NOR gate. Derive
characteristics equation.

2. What is priority encoder? Design 4:2 priority encoder with necessary diagrams.

3. Design and explain four bit adder with carry look ahead.Distinguish Between
Combinational and sequential circuits.

4. What is multiplexer? Design 8:1 mux using 2:1 mux.

5. Implement full adder circuit using 3:8 decoders.

6. With Truth table and K-map simplification, implement the full adder with basic gates
and using two half adders an OR gate.

7. Obtain the characteristic equation of SR, JK, D and T flip flops.

8. Explain the structure of VHDL and verilog program. Write Verilog code for 4 bit parallel
adder using full adder as component.

9** what is multiplexer .explain 8 to 1 multiplexer with the help of logic diagram and
corresponding expression.

10** Explain seven (7) segment decoder and realize using PLA

11**Implement full subtracter suing 3 to 8 decoder and NAND gates

12** what are hazards in digital circuits explain different types of hazards

13**** vimp .Derive the characteristic equation for SR flip flop and JK flip flop in product
of sum form(all read all types of flip flops)[with logic diagram].

14** Distinguish between combinational and sequential circuits

15* Difference between PLA and PAL.

16** Explain the working od SR latch using NOR gate Verilog HDL code for 4:1
multiplexer(design and implement).
 MODULE 3

1. Explain four types of operation performed by computer with an example.

2. What is addressing mode? Explain different types of addressing mode with an

examples.

3. With a neat diagram, explain basic operational concepts of a computer.

4. Write a note on:

i) Register Transfer Notation (RTN)

ii) Assembly Language Notation.

5. What is performance measurement? Explain the overall SPEC rating for a computer in
a program suite.

6. Write the difference b/w RISC and CISC processors.

7. How input and output operation performed by Processor?

8. Derive the basic performance equation? Discuss the performance. measures to

improve the performance.

9***. Define addressing modes. Explain any five types of addressing modes with
example

10**. With a neat diagram analyze the basic operations concept of a computer give the
operating steps.

11***.How to measure the performance of a computer explain the overall SPEC rating of
a computer.

12***.Define subroutine and parameter passing . expalin how to pass the parameter by
value and by reference.

13***. With proper example explain big-endian anf little endian of byte addressing .

14**.How the input and output operation are to be performed by the processor ? write a
program that read the line of character and display it.

15**.Write a basic performance equation indicate the role of each parameter in the
equation.
 MODULE 4

1. Explain the following with respect to interrupts with diagram.

i) Vector interrupt

ii) Interrupt nesting

iii) Simultaneous request.

2. Explain Direct Memory Access with a neat diagram.

3. What is Bus arbitration? Explain different types of bus arbitration.

4. Explain Hardware interrupt, enabling/disabling of interrupts and sequence of events

in handling interrupt request from a single device.

5. Explain memory mapped 1/0 and 1/0 interface for an input device with a diagram.

6. Describe DMA with its register and controllers.Explain with a block diagram a general
8 bit parallel interface.

7. Explain different mapping functions used in cache memory.

8. Explain the effect of size, cost and speed in memory Hierarchy.

9**.Explain how the I/O devices should be organized in a priority structure

10***.With neat sketch, explain various methods for handling multiple interrupts
request raised by multiple devices.

11***vimp. With a neat diagram, explain centralized bus arbitration and distributed bus
arbitration.

12***.Explain the I/O interface for a input device to the processor with a neat block
diagram

13***vimp.State the importance of a cache memory and describe types of a cache

mapping techniques with diagram.

14**vimp.Explain the different mapping function used in a cache memory

15**.what is direct memory access when it is used? Explain it with block diagram.

16**.Draw a neat block diagram of memory hierarchy in computer system. Discuss the

Variation of size, speed, and cost per bit in the hierarchy.

 MODULE 5

1.. Draw and explain the single-bus organization of the data path inside processor.

2. List out the actions needed to execute the instruction ADD (R3), R1

write and explain the sequence of control steps for the execution of the same.

3. Analyze how does execution of a complete instruction carry out. Discuss with neat
diagram I/O interface for an input device.

4. What is pipeline? Explain the performance of pipeline with an example.

5. Explain the process of Fetching word from memory in processor. Explain the role of
cache memory in pipelining.

6. Describe the three bus organization of the datapath and describe in detail.

7. Describe how an ALU perform on arithmetic and logic operation along with input
gating diagrams.

8***vimp. Explain the operations of a 4-stage pipeline.

9***.Write and explain the control sequence for execution of the instruction(R3),R1,.

10**.With suitable example explian the concept of pipeline processing.

11**.Draw and explain pipe lie for floating point addition and subtraction.

12**.Write and explain the control sequence for execution of an unconditional branch
instruction.

13**.Describe the process of performing Arthematic and logic unit(ALU) operation

within a basic processing unit.

14**.Discuss the procedures involved in the storing a word in a memory with in a basic
processing unit.

15***.Define cache memory and explain its role in computer system.