1. Which of the following is an example of a spooled device?

A. A line printer used to print the output of a number of jobs

B. A terminal used to enter input data to a running program
C. A secondary storage device in a virtual memory system
D. A graphic display device
Correct Option: A

2. When a CPU is interrupted, it

A. stops execution of instructions
B. acknowledges interrupt and branches to a subroutine
C. acknowledges interrupt and continues
D. acknowledges interrupt and waits for the next instruction from the interrupting device
Correct Option: B

3. A microprocessor, on arrival of RESET signal returns, from HALT state to

A. execute B. fetch
C. interrupt D. none of these
Correct Option: B

4. The frequency of the driving network connected between pin 1 and 2 of a 8085 chip must be
A. twice of the desired clock frequency B. equal to the desired clock frequency
C. four times the desired clock frequency D. none of these
Correct Option: A

5. A microprocessor with a 12– bit address bus will be able to access

A. 1 kilobyte of memory B. 4 kilobytes of memory
C. 8 kilobytes of memory D. 0.4 kilobytes of memory
Correct Option: A

6. Intel 8085A and 8086A differ in

A. number of address lines B. number of data lines
C. operating frequency D. all of these
Correct Option: D

7. Stack memory is used

A. to provide additional memory to the base memory
B. to save return addresses of a subroutine
C. to save the status of the microprocessor
D. none of these
Correct Option: B

8. Which of the following statements is not applicable to serial transmission of data?

A. One bit at a time B. Faster method of trans-mission
C. LSB transferred first D. Only one wire used
Correct Option: B
9. A microprocessor contains
A. most of the control and arithmetic logic functions of a computer
B. most of the RAM
C. most of the ROM
D. peripheral drivers
Correct Option: A

10. In microprocessor
A. program is stored in memory and data is stored in registers
B. program is stored in registers and data is stored in memory
C. both program and data are stored in memory
D. both program and data are stored in registers
Correct Option: A
1. Which one of the following statements regarding the INT (interrupt) and the BRQ (but request) pins in
a CPU is true?
A. The BRQ pin is sampled after every instruction cycle, but the INT is sampled after every machine cycle
B. Both INT and BRQ are sampled after every machine cycle
C. The INT pin is sampled after every instruction cycle, but the BRQ is sampled after every machine cycle
D. Both INT and BRQ are sampled after every instruction cycle
Correct Option: A

Interrupt is sampled after every machine cycle and Bus request pin is sampled after every instruction cycle.

2. An advantage of memory interfacing is that

A. a larger memory is obtained
B. effective speed of the memory is increased
C. the cost of the memory is reduced
D. a non-volatile memory is obtained
Correct Option: B

3. Return from a subroutine is affected by

A. a jump instruction B. an RST instruction
C. a RET instruction D. a hardware interrupt signal
Correct Option: C

4. The process of causing an unplanned branching operation to occur, usually initiated by external system
is called
A. debugging B. masking
C. interrupt D. iteration
Correct Option: C

5. WAIT states are used

A. to give slow devices additional time to put out valid data
B. to insert a deliberate delay
C. during I/O operation
D. none of these
Correct Option: A

6. Which of the following signal is used when a peripheral device request the microprocess to have a
DMA operation?
A. IO/ M B. READY
C. HOLD and HLDA D. RD and WR
Correct Option: C
1. In an 8085 A microprocessor based system, it is desired to increment the contents of memory location
whose address is available in (D,E) register pair and store the result in same location. The sequence of
instructions is
A. XCHG B. XCHG
INR M INX H
C. INX D D. INR M
XCHG XCHG
Correct Option: A

The address of the memory location is stored in DE register pair. But INR M command will increase the content of the
memory location M. But this command will execute only on HL pair. So we have to exchange the address of Memory
location in HL pair from DE pair first.

2. A software delay subroutine is written as given below:

How many times DCR L instruction will be executed?

A. 255 B. 510
C. 65025 D. 65279
Correct Option: A

DCRL will be executed 255 times till it content of L becomes zero.

Then, for every decrement of content of H, DCRL will again be executed by 256 times. (When L is decremented by 1
and becomes FFH). This will be repeated by 254 times.
Hence, no. of execution of DCRL = 254 × 256 + 255 = 65279

3. The contents (in Hexadecimal) of some of the memory locations in an 8085A based system are given
below:
 The contents of stack pointer (SP), program counter (PC) and (H, L) are 2700H, 2100H and 0000H
respectively. When the following sequence of instructions are executed
2100 H: DAD SP
2101 H: PCHL
the contents of (SP) and (PC) at the end of execution will be
A. (PC) = 2102H, (SP) = 2700H B. (PC) = 2700H, (SP) = 2700H
C. (PC) = 2800H, (SP) = 26 FEH D. (PC) = 2A02H, (SP) = 2702H
Correct Option: B

Given
(SP) = 2700H
(PC) = 2100H
(HL) = 0000H
2100H : DAD SP: it adds the contents of stack pointer (SP) to the content of HL pair and store the result in HL pair.
∴ 2700H + 0000H = 2700H stored in HL pair 2101H: PCH L; the content of HL pair are transfered to program counter.
So now PC has 2700H and contents of SP remains unchanged
∴ (PC) = 2700H
(SP) = 2700H

4. An input device is interfaced with Intel 8085A microprocessor as memory mapped I /O. The address
of the device is 2500H. In order to input data from the device to accumul at or, the sequence of
instructions will be
A.
LXI H,2500H
MOV A,M
B.
LXI H,2500H
MOV M,A
C.
LHLD 2500H
MOV A,M
D.
LHLD 2500H
MOV M,A
Correct Option: A

L × 1 H, 2500H: the data 2500H is loaded into HL pair

MOV A,M: the content of memory location whose address is in HL pair, is moved to accumulator. So finally input data
from device is moved to accumulator.
5. In an 8085 microprocessor, the contents of the Accumulator, after the following instructions are
executed will become
XRA A
MVIB F0H
SUB B
A. 01 H B. 0F C. F0H D. 10 H
Correct Option: D

XRA A
A ← 00
MVIBF0
B ← F0
SUB B
A←A–B
A ← A + (2’s complement to B)
A = 00000000
B = 11110000
2’s complement of B = 00010000
∴ A + B = (10)H

6. A portion of the main program to call a subroutine SUB in an 8085 environment is given below. :

It is desired that control be returned to LP + DISP + 3 when the RET instruction is executed in the
subroutine. The set of instructions that precede the RET instruction in the subroutine are

A.

B.
 C.

D.
Correct Option: C

7. An output device is interfaced with 8-bit microprocessor 8085A. The interfacing circuit is shown in
figure

The interfacing circuit makes use of 3 Line to 8 Line decoder having 3 enable lines E1 ,E2 ,E3. The
address of the device is
A. 50H B. 500H
C. A0H D. A000Hs
Correct Option: B

To enable 3L × 8L decoder, three enable lines E1 (which is connected as an output of AND-gate)

should be HIGH and E2 and E3 should be active low, it means I0/m should be active low which is indicating that it is
memory mapped I/O interfacing. So address of the device will be in 16-bits. To select output port through decoder 2nd
line the status of A15 (I2) A14(I1) A13(I0) = 010 and to enable decoder through E1 enable line A12 = 1 and A11 = 0 and by
 default as a starting address other address lines (A10......A0) shold be zero. So, overall port address is

8. The ____ number of address lines are needed to address each memory location in a 2048 × 4 memory
chip
A. 12 B. 12 C. 13 D. 11
Correct Option: D

9. The minimum number of operations required in a micro-processor with 8 data pins to read a 32-bit
word
A. 1 B. 2 C. 3 D. 4
Correct Option: D

10. The address bus of inlet 8085 is 16 bit wide and hence the memory which can be accessed by this
address bus is________KB
A. 60 B. 62 C. 64 D. 66
Correct Option: C

11. The maximum integer which can be stored on an 8-bit accumulator is_______
A. 260 B. 255 C. 260 D. 300
Correct Option: B

12. The number of minimum clock cycles in a machine cycle for 8085 are_____
A. 1 B. 2 C. 3 D. 4
Correct Option: C

13. In a 8-bit microcomputer having 8K bytes of RAM memory, the length of SP will be_______
A. 12 B. 11 C. 10 D. 13
Correct Option: D

14. Following program is written for an 8085 microprocessor to add two bytes located at memory
addresses 1FFE and 1FFF
LXI H, 1FFF
MOV B, M
INR L
MOV A,M
ADD B
INR L
MOV M, A
 XOR A
On completion of the execution of the program, the result of addition is found
A. in the register A B. at the memory address 1000
C. at the memory address 1F00 D. at the memory address 2000
Correct Option: D

15. In 8085 microprocessor, the value of the most significant bit of the result following the execution of
any arithmetic or Boolean instruction is stored in the
A. carry status flag B. auxiliary carry status flag
C. sign status flag D. zero status flag
Correct Option: C

16. An interrupt in which the external device supplies its address as well as the interrupt request, is
known as
A. vectored interrupt B. maskable interrupt
C. polled interrupt D. non-maskable interrupt
Correct Option: C

17. In 8085 microprocessor system, the direct addressing instruction is

A. MOV A, B B. MOVB, OAH
C. MOV C, M D. STA addr
Correct Option: D

18. The highest priority in 8085 micropr ocessor system is

A. RST 7.5 B. RST 6.5
C. INTR D. TRAP
Correct Option: D

19. In a 8085 microprocessor, the following sequence of instructions is executed:

STC
CMC
MOVE A,B
RAL
MOVE B,A
After the last instruction, the output will
A. rotate the contents of the accumulator and store it in B
B. get the contents of B register into accumulator and rotate it to left by one bit
C. double contents of B register
D. manipulate carry in A and B
Correct Option: C

20. The larger the RAM of a computer, the faster is its speed, since it eliminates
A. need for ROM
B. need for external memory
C. frequent disk I/Os
D. need for a data-wide path
Correct Option: C
21. Consider the following set of instructions:
STC
CMC
MOV A,B
RAL
MOV B,A
This set of instructions
A. doubles the number in Register by B B. divides the number in Register by 2
C. multiples B by A D. adds A and B
Correct Option: B

22. A personal computer has typically

A. 5 to 10 kilobytes of main memory
B. 10 to 100 kilobytes of main memory
C. 100 to 256 kilobytes of main memory
D. 256 kilobytes to 1 megabyte of main memory.
Correct Option: D

23. The TRAP is one of the interrupts available in INTEL 8085. Which one of the following statements is
true of TRAP?
A. It is level triggered
B. It is negative edge triggered
C. It is positive edge triggered
D. It is both positive edge triggered and level triggered
Correct Option: D

24. The data bus in 8080A/8085 microprocessor is a group of

A. eight bidirectional lines that are used to transfer 8 bits between the microprocessor and its I/O and
memory
B. eight lines used to transfer data among the registers
C. eight unidirectional lines that are used for I/O devices
D. sixteen bidirectional lines that are used for data transfer between the microprocessor and memory
Correct Option: D

25. If instruction RST is written in a program the problem will jump to location
A. 0020 H B. 0024 H
C. 0028 H D. 002 CH
Correct Option: C

26. An I/O processor control the flow of information between

A. cache memory and I/O devices B. main memory and I/O devices
C. two I/O devices D. cache and main memories
Correct Option: B
27. In an 8085 microprocesser system, the RST instruction will cause an interrupt
A. only if an interrupt service routine is not being executed
B. only if a bit in the interrupt mask is made 0
C. only if interrupts have been enabled by an EI instruction
D. none of these
Correct Option: C

28. An instruction used to set the carry flag in a computer can be classified as
A. data transfer B. arithmetic
C. logical D. program control
Correct Option: B

29. Number of machine cycles required for RET instruction in 8085 microprocessor is
A. 1 B. 2 C. 3 D. 5 E. 7
Correct Option: C

30. A ROM is used to store the table for multiplication of two 8-bit unsigned integers. The size of ROM
required is
A. 256 × 16 B. 16K × 8
C. 4K × 16 D. 64K × 16
Correct Option: D

31. Which of the following statements is true?

A. ROM is a Read/ Write memory
B. PC points to the last instruction that was executed
C. Stack works on the principle of LIFO
D. All instructions affect the flags
Correct Option: C

32. A single instruction to clear the lower four bits of the accumulator in 8085 assembly language is
A. XRI OFH B. ANI FOH
C. XRI FOH D. ANI OFH
Correct Option: B

33. An ‘Assembler’ for a micro-processor is used for

A. assembly of processors in a production line
B. creation of new programmes using different modules
C. translation of a program from assembly language to machine language
D. translation of a higher level language into English text
Correct Option: C

34. The decoding circuit has been used to generate active low chip. Signal for a microprocessor
peripheral (address line are designated as A 0 to A7 for I/O address)
 A. 60H to 63 H B. A4 to A7H
C. 71H to 73H D. 70H to 73H
Correct Option: A

35. The chip select access time for reading ROM contents is
A. the delay between application of proper chip select signal and the stable output address
B. the delay between the previous valid output data and the next change in address
C. the time for which the output data remains valid when the device is no longer selected
D. maximum time for which the valid address can be changed
Correct Option: A

36. After completing the execution, microprocessor return to

A. Halt state B. Fetch state
C. Execute state D. Interrupt state
Correct Option: B

37. Normally a microprocessor cycles between

A. Fetch and Halt states B. Fetch and Interrupt states
C. Fetch and Execute states D. Halt and Execute states
Correct Option: C

38. A high on RESET OUT line signifies that

A. all the registers of the CPU are being reset
B. all the registers and counters are being reset
C. all the registers and counters are being reset and in addition this signal can be used to reset external
support chips
D. processing can begin when this signal goes high
Correct Option: C

39. In 8085, interrupts excepts TRAP are disabled (check the incorrect statement) by
A. a DI instruction B. a system reset
C. acknowledgement of a previous interrupt D. none of these
Correct Option: D

40. During a DMA transfer, the processor (check the incorrect statement)
A. continues its normal operations
B. suspends its normal operations
C. needs to initiate read (write) command
D. needs to check if the input/output device is ready for data transfer
Correct Option: A

41. PSW stands for

A. accumulator contents B. flag byte
C. accumulator and the flag byte D. accumulator and temporary register byte
Correct Option: C
42. A DAD H instruction is same as
A. shifting each bit one position to the left
B. shifting each bit one position to the right
C. shifting each bit one position to the left with a zero inserted in 1st position
D. shifting each bit one position to the right with a zero inserted in 1st position
Correct Option: C

43. READY signal in 8085 is useful when the CPU communicates with
A. a slow peripheral device B. a fast peripheral device
C. a DMA controller chip D. a PPI chip
Correct Option: A

44. Which of the following flag conditions are not available in 8085 processor?
A. Zero flag B. Parity flag
C. Overflow flag D. Auxiliary carry flag
Correct Option: C

45. Every processor must necessarily have

A. data bus B. data bus and address bus
C. control bus D. data bus, a control bus and an address bus
Correct Option: D

46. Direct– Memory Access Channel (DMA) facilitates data to move into and out of the system
A. on first-come first-serve basis B. with equal time delay
C. without sub – routine D. without programme intervention
Correct Option: B

47. Which of the following actions detect locations, and remove mistakes from a programme routine?
A. Erase B. Debug
C. Diagnose D. Emulate
Correct Option: B

48. What is the state of the signal at X?

A. Don’t know B. Floating

C. Changing their states D. All high
Correct Option: B

49. Mnemonic symbols are used

A. to denote address B. to employ hamming code
C. to denote error D. to assist human memory
Correct Option: D

50. Flag is a character for

A. identification of a word B. occurance of some condition
C. marking a tagging D. all of these
Correct Option: D
51. The basic elements of a micro-processor are
A. ALU, memory B. ALU, control unit
C. ALU, memory, I/O device D. ALU, control unit, memory
Correct Option: B

52. Address usually is

A. alphabetical B. numerical
C. alpha-numerical D. none of these
Correct Option: B

53. Accumulation is a device which

A. stores a number
B. adds two numbers
C. adds and stores previously stored number to another number
D. none of these
Correct Option: C

54. ACK indicates reception of

A. correct data B. incorrect data
C. insufficient data D. sufficient data
Correct Option: A

55. A microprocessor is a minimum combination of

A. mP and clock B. mP, clock and ROMs
C. mP, clock, RAMs and ROMs D. mP, clock, RAM, ROM, PIA and ACIA
Correct Option: D

56. In microprocessor architecture, flag indicates

A. the number of microprocessor
B. the name of the manufacturer
C. the inte the bit-size of the micro-processor nal status of the CPU
D. the bit-size of the micro-processor
Correct Option: C

57. Stack pointer is a register which comes into use

A. whenever a data is read from the memory
B. whenever a data is written into the memory
C. whenever the output variable is sent out of the CPU
D. whenever an interrupt or high priority call comes from external devices
Correct Option: D

58. A program counter is a storage register for

A. location of data in memory
B. location of instruction in memory
C. binary code for the operation to be performed
D. address of the next instruction to be executed
Correct Option: D
59. An instruction register is storage for
A. location of data in memory
B. location of instruction in memory
C. binary code for the operation to be performed
D. address of the next instruction to be executed
Correct Option: C

60. The microprocessor contains ROM chip which contains

A. control function B. arithmetic functions
C. instructions to execute data D. memory functions
Correct Option: C

61. The set of commands which give directions to the assembler during the assembly process but are not
translated into machine instructions are called
A. mnemonics B. directives
C. identifiers D. operands
Correct Option: B

62. The advantage of using segment registers in 8086 and above microprocessors are that they
A. allow the memory capacity to be 1 megabyte even though the addresses associated with the individual
instructions are only 16 bits wide
B. allow the instruction, data or stack portion of a program to be more than 64K bytes long by using more
than one code, data or stack segment
C. facilitate the use of separate memory area for a program, its data and the stack
D. all of these
Correct Option: D

63. As compared to 16-bit microprocessor, 8 bit microprocessor are limited in

A. speed B. directly addressable memory
C. data handling capability D. all of these
Correct Option: D

64. Intel 8080A and Motorola 6800 microprocessor differ in

A. number of address lines B. number of data lines
C. instruction set D. instruction set and operating frequency
Correct Option: D

65. In 8085 Program Status Word consists of

A. accumulator contents B. flags
C. both accumulator and flag D. status bits
Correct Option: C

66. Intel 8080A and 8085A differ in

A. number of address lines B. number of data signal
C. instruction set D. number of interrupt
Correct Option: D
67. The synchronization between microprocessor and memory is done by
A. ALE signal B. HOLD signal
C. READY signal D. none of these
Correct Option: C

68. Program Counter is used to

A. store address of the next instruction to be executed
B. store temporary data to be used in arithmetic operations
C. store the status of the microprocessor
D. none of these
Correct Option: A

69. Which of the following signal is used when a microprocessor wants to address the memory?
A. IO/ M B. Status signals
C. ALE D. HOLD and HLDA
Correct Option: C

70. The selection of a microprocessor for an application is done keeping in mind

A. speed compatibility of microprocessor with perip-herals
B. the time critical behaviour of the application
C. the size of program required to implement certain functions
D. all of these
Correct Option: D

71. SHIFT LEFT instruction causes all bits shifted from one position to the left with rightmost bit set to
zero. The effect is to
A. multiply by 2 B. divide by 2
C. SET the most significant bit D. none of these
Correct Option: A

72. 8085 microprocessor is a

A. zero address microprocessor B. one address microprocessor
C. two address microprocessor D. none of these
Correct Option: B

73. Setting contents of a register to zero can be efficiently done by

A. Movimmediate instruct ion using zero as immediate data
B. AND immediate instruction using zero as immediate data
C. XORing register with itself
D. none of these
Correct Option: C

74. Two operands can be checked for equality using

A. OR-operation B. AND-operation
C. X-OR operation D. none of these
Correct Option: C
75. A microprocessor is called an n-bit microprocessor depending on
A. register’s length B. size of internal data bus
C. size of external data bus D. none of these
Correct Option: B

76. A microprocessor is also referred to as

A. the chip that does some calculations for the computer
B. the computer on a chip
C. the chip that is responsible for data transfer
D. none of these
Correct Option: B

77. When used with I/O devices, the term intelligent implies
A. a colour output capability B. speech processing capability
C. high speed printing capability D. features to support offline and online tasks
Correct Option: D

78. An interrupt in which the external device supplies its address as well as the interrupt request is known
as
A. vectored interrupt B. maskable interrupt
C. non-maskable interrupt D. designated interrupt
Correct Option: A

79. An interrupt which can be temporarily ignored by the counter is known as

A. vectored interrupt B. non-maskable interrupt
C. maskable interrupt D. low priority interrupt
Correct Option: C

80. The bus which is used to transfer data from main memory to peripheral device is the
A. data bus B. input bus
C. DMA bus D. output bus
Correct Option: C

81. The three buses associated with three-bus system are I/O bus, memory bus and the
A. address bus B. unibus
C. direct memory access bus D. data bus
Correct Option: C

82. Which of the following cycle is required to fetch and execute information?
A. Clock cycle B. Tri cycle
C. Introduction cycle D. Memory
Correct Option: C

83. The register whose contents may be added to or subtracted from the operand address prior to or
during the execution of an instruction is known as
A. index register B. control register
C. address register D. none of these
Correct Option: A
84. An opcode
A. translates a mnemonic B. instructs the CPU
C. stores data D. all of these
Correct Option: B

85. Which of the following enables peripherals to pass a signal down the bus to the next device on the bus
during polling of the device?
A. DMA B. interrupt vectoring
C. daisy chain D. cycle stealing
Correct Option: C

86. The stack pointer in the 8085 microprocessor is a

A. 16 bit register which points to stack memory locations
B. 16 bit accumulator
C. memory location in the stack
D. flag register used for the stack
Correct Option: A

87. A microprocessor with 12 address lines is capable of addressing

A. 1024 locations B. 2028 locations
C. 4096 locations D. 64 K locations
Correct Option: C

88. The flow and timing of data to and from the microprocessor is regulated by
A. control pins B. address pins
C. data pins D. power pins
Correct Option: A

89. The process of fetching and executing instructions one at a time in the order of increasing addresses is
known as
A. instruction execution B. straight line sequencing
C. instruction fetching D. random sequencing
Correct Option: B

90. The register which contains the data to be written into or read out of the addressed location is known
as
A. index register B. memory address register
C. memory data register D. program counter
Correct Option: C

91. The register which holds address of the location to or from which data are to be transferred is known
as
A. index register B. instruction register
C. memory address register D. memory data register
Correct Option: C
92. The register which keeps track of the execution of a program and which contains the memory address
of the instruction currently being executed is called
A. index register B. memory address register
C. program counter D. instruction register
Correct Option: C

93. The register which contains the instruction to be executed is called

A. instruction register B. index register
C. memory address register D. memory data register
Correct Option: B

94. In a 8-bit microprocessor, the fetch cycle required to fetch a 8 byte instruction will be
A. 1 B. 2
C. 5 D. depends on computer design
Correct Option: D

95. An instruction cycle is made up of

A. one or more execute cycles B. one or more fetch cycles
C. one opcode and one execute cycle D. none of these
Correct Option: A