Scribd
Upload
15 views1 page

Lab5 - Introduction To HDL

Digital Electronics Lab5 - Introduction to HDL

Uploaded by

alaminuiu07
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
15 views1 page

Lab5 - Introduction To HDL

Digital Electronics Lab5 - Introduction to HDL

Uploaded by

alaminuiu07
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 1

United International University (UIU)

Dept. of Electrical & Electronic Engineering (EEE)


EEE 224: Digital Electronics Laboratory

Lab 5: Introduction to HDL

PURPOSE

This lab elaborates the usage of the Xilinx ISE Design Suite for Verilog HDL design.

PRELAB

(1) Write the truth table for a Half Adder circuit. Obtain the output equations for it and draw its
logic circuit diagram accordingly.

(2) Write the truth table for the logic equation

Out = (S. I0) + S.I1

Draw a logic circuit diagram for this function using AND, OR and NOT gates. Assume that
complemented inputs are NOT available so S must be generated explicitly by your circuit. There is
no need to use the Xilinx ISE Design Suite at this time.

EXPERIMENT

(1) The Lab Instructor will demonstrate the usage of the Xilinx ISE Design Suite to you. Make
sure you understand the demonstration. Please see the attached HDL Tutorial.

(2) Using Xilinx ISE Design Suite, create a module mux_2to1 according to the wire connection
you have drawn in the circuit diagram from Pre-Lab (2). Create a test bench module mux_2to1_tb
to simulate the mux_2to1 module. Run simulation, testing all combinations of the inputs, S, I0 and
I1. Write down your results in the form of a truth table, and create the timing diagram from Xilinx
ISE Design Suite using ‘Simulate Behavioral Model’ under ISim Simulator of the process window.
Save your files in a pen-drive. Print a copy of your circuit (i.e. design module and test bench
module) and timing diagram.

(3) Perform the similar tasks for Half Adder as done in Pre-Lab (1).

FINAL REPORT: All that is required for this Lab is your Verilog modules and timing diagram
printouts.

Start to work on the Laboratory 6 Pre-Lab questions.

You might also like