United International University (UIU)

Dept. of Electrical & Electronic Engineering (EEE)

EEE 224: Digital Electronics Laboratory

Lab 7: Latches and Flip-Flops

PURPOSE

The purpose of this experiment is to introduce the various types of bi-stable elements and their
characteristics. The positive-edge-triggered D flip-flop is the most important. Nearly all will be
done using Verilog HDL software.

INTRODUCTION

The following diagram illustrates the different ways in which the different types of flip-flops (FFs)
respond to the same inputs.

(Clock) C

(Data) X

74LS74
Positive-edge-triggered D FF

74LS109
Positive-edge-triggered J-K FF

74LS112
Negative-edge-triggered J-K FF

The control input C is connected to the Clock or Enable of all three FFs. The data input X is
connected to the D-input and the two J-inputs. The K-input of the J-K FF is connected to +5V and
the K-input is connected to 0V, their active levels.

PRELAB

(1) (5 pts) Using Verilog HDL design and document a circuit for an SR Latch (not an SR Latch)
using only one 74LS00 IC package. The outputs will be the same when both S and R are asserted,
but it doesn't matter whether they are both 0 or both 1. Include both the Q and Q outputs. In your
lab book, write out the function table and the logic symbol of this device. Save the file for
demonstration to your Lab Instructor. (The 74x279 contains four SR latches.)

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(2) (8 points) In TTL Databook, look up and record the typical propagation delay of your 74LS00
NAND gates. Change the Verilog HDL to add the delays for each gate of your module and then
run a simulation, and print out the trace for inclusion here.

(3) (8 points) Redraw the following chart in your Lab Notebook and consider the three devices
listed. Show the output waveforms at Q in each case assuming that all devices are initially cleared
as shown. Do not use Xilinx ISE Design Suite and disregard propagation delays. If C has a
frequency of 12.5 MHz with a 50% duty cycle, what is the time per division?

Name Function

C (Clock)

DJ (D or J)

K/K (K or K)

74LS74
Positive-edge-triggered D FF

74LS109
Positive-edge-triggered J-K FF

74LS112
Negative-edge-triggered J-K FF

(4) (5 points) Using Verilog HDL, design a simple circuit to demonstrate these waveforms.
Create three 1-bit inputs named C, DJ, and K/K and connect them to the appropriate inputs - D, J,
K, or K - of the three devices. Another 1-bit input should be used to generate a signal (RESET) to
initialize the flip-flops to 0. Print out a copy of your design module to include with your report.

EXPERIMENT

(1) (4 points) On the simulator, demonstrate the circuit from Prelab 1 to your Lab Instructor.
In your report, discuss the problematic behavior of this simple device when both S and R are
simultaneously un-asserted from their previous asserted values.

(2) (6 points) Use the waveforms shown in Prelab 3 to run a simulation and print out the trace for
inclusion here. Compare these results to those you drew by hand for Prelab 3. They should be the
same.

Discuss with your Lab Instructor any problems you may have had with the Prelab assignments.

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POSTLAB

(1) (5 points) A negative edge-triggered T flip-flop can be built using a 74LS74 positive edge-
triggered flip-flop, a 74LS04 inverter, and a 74LS86 Exclusive-OR gate as shown:

D Q Q
EN

T CLK Q

Suppose the ICs have the following timing parameters:

74LS74 - Min. propagation delay, clock to output 10 ns

- Max. propagation delay, clock to output 40 ns

74LS04 - Min. propagation delay, input to output 3 ns

- Max. propagation delay, input to output 10 ns

74LS86 - Min. propagation delay, input to output 5 ns

- Max. propagation delay, input to output 15 ns

Determine the following timing parameters for the composite negative edge-triggered flip-flop
constructed as above. Show how you calculate them from the individual parameters given.

(a) Min. propagation delay, T to output Q

(b) Max. Propagation delay, T to output Q
(c) Min. propagation delay, EN to output Q
(d) Max. propagation delay, EN to output Q

(2) (10 points) Analyze the sequential logic circuit, actually a clocked synchronous state machine,
shown in the next page. Do this by hand. ISE Design Suite timing diagrams will not be accepted.

(a) Explicitly show that whenever the input X = 1, the flip-flops always clear on the next
clock tick, regardless of their current value or state, and that the output Z = 1.

(b) Then, assuming that X = 0 and that the flip-flops are both cleared, draw a timing
diagram for CLK, X, QB, QA, and Z for 10 clock ticks or until the signals repeat
themselves, whichever comes first.

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 QA
Z
X D Q J Q
QB
CLK
CLK
CLK Q K Q

What is the function of this circuit? There are two ways of looking at it. (1) Sequence
Detector: X is considered to be a serial data line. The circuit asserts its output Z only when it
detects a non-overlapping sequence of four consecutive 0s on X. (2) 2-bit Binary Counter: X is
considered to be an active-low control signal (better named EN), which, when asserted, enables the
circuit to increment its contents. The two flip-flops, with QB the MSB, count 00, 01, 10, 11, and Z
(better named MAX) indicates when the maximum count is reached. When not enabled, this
counter always returns to 00.