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Lab8 - Sequential Logic Design

Digital_Electronics_Lab8 - Sequential Logic Design

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5 views

Lab8 - Sequential Logic Design

Digital_Electronics_Lab8 - Sequential Logic Design

Uploaded by

alaminuiu07
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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United International University (UIU)

Dept. of Electrical & Electronic Engineering (EEE)


EEE 224: Digital Electronics Laboratory

Lab 8: Sequential Logic Design: Counters

PURPOSE: The purpose of this lab is to familiarize you with a common sequential logic circuit,
the binary counter.
7474
PRELAB
(1) (6 points) Design a 3-bit binary ripple counter with three D 1R 1 14 VCC
flip-flops and as little else as possible (up_cntr_3bit). This
1D 2 13 2R
counter has 23 states.
1CLK 3 12 2D
Only the first flip-flop (LSB) of a ripple counter is triggered by the 1S 4 11 2CLK
external clock (CLK). The next flip-flop is triggered by the first. If 1Q 5 10 2S
it toggles, it does so after the LSB and so on down the line. This 1Q 6 9 2Q
means that the counter will always momentarily enter intermediate GND 7 8 2Q
states whenever two or more flip-flops change state. To detect the
presence of the glitch states and the valid ones, add 74x138 3-to-8 Dual Positive Edge-
Decoder in your circuit to decode the eight states of your counter. Triggered D Flip-flop

The eight outputs of your Decoder tell you when your counter contains a certain binary value.
Each valid state will persist for one period of CLK. But some outputs of your Decoder will
produce spurious outputs or glitches as well, whenever the counter happens to pass through the
decoded state on its way to another. These occur shortly after the active edge of CLK. Other
outputs never show any glitches. Explain which states do or don't, and why.

(2) (6 points) Change your design to make the ripple counter count down (dwn_cntr_3bit) instead
of up. Which states glitch now?

EXPERIMENT
(1) (5 points) Using Verilog HDL implement the ripple counter (up_cntr_3bit.v) and a test bench
(up_cntr_3bit_tb.v) and simulate the circuit designed in PRELAB 1. Demonstrate your
working circuit to your Instructor by going through the sequence of counter values. √Include a
printout of the modules and timing diagram in your lab book.

(2) (5 points) Write Verilog HDL for the down counter (dwn_cntr_3bit.v) and a test bench
(up_cntr_3bit_tb.v) and simulate the circuit designed in PRELAB 2. Demonstrate your
working circuit to your Instructor by going through the sequence of counter values and verify that
each CLK pulse decrements the count. √Include a printout of the modules and timing diagram in
your lab book.

1
(3) (5 points) Add the Decoder (decoder_3to8.v) to your down-counter (dwn_cntr_3bit.v) and
simulate to see the Decoder outputs. Note the presence of glitches on four of them. You may have
to turn up the frequency of CLK in order to see them. √Include a printout of the modules and
timing diagram in your lab book.

FINAL REPORT None is required.

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