Basic Computer Operations(3)(2)(2)
Basic Computer Operations(3)(2)(2)
• State the functional units in the Central Processing Unit (CPU) of a computer
System Bus
• Input/ Output (I/O) Interface Data bus
Hence, multiple bits are combined together to give a wider range (or more variety of combinations).
The subscript ‘2’ or ‘b’ means the number should be interpreted using a base-2 numeral system.
Example:
Decimal value of 0110b 0110b = 23 × 0 + 22 × 1 + 21 × 1 + 20 × 0
= 0 + 4 + 2 + 0
≡ 610
Introduction to Computational Thinking 12
Hexadecimal Format
Base-2 binary format: most conveniently used by the computer but it is not human-friendly.
e.g. 1011010101101100b
To make it easier for human to read (and write) binary data, base-16 hexadecimal format
is normally used instead.
Hexadecimal symbols: 0, 1, 2, … 8, 9, A, B, C, D, E, F
To convert between the two formats, the binary format data is separated into groups of four (4) bits.
• one Word = 16 bits or 32 bits, depending on the natural data size/ data width of the
CPU architecture
• CPU
• System bus
Recap
System Bus
• Input/ Output (I/O) Interface Data bus
Control bus
• System Bus
- providing the connection between the
Microprocessor
modules
CPU
Three main Functional Units within the CPU:
• Control Unit (CU) REG
- controls and coordinates the overall operation of the
ALU REG
CPU
REG
• Arithmetic/ Logic Unit (ALU)
- performs the arithmetic operations as well as Boolean
logic functions
:
CU
REG
• Register Array
- holds the various information used by CPU operations
These functional units are connected internally by wires that System Bus
are extended to the external system bus.
The system bus consists of groups of parallel signals that are used to transfer information
between the modules in the microprocessor.
System Bus
Control Bus - provides the control signals for the Data bus
:
Each location stores an 8-bit (byte) size data. :
:
2
Each location is allocated a unique address.
1
• identified by specifying its binary pattern on the address bus
0
0
When n = 20 8 bits
• 220 ≡ 1024 × 1KB = 1KB × 1KB is known as 1 MegaByte (MB)
When n = 30
• 230 ≡ 1KB × 1KB × 1KB is known as 1 GigaByte (GB)
CPU Memory
REG MEM
MEM
REG
ALU MEM
REG .
System .
:
CU Bus MEM
REG
MEM
• How the CPU and memory work together when executing a program
• The role of the different functional units within the CPU module
When a program is loaded in the memory, the memory will hence contain the following information:
• instructions to be executed
• data needed by the relevant instructions
Fetch
Decode
Execute
So, how does the CPU know whether the content retrieved is an
instruction or data (e.g. an unsigned integer)?
Valid machine instructions of a microprocessor family are encoded in specific binary bit patterns
• known as the instruction set of that microprocessor
To understand how the CPU works, the simple stored-program model will be used here
• where both instruction and data are stored in the memory
CPU Memory
REG -
ALU Data
REG
System Data
REG Bus
.
. .
CU
. Instr
REG Instr
Example
Addition Instruction: CPU Memory
Var1 = Num1 + Num2 REG A yyh
ALU
REG B
.
61h Num1
Assumptions:
REG C 60h Num2
• Num1 is stored in memory .
location 61h. . System 40h Var1
• Num2 is stored in memory CU . Bus .
location 60h. 01h
REG x
00h
• Var1 is stored in memory
location 40h.
Example
Addition Instruction: CPU Memory
Var1 = Num1 + Num2 Num1
REG A yyh
Num1
ALU
+
Num2
REG B
.
Num2 Num1
Execution: CU carries out 61h
REG C 60h Num2
the addition operation
.
• Num1 is copied to (loaded . System 40h Var1
into) Register A
CU . Bus .
• Num2 is copied to Register B 01h
REG x
00h
• ALU executes the Addition
operation: REG A + REG B
Example
Addition Instruction: CPU Memory
Var1 = Num1 + Num2 Num1
REG A yyh
Num1
ALU
+
Num2
REG B
.
Num2 Num1
Execution: CU carries out 61h
REG
Num1 C
+ Num2
60h Num2
the addition operation
.
• Result of ALU operation is . System 40h Var1
Num1 + Num2
moved into Register C.
CU . Bus .
• Content of Register C is 01h
REG x
copied (stored) into memory 00h
location 40h.
Example
Let Num1 value = 03h, CPU Memory
Num2 value = 15h, 03hA
REG yyh
03hALU
+ 15h
= 18h 15hB
REG
.
and Var1 = xxh 61h Num1
03h
(i.e. it doesn’t matter) 18hC
REG 60h Num2
15h
.
. System 40h xxh
18h
Var1
CU . Bus .
01h
REG x
00h
CPU
REG A
ALU REG B
Instructions
Each operation cycle of the stored-program CPU typically involves three (3) basic steps:
After power-on,
• memory is loaded
with program and
data
• Program Counter’s
content is set to
‘00h’ (by design)
• The set of instructions understood by a CPU “3A” is the code that means “Load
is specific to that particular CPU, which is Register A from memory”.
determined by the designer of the CPU.
• Hence each CPU has its own “language”, Note: This will have a totally different
which is known as its instruction set. meaning for another CPU family
• Examples: (E.g. It could be interpreted as “multiply”).
Back to Example
After power-on,
• memory is loaded
with the program
and data
• PC content is set to
‘00h’ (by design)
Fetch 1
• Content of location
00h and 01h are
loaded (or fetched)
into IR (assume 16-
bit size instruction).
• PC then
automatically
increments to ‘02h’
(by design).
Decode 1
CU decodes the content
IR:
Execute 1
CU executes the
instruction:
Fetch 2
• Content location 02h
and 03h are loaded
into IR.
• PC increment to ‘04h’.
Decode 2
CU decodes the content
IR:
Execute 2
CU executes the
instruction:
Fetch 3
• Content of location
04h and 05h are
loaded to IR.
• PC increments to
‘06h’.
Decode 3
CU decodes the content
IR:
Execute 3
CU executes the
instruction:
Fetch 4
• Content of location
06h and 07h are
loaded to IR.
• PC increments to
‘08h’.
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Introduction to Computational Thinking
An Illustrative Example (Cont’d)
Decode 4
CU decodes the content
IR:
Execute 4
CU executes the
instruction: