Simplifying the Boolean Equation Based on

Simulation System using Karnaugh Mapping Tool in

Digital Circuit Design
Md. Jahidul Islam , Md. Gulzar Hussain, Babe Sultana, Mahmuda Rahman , Md. Saidur Rahman
and Muhammad Aminur Rahaman

Abstract—In computerized integrated circuits, the Logic (PAL) and Programmable Logic Array (PLA)
fundamental principle intends to avoid the multifaceted [1], and here the amount of logic circuits are to be
nature of the circuitry by making it as brief as attainable maintained in a minimal form, the production costs
and minimize the expenditure. Techniques like Quine- of such devices will be decreased. The K map is
McCluskey (QM) and Karnaugh Map (K-Map) are often the graphical procedure to optimize Boolean function
used approaches of simplifying Boolean functions. This
study presents a recreation framework of simplification throughout the format of a minimal SOP form. Logic
of the Boolean capacities by the utilize of the K- Gate-wise, these observations resulted such a two-
Map definition for beginner-level learners. It uses the tier minimal system. It’s used mostly for many small
algebraic expression of the Boolean function to decrease design problems. It is obvious that several larger mod-
the number of terms, generates a circuit, and does els are carrying out using various computer method
not use any redundant sets. In this way, it gets to be implementations, and so we can obtain a pretty good
competent to deal with lots of parameters and minimize
insight in to digital logic gate circuit after learning K
the computational cost. The result of the assessment is
performed in this paper by contrasting it with the C- map. The process of logic to circuit design in digital
Minimizer algorithm. In computation time terms, the logic circuit design, AND, OR, and NOT are treated
result appears that our comprehensive K mapping tool as the basic boolean operations. These processes can be
outflanks in current procedures, and the relative error combined to construct complex expressions that can
accomplishes a lower rate of percentage (2%), which be directly converted into a hardware implemen- tation,
fulfills the satisfactory level. too. The construction cost of a logic gate circuit is
Index Terms—K-map, Digital Logic Design, Quine inferred by its Boolean Algebraic expression. Small
McCluskey(QM) technique, C minimizer . configuration circuit’s costs will be smaller than
biggest one. For a wide range of logic gate
I. I NTRODUCTION configuration is being performed with a tiny one and
OGIC-level simulation is one of the most the resulting functionality is the same as well, in that
L commonly performed electrical circuit practices,
during testing times and design. Amount of logic will
case, we will definitely take the small one because
of the low cost. It can be difficult to use Boolean
be integrated in a simple circuits grows fast, there is a algebra to simplify Boolean expressions and can lead
need for greater attempts to automate the designing to solutions that are not, although they seem minimal.
scheme. One of the key objectives is to develop Numerous studies have been conducted to simplify the
integrated logic circuit with the Programmable Array Boolean expression. First of all the Boolean function
is simplified by postulates and theorems in which
DOI: https://doi.org/10.3329/gubjse.v7i0.54025 there are no special regulations [2]. The very first
approach to minimize it seems to apply theorems
This paper was received on 9 January 2021, revised on 15 March of postulates and many other specific manipulation
2021 and accepted on 19 April 2021.
techniques. Best of our knowledge, literally, for a
Md. Jahidul Islam is with the Computer Science & Engineering,
Green University of Bangladesh, Dhaka, Bangladesh. E-mail: limited count of variable in the primary learning stage,
[email protected] the K map is very smooth and better, but it is difficult
Md. Gulzar Hussain is with the Computer Science & Engineering, to do it side by side when comes to more than 5
Green University of Bangladesh, Dhaka, Bangladesh. E-mail:
[email protected] variables. The goal of this research study is to work
Babe Sultana is with the Computer Science & Engineering, Green University with the primary level digital logic design learners who
of Bangladesh, Dhaka, Bangladesh. E-mail: [email protected]
Mahmuda Rahman is with the Computer Science & Engineering, are want to work with Boolean Expression and circuit
Green University of Bangladesh, Dhaka, Bangladesh. E-mail: mah- containing a large number of variables while they want
[email protected]
Md. Saidur Rahman is with the Computer Science & Engineering, Green to use the mapping approach for minimizing
University of Bangladesh, Dhaka, Bangladesh. E-mail: [email protected] Boolean function. The rest of our research paper
Muhammad Aminur Rahaman is with the Computer Science & is ornamented as follows. The background history
Engineering, Green University of Bangladesh, Dhaka, Bangladesh. E-mail:
[email protected] of Boolean Logic Design and its simplification

76 Green University Press

 Simplifying the Boolean Equation Based on Simulation System using Karnaugh Mapping Tool in Digital Circuit Design

techniques with the decade invention of this area are But for dealing with a large number of variables, there
discussed in II. The demonstration and the process of is no definition. To minimize different circuit outputs,
the Kaurnaugh mapping are exhibited in section III. the author [22] suggested an Expanded K-MAP that
Overall demonstration of whole working procedures uses a single Karnaugh map. And essentially, in their
are exhibited in section IV. The impact of our research algorithm, the multiple Karnaugh-maps accumulated in
works with performance evaluation are described in a single Karnaugh-map. The experimental outcome of
section V. And at the end, we have concluded and their contribution and interpretation gives us an idea
addressed the future direction in section VI. that they function only for no more than 5 vari- ables.
Authors of [10] proposed a modified algorithm of K-
II. R ELATED W ORKS Map algorithm and implemented a K-map solver which
works up to 6 variables. It also performs better than C-
In this section, significant research has been dis-
Minimizer algorithm [7].
cussed below:
For big amount of variables, the common tabular
III. OVERVIEW OF K AURNAUGH M AP T OOL
method called the Quine McCluskey (QM) technique is
sufficient. This tabular technique is a step-by- step Kaurnaugh map optimizes the boolean function using
procedure which is a system-wise instruction the human’s ability to identify patterns. This re- search
introduced by Quine [3] first and McCluskey [4] paper presents a structure to implement the K- map for
demonstrated it in later. It operates for huge numbers optimizing the boolean function. A boolean function is
of variables, as far as we know. So it is perfect for fed to the system as an input. Then the sys- tem
controlling machines. Two main activities work for generates 2n positions in the K-map based on the input
QM method is as follows: a) Prime Implicates variables (n). In K-map each position contains a digit
Determination b) Collection of Critical Prime either zero or one to represent the output of the
Implicates [5]. Main sickening aspect of QM seems: function for the corresponding combination of the
QM is a NP Complete problem and computation times input.The system then generates minterm groups with a
of the algorithm enhance exponentially by the region of 2n (where, n = 0,1,2,...) with neighboring 1s.
increasing length of input [6]. Therefore, it is quite And then by evaluating which variables remain the same
difficult for primitive level DLD students to manage inside each box, algebraic minterms are derived.
the tabular method of QM. The common approach
of generalization, called the mapping method. Veitch
[7] suggested it first and then Karnaugh modified it.
[8], provides a smooth, transparent procedure for
reducing Boolean expressions.
The K map is truly an important instrument with few
parameters in the processing of algebra logic. In the
engineering field, this system is often used for various
purposes. Author prasad at el. [14] premises a K-map
like online cable virtualization engaging algorithm that
consists of two things, first one is scheduling
technique which is based on online and second one is
K-map-like embedding algorithm. Au- thor jinrong at
el. [18] offers an alg at el.orithm which is one of
the simplified way to use the idea of a relational Fig. 1: A Karnaugh Map with 4 × 4 Cells
database by using the Karnaugh map approach to
manage all candidate keys with usable dependency
sets. After all and above discussion, it can be said
that, working with such a wide range of variables for
the Karnaugh map will be a significant achievement
throughout this sector. The researcher [19] discusses a
prominent primary design of elec- tronics circuit issue
that is compounded by the Type 2 problem. This
resource gives an overview of their ongoing attempt to
reform techniques to deal with basic digital circuit
design problems through ’big’ Boolean algebraic
methods. In this research [20] has an integrated method
since it teaches students how to easily and logically
simplify Boolean equations step by step, including a
description of the phases and instances to explain
that. The author [21] suggests a modified method
of the Karnaugh map that gives students a
opportunity to analyze exactly how a K- map was Fig. 2: Block Schematic of the Suggested
generated and helps all to know some queries Implementation Framework for the Karnaugh Map
farther explicitly during the education in DLD.

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TABLE I: EXISTING WORKS ANALYSIS

Authors Contributions
Elham et al. [9] Design a simulation system that finds optimal expression and reduces the cost of the
circuit.
Rahman et al. [10] Develop a Karnaugh mapping that can deal with a big number of variables with
minimum cost and also a comparison with C-Minimizer algorithm.
Rushdi et al. [11] Present a prominent basic digital circuit design issue using Variable-Entered Karnaugh
Maps (VEKMs) with don’t care notation.
Vyas et al. [2] Propose a procedure widely linked to asymmetric base logic function systems using
Karnaugh maps and also the technique thus makes it possible to minimize spintronic
and memristive logic circuits.
Wang et al. [12] Design a system that enhances the concept of Karnaugh maps also demonstrate the
results and applications.
Abdalla et al. [13] Develop a method that improves the concept of Karnaugh maps and better than the
Quine-McCluskey method for low and large variables.
Prasad et al. [14] Propose a generalized Karnaugh Map Method that uses ”K–don’t care” and it can easily
solve seven variables k-map for all prime implicants.
Kim et al. [15] Design a karnaugh map using web-based java applets based on Quine-McCluskey
minimization technique which aim is to maximize the learning efficiency.
Murugavelneural et al. Design a Boolean circuit and also proposed an algorithm with many variables using
[16] modified karnaugh map
Nabulsi et al. [17] Present a comprehensive procedure that simplified the logical function using a truth
table Based on the Minterms combination.
Proposed Design & development a simulation system that finds optimal expression, simplified the
logical function using a truth table, reduces the cost of the circuits and also demonstrate
the results.

digit in every location of the Karnaugh-map. They

suggested approach uses two arrays of one dimension
where this one is used for holding the location of the
K map & the other one is used for storing the result
of the function for that location in the same array index.
For instance, Fig. 4 displays the iterator repre- sentation
of a 4-variable Boolean expression between both the
location set as well as the method output list. The
framework produces all the potential classes of
minterms for both the periodic system dependent on
the number of parameters and the variations are
described by an Array List of two dimension. The
List is then forwarded to the GroupChecker method to
review the unique Boolean expression for a major
combination of minterms containing adjacent 1s.

Fig. 3: System Flow Diagram for the K-Map

IV. M ETHODOLOGY Fig. 4: Positional Values of K-Map (4 Variables)

A. Creation of 2n Positions and Min-term Groups
B. Checking of Groups
The framework creates 2n placements for n param- Minterms are grouped possessing a region of 2n
eters to build the K-map where gray code is used (where, n = 0,1,2,...) in K-map. The method Group
to order the locations as if the change occurs only Checker has tested all possible combinations which
in a single variable in each pair of adjoining cells. Then can be generated by the neighboring 1’s. The con-
the output of the function for the corresponding flicting groups were often thought to establish bigger
input combinations is preserved using zero and one

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 Simplifying the Boolean Equation Based on Simulation System using Karnaugh Mapping Tool in Digital Circuit Design

Fig. 5: An Overview of all Possible Permutations of the Boolean Method Min-term Consisted of Three
Parameters.

Algorithm 1: K Map Algorithm 2: Algorithm of Group Checker

Input: k-Map position Array[], Input: k-Map[], combination-Array[],
function output[], variable Size combination-Number,
Output: vCombinationArray[],rGroup[] mCombinationCount, grpMax1
1 Initial variable Size ← values from the users;; Output: validGrpCombinations
2 Initial k-Map position Array ← values from 1 Initial pCombination[] ←
the users; mCombinationCount;
3 Initial function output ← Method input values 2 Initial s ← 0;
as stated by the location; 3 Initial end ← combination-Array[].length;
4 Initial comb[][] ← Potential amalgamation 4 Initial f ← 0;
values of the array; 5 for i= 0 to end do
5 Initial m ← 0; 6 if k-Map[combination-Array[i]] = 1 then
6 Initial s ← 0; 7 increment f by 1;
7 Initial end ← combination[][].len; 8 end
8 for k= 0 to end do 9 if f = grpMax1 then
9 init vCombination ← 10 pCombination[combination-Number]← 1;
call group-Checker(k-Map[], comb[k], 11 increment s by 1;
k); 12 return one;
10 if vCombination = zero then 13 else
11 increment m by one; 14 return zero;
12 end 15 end
13 end
14 Init rGroup[]← call C. Algebraic Min-terms Computation
pCombination[group-Size];
The given algorithm 3, measures the numbers of ones
in each grouping while groups are generated. It
numbers of groups without any zeroes. Fig. 5 demon- specified how many parameters are needed to describe
strates that, there exist two potential minterms classes this min-term as according to the number of ones.
of getting area four for the scenario given in Fig. 4. Whenever the number of parameters is specified, the
Therefore the method GroupChecker returns amount frequent bit among all the places was regarded as well
of teams for that key method. as the parameter for that location was obtained.

Algorithm 3: Counter of Numbers of one’s

Input: k-Map[]
Output: The Numbers of 1’s
1 Init count ← 0;
2 Init len ← k-Map[].len;
3 for k=0 to len do
4 if k-Map[combination-Array[k]] is one
then
5 increment count by one;
Fig. 6: Min-terms Groups for Boolean Methods 6 end
7 end
8 return count;

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 GUB Journal of Science and Engineering, Volume 7, Issue 1, Dec 2020

D. Circuit Drawing from Expression This system uses the input expression 1 and gener-
The given algorithm 4, generates the required cir- ates truth table and simplified equation shown in Fig. 7.
cuit form the simplified equation. In this algorithm The best part is our it also generates the circuit (with
operators and operands are considered to generate minimum cost) diagram as Fig. 8. Moreover, 5
correspondingly circuits. variables K-Map truth table, optimal expression and
circuit diagram also shown in Fig. 9 and 10 respectively.
Algorithm 4: Algorithm for Circuit C. Performance Discussion
Genera- tion 1) Influences of increase in the number of Parameters
Input: Expression[] with relative error: A team of 100 Digital Logic Design
Output: Circuit (DLD) students and undertaking a Bachelor’s Degree in
1 Init len ← Expression[].len;
Computer Science and Engineering (CSE) inspected it
2 for k=0 to len do
after the implementation of the system. The students are
3 if Expression[k] is ’+’ then given three(3) groups of Boolean algebra expressions
4 Generate a OR circuit; with parameter number three(3), four(4), five(5), six(6),
5 Assign Expression[k-1] as left operand and seven(7) to evaluate soft- ware where various
of OR; numbers of equations are included in each set. This is
6 Assign Expression[k+1] as right achieved because it is more difficult to optimize
operand of OR; expression with a greater set of variables than just a
7 end lesser set of variables. For Boolean algebra equations
8 if Expression[k] is ’.’ or ’ ’ then with parameter numbers three (3), four(4), five(5),
9 Generate a AND circuit; six(6), and seven(7), the Table III displays relative and
10 Assign Expression[k-1] as left operand absolute errors.
of AND;
11 Assign Expression [k+1] as right TABLE III: RELATIVE ERROR FOR EXPRESSIONS
operand of AND; No. of No. of ex- Accurately Perfect Relative
Vari- pressions identified Error Error
12 end ables Expres-
13 if expression[k] is '!' then sions
14 Generate a NOT circuit; 200 196 4 0.022
4 400 390 10 0.026
15 Assign Expression [k-1] as operand of 600 584 16 0.027
NOT; 200 192 8 0.042
5 400 380 20 0.054
16 end 600 564 36 0.065
17 end 100 93 7 0.075
18 return Circuit; 6 200 187 13 0.070
300 279 21 0.075
50 44 6 0.136
V. P ERFORMANCE E VALUATION 7 100 83 17 0.205
150 126 24 0.190
A. Setup for Evaluating the System
With the following environment as shown in Table II, we TABLE IV: RELATIVE ERROR FOR CIRCUIT
have tested the established Karnaugh mapping No. of No. of Correctly Perfect Relative
visualization tool: Vari- Circuits Identified Error Error
ables
TABLE II: ENVIRONMENT SETUP 50 49 1 0.02
4 80 77 3 0.038
Operating System Window’s 10 64-bit 100 95 5 0.05
Processors Intel’s Core i5-3.5 GHz CPU 50 47 3 0.06
Memory 16 GB 5 70 64 6 0.086
Solid-State Drive 512 MB 90 80 10 0.11
IDE MS Visual’s Studio Express 2010 10 9 1 0.1
Language C# 6 20 17 3 0.15
30 25 5 0.17
B. Design of the Simulation system
For testing this application the cell numbers (as an From Table III, we do see that relative error increases
input) have been entered. Then, it have found the like those of the numbers of expression as well as the
following Sum of Product (SOP) expression 1 as the numbers of variables increases. We identified a
input of four variables and also have found optimal minimal relative error of 0.02 with 4 variables as well
expression 2 as output which is shown in Fig. 7. as a maximum of 7 expressions of the variables. Fig.
X  ABCD  ABCD  ABCD  ABCD  12 displays the relationship among the numbers of
parameters, the numbers of expression, and also the
ABCD  ABCD  ABCD  ABCD (1)
respective error found in Table III. Moreover, Table
IV shows the relative error for circuit generation with
Y  ACD  ABC  ACD  ABD  ACD (2) respect to the no. of variables. We have identified a

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 Simplifying the Boolean Equation Based on Simulation System using Karnaugh Mapping Tool in Digital Circuit Design

Fig. 7: Simplified Optimal Expression with Truth Table Created by the Expression System 1

Fig. 8: The Circuit diagram produced by the expression (4 variables)

Fig. 9: Simplified Equation for 5 Variables K-Map

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 GUB Journal of Science and Engineering, Volume 7, Issue 1, Dec 2020

Fig. 10: The Circuit Diagram for the 5 Variables

TABLE V: COMPARATIVE ANALYSIS

References Optimal Circuit Generation No. of Variables Truth Table Gen-
Expression used eration
Elham et al. [9] YES NO 4 Variables NO
Rahman et al. [10] YES NO 7 Variables NO
Wang et al. [12] YES YES 4 Variables NO
Abdalla et al. [13] YES NO 6 Variables NO
Prasad et al. [14] YES NO 7 Variables NO
Kim et al. [15] YES YES 3 Variables YES
Nabul et al. [17] YES NO 4 Variables YES
Our System YES YES 7 Variables YES

minimal relative error of 0.011 with 4 variables as well

as a maximum of 6 variables.

Fig. 12: Relative Error with Respect to the Numbers of

Expressions Vs Variables
Fig. 11: System Accuracy (%) for Expressions of the
System with Respect to the No. of Variables performance discovered from the application system.
Fig. 13 shows the computational time increases with
2) System Accuracy: Fig. 11 shows the system the number of parameters. Notably, with a small
accuracy for various expressions with respect to the no. number of variables (i.e. ≈ 4), the computational
of variables. With a small number of variable less time of our system and C-Minimizer assumes similar
than 4, the system accuracy almost 100%. Then, values. Then, increasing the no. of variables, the
increasing the no variables, the accuracy is decreasing computational time also increasing We can assume
with a linear trend. Fig. 12 shows that when number from the graph that we need just 312.43 milliseconds
of variables is increasing and number of expressions for 7 variables, which is very efficient. This result
is decreasing then relative error is high and it is low proves the practicality that can effectively reduce
when the number of variables is low but number of the computational time with respect to the existing
expression is high. baseline.
3) Computation Time Comparisons: We have eval- To measure the effectiveness of this method as there
uated the computational time analysis to evaluate the

82 Green University Press

 Simplifying the Boolean Equation Based on Simulation System using Karnaugh Mapping Tool in Digital Circuit Design

are no latest projects on system creation to reduce the [4] E. J. McCluskey Jr, “Minimization of boolean functions,”
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GUB Journal of Science and Engineering, Volume 7, Issue 1, Dec 2020

Md. Jahidul Islam received the Mahmuda Rahman received her B.

B.Sc. and M.Sc. degrees in Sc. Engineering degree in Computer
Computer Science and Engineering Science and Engineering (CSE)
from Jagannath University (Jnu), from Green University of
Dhaka, in 2015 and 2017 re- Bangladesh, in 2018. She is
spectively. Currently, he is working Currently working as a Lecturer of
as a Lecturer and Program CSE Department in Green
Coordinator (Day) at Computer University of Bangladesh. Her
Science and Engineering (CSE), research interests include Digital
Green University of Bangladesh (GUB), Dhaka, Image processing, Computer Vision and Natural
Bangladesh since May 2017 to present. He is a member Language Processing.
of Computing and Communication and Human-Computer
Interaction (HCI) research groups, CSE, GUB. His
research interests include Internet of Things (IoT),
Blockchain, Network Function Virtualization (NFV), Saidur Rahman received his B.Sc.
Software Defined Networking (SDN), Digital Forensic Engineering degree in Computer
Investigation (DFI), HCI, and Wireless Mesh Networking Science and Engineering (CSE)
(WMN). from Green University of
Bangladesh. He is Currently
working as an assistant programmer
of IT department in Green
Md. Gulzar Hussain was born in University of Bangladesh. His
Nimnagar, Dinajpur City, research interests include Software Engineering and
Bangladesh. He received the B.Sc. Robotics.
degree in computer science and
engineering from the Green Uni-
versity of Bangladesh, Dhaka, in
2018. Since 2019, he has been a Muhammad Aminur Rahaman was
Lecturer with the Computer born in Tangail, Bangladesh, in
Science and Engineering 1981. He received his Ph.D. from
Department, Green University of Bangladesh, Dhaka, the Department of Computer
Bangladesh. He is the author of one conference article. Science & Engineering, University
His research interests include machine learning, natural of Dhaka, Bangladesh in 2018.
language processing, text mining, topic modeling etc. Rahaman has completed his B.Sc.
Mr. Hussain was a recipient of seven times Vice- and M.Sc. degree from the
Chancellor awards and once Dean award for excellent Department of Computer Science & Engineering, Islamic
performance in trimester result. He is a Graduate University, Kushtia, Bangladesh in 2003 and 2004,
Student Member of IEEE since 2019. respectively. He is a founder Director of Worldgaon (Pvt.)
Limited. He is working as an Assistant Professor and
Program Coordinator at the Department of Computer
Science and Engineering, Green University of
Babe Sultana was born in, Cox’s Bangladesh, Dhaka, Bangladesh since September 2018 to
Bazar, Bangladesh, in 1994. She present. His current research interests include Computer
received her B.Sc. Degree in Vision, Image Processing, Human-Computer Interaction
Computer Science and Engineering System, Robotics and Software Engineering. He is a
from Green University of senior member of IEEE.
Bangladesh (GUB) in 2018. At
present she is working as a Lecturer,
Dept. of CSE, Green University of
Bangladesh. Also, her publication was about ”Multimode
Project Scheduling with Limited Resource and Budget
Constraints” published in International Conference on
Innovation in Engineering and Technology (ICIET) 27-
28 December, 2018 and she got Best Paper Award and
IEEE Best Paper Award on this conference. Her research
interests include Theory of Optimization, Natural
language Processing, Renewable and Sustainable Energy.

84 Green University Press