Computer Architecture PYQ - SS2
Computer Architecture PYQ - SS2
COMPUTER ARCHITECTURE
CS401
TIME ALLOTTED: 3 HOURS FULL MARKS: 70
The figures in the margin indicate full marks.
Candidates are required to give their answers in their own words as far as practicable
GROUP – A
(Multiple Choice Type Questions)
1. Answer any ten from the following, choosing the correct alternative of each question: 10×1=10
Marks CO No.
(i) There are situations that prevent the next instruction in the 1 2
instruction stream from being executing during its designated
clock cycle is called
(a) Prefetching
(b) Hazard
(c) Functional dependency
(d) Interleaving
(iv) A computer with cache memory access time of 200 ns, main 1 3
memory access time of 2000 ns and hit ratio of 0.9 produces an
average memory access time of
(a) 250 ns
(b) 218 ns
(c) 190 ns
(d) None of these
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B.TECH. / CSE / R18 / EVEN / SEM-4 / CS401 / 2020-2021
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B.TECH. / CSE / R18 / EVEN / SEM-4 / CS401 / 2020-2021
GROUP – B
(Short Answer Type Questions)
Answer any three from the following: 3×5=15
Marks CO No.
3. What are the different factors that can affect the performance of 5 2
pipeline system?
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B.TECH. / CSE / R18 / EVEN / SEM-4 / CS401 / 2020-2021
GROUP – C
(Long Answer Type Questions)
Answer any three from the following: 3×15=45
Marks CO No.
7. (a) Explain set-associative mapping method with example. 5 3
(b) Explain VLIW architecture with proper diagram. 5 3
(c) Assume that main memory size is of 32 kb x 12. Cache memory 5 5
size is of 512x12 and block size is of 1 word. Describe the
following:
i) Direct mapping technique
ii) Associative mapping technique
8. (a) What is temporal vs. spatial locality? What is MIPS? 3+2 3
(b) Explain Superscalar processor with example and diagram. 5 3
(c) Explain cache coherence problem with diagram. 5 3
11. Write short notes on any three of the following 3x5 =15
(a) Vector register architecture 5 3
(b) Omega network 5 4
(c) Array Processor 5 3
(d) DMA 5 4
(e) Direct Mapping 5 3
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