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Computer Architecture PYQ - SS2

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37 views4 pages

Computer Architecture PYQ - SS2

Uploaded by

trishitkb009
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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B.TECH.

/ CSE / R18 / EVEN / SEM-4 / CS401 / 2020-2021

COMPUTER ARCHITECTURE
CS401
TIME ALLOTTED: 3 HOURS FULL MARKS: 70
The figures in the margin indicate full marks.
Candidates are required to give their answers in their own words as far as practicable

GROUP – A
(Multiple Choice Type Questions)
1. Answer any ten from the following, choosing the correct alternative of each question: 10×1=10

Marks CO No.

(i) There are situations that prevent the next instruction in the 1 2
instruction stream from being executing during its designated
clock cycle is called
(a) Prefetching
(b) Hazard
(c) Functional dependency
(d) Interleaving

(ii) What characteristic of RAM memory makes it not suitable for 1 2


permanent storage?
(a) too slow
(b) unreliable
(c) it is volatile
(d) too bulky

(iii) Basic difference between vector and array processor is 1 2


(a) Pipeline
(b) Interconnection Network
(c) Register
(d) None of these

(iv) A computer with cache memory access time of 200 ns, main 1 3
memory access time of 2000 ns and hit ratio of 0.9 produces an
average memory access time of
(a) 250 ns
(b) 218 ns
(c) 190 ns
(d) None of these

Page 1 of 4
B.TECH. / CSE / R18 / EVEN / SEM-4 / CS401 / 2020-2021

(v) A multiprocessor system with common shared memory is called: 1 3


(a) Loosely coupled system
(b) Tightly coupled system
(c) Both a and b
(d) None of the above

(vi) SPECint is a computer benchmark specification for 1 3


(a) floating point performance testing component of the SPEC
CPU testing suit.
(b) test of the CPU performance
(c) integer performance testing component of the SPEC test
suite.
(d) physical simulations

(vii) The idea of cache memory is based 1 3


(a) on the property of locality of reference
(b) on the heuristic 90-10 rule
(c) on the fact that references generally tend to cluster
(d) all of the above

(viii) Which of the following is lowest in memory hierarchy? 1 3


(a) Cache memory
(b) Secondary memory
(c) Registers
(d) RAM
(e) None of these

(ix) Floating point representation is used to store 1 1


(a) Boolean values
(b) whole numbers
(c) real integers
(d) integers

(x) What characteristic of RAM memory makes it not suitable for 1 3


permanent storage?
(a) too slow
(b) unreliable
(c) it is volatile
(d) too bulky

Page 2 of 4
B.TECH. / CSE / R18 / EVEN / SEM-4 / CS401 / 2020-2021

(xi) The average time required to reach a storage location in memory 1 3


and obtain its contents is called the
(a) seek time
(b) turnaround time
(c) access time
(d) transfer time

(xii) The total size of address space in a virtual memory system is 1 2


limited by
(a) The length of MAR
(b) The available secondary storage
(c) The available main memory
(d) All of the above

GROUP – B
(Short Answer Type Questions)
Answer any three from the following: 3×5=15

Marks CO No.

2. (a) Classify Flynn’s classification of computer architecture. 2 4

(b) Describe SIMD architecture. 3 5

3. What are the different factors that can affect the performance of 5 2
pipeline system?

4. Why is the crossbar switch a non- blocking switch? 5 4

5. We have 2 designs D1 and D2 for a synchronous pipeline 5 1


processor. D1 has a 5 stage pipeline with execution time of 3 ns,
2 ns, 4 ns, 2 ns and 3 ns. While the design D2 has 8 pipeline stages
each with 2 ns execution time. How much time can be saved using
design D2 over design D1 for executing 100 instructions?

6. (a) How is it resolved in set associative cache memory? 2 4

(b) What is an Interconnection Network (ICN)? 3 5

Page 3 of 4
B.TECH. / CSE / R18 / EVEN / SEM-4 / CS401 / 2020-2021

GROUP – C
(Long Answer Type Questions)
Answer any three from the following: 3×15=45

Marks CO No.
7. (a) Explain set-associative mapping method with example. 5 3
(b) Explain VLIW architecture with proper diagram. 5 3
(c) Assume that main memory size is of 32 kb x 12. Cache memory 5 5
size is of 512x12 and block size is of 1 word. Describe the
following:
i) Direct mapping technique
ii) Associative mapping technique
8. (a) What is temporal vs. spatial locality? What is MIPS? 3+2 3
(b) Explain Superscalar processor with example and diagram. 5 3
(c) Explain cache coherence problem with diagram. 5 3

9. (a) Explain the working principle of a pipeline. 3 2


(b) What are the different types of hazards in pipelines? Explain 3+2 2
structural hazards.
(c) Consider the following reservation table: 2+3+2 2
1 2 3 4
S1 X X
S2 X
S3 X
Write down the forbidden latencies and initial collision vector.
What is Minimum average latency (MAL)?
10. (a) Describe Cache Coherency in Shared Memory architecture. 4 3
(b) Explain virtual memory. 3 3
(c) What is the significance of interconnection network in 3 3
multiprocessor architecture?
(d) Explain any one static interconnection network 5 3

11. Write short notes on any three of the following 3x5 =15
(a) Vector register architecture 5 3
(b) Omega network 5 4
(c) Array Processor 5 3
(d) DMA 5 4
(e) Direct Mapping 5 3

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