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Digital Design Verification IA-4: Name: Advika Priyabhashini DOS: 7/11/24 Sub: Minor Spec in VLSI

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0% found this document useful (0 votes)
11 views9 pages

Digital Design Verification IA-4: Name: Advika Priyabhashini DOS: 7/11/24 Sub: Minor Spec in VLSI

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advi.2003.ap
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© © All Rights Reserved
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DIGITAL DESIGN VERIFICATION

IA-4

Name: Advika Priyabhashini


DOS: 7/11/24
Sub: Minor Spec in VLSI

Class I Output:

 class_1 :: Value of x = 10
 class_1 :: Value of x = 20

Class 2 Output:
addr = 0

data = 0

write = 0

pkt_type =

Class 3 Output:
addr = 10

data = ff

write = 1

pkt_type = GOOD_PKT

Class 4 Output:
addr = 16

data = ff

write = 1

pkt_type = GOOD_PKT

Class 5 Output:
--------------------------------------

packet_id = 1
--------------------------------------

--------------------------------------

packet_id = 2

--------------------------------------

--------------------------------------

packet_id = 3

Class 6 Output:
--------------------------------------

3 packets created.

--------------------------------------

Class 7 Output:
Error-[SV-AMC] Non-static member access

testbench.sv, 19

$unit, "packet_id"

Illegal access of non-static member 'packet_id' from static method

'packet::display_packets_created'.

Class 8 Output:
--------------------------------------

3 packets created.

--------------------------------------

--------------------------------------

3 packets created.

--------------------------------------

Class 9 Output:
packet pkt_1;

pkt_1 = new();

packet pkt_2;

pkt_2 = pkt_1;

Class 10 Output:
****calling pkt_1 display****
---------------------------------------------------------

addr = 16

data = ff

write = 1

pkt_type = GOOD_PKT

---------------------------------------------------------

****calling pkt_2 display****

---------------------------------------------------------

addr = 16

data = ff

write = 1

pkt_type = GOOD_PKT

---------------------------------------------------------

****calling pkt_1 display****

---------------------------------------------------------

addr = 171

data = ff

write = 1

pkt_type = BAD_PKT

---------------------------------------------------------

Class 11 Output:
**** calling pkt_1 display ****

---------------------------------------------------------

addr = 10

data = ff

start_address = 10

end_address = 50

---------------------------------------------------------

**** calling pkt_2 display ****

---------------------------------------------------------

addr = 10
data = ff

start_address = 10

end_address = 50

---------------------------------------------------------

**** calling pkt_1 display after changing pkt_2 properties ****

---------------------------------------------------------

addr = 10

data = ff

start_address = 60

end_address = 80

---------------------------------------------------------

**** calling pkt_2 display after changing pkt_2 properties ****

---------------------------------------------------------

addr = 68

data = ff

start_address = 60

end_address = 80

---------------------------------------------------------

Class 12 Output:
**** calling pkt_1 display ****

---------------------------------------------------------

addr = 10

data = ff

start_address = 10

end_address = 50

---------------------------------------------------------

**** calling pkt_2 display ****

---------------------------------------------------------

addr = 10

data = ff

start_address = 10
end_address = 50

---------------------------------------------------------

**** calling pkt_1 display after changing pkt_2 properties ****

---------------------------------------------------------

addr = 10

data = ff

start_address = 10

end_address = 50

---------------------------------------------------------

**** calling pkt_2 display after changing pkt_2 properties ****

---------------------------------------------------------

addr = 68

data = ff

start_address = 60

end_address = 80

Class 12 Output:
Value of addr = 10 data = 20

Class 13 Output:
ext_class_1 ec_1 = new();

ext_class_2 ec_2 = new();

ext_class_3 ec_3 = new();

Class 14 Output:
Inside extended class 1

Inside extended class 2

Inside extended class 3

Class 15 Output:
Addr = 10

Data = 20

Class 16 Output:
real value is 6.720000

int value is 7

Class 17 Output:
Addr = 10

Data = 20

Class 18 Output:
"c = p;"

Expression 'p' on rhs is not a class or a compatible class and hence cannot

be assigned to a class handle on lhs.

Please make sure that the lhs and rhs expressions are compatible.

Class 19 Output:
Error- Illegal class variable access

testbench.sv,

Local member 'tmp_addr' of class 'parent_class' is not visible to scope

'encapsulation'.

Class 20 Output:
virtual_class, "p = new();"

Instantiation of the object 'p' can not be done because its type 'packet' is

an abstract base class.

Perhaps there is a derived class that should be used.

Class 21 Output:
Inside base_class

Class 22 Output:
Values are 20 10

Class 23 Output:
Addr = 10 Data = 20

Class 24 Output:
Error-[ECMDSMPD] Mismatched method definition

testbench.sv, 11

External class method definition should match prototype declaration.


Argument names do not match. The signature of function 'packet::display'

should match the corresponding prototype declaration at: "testbench.sv", 7.

Class 25 Output:
Error-[SE] Syntax error

Following verilog source has syntax error :

token 'c2' should be a valid type. Please declare it virtual if it

is an Interface.

"testbench.sv", 6: token is ';'

c2 c;

Class 26 Output:
addr1 = 6 addr2 = 4

addr1 = 4 addr2 = 3

addr1 = 2 addr2 = 0

addr1 = 6 addr2 = 6

addr1 = 1 addr2 = 7

addr1 = 3 addr2 = 5

addr1 = 7 addr2 = 1

addr1 = 6 addr2 = 2

addr1 = 4 addr2 = 7

addr1 = 4 addr2 = 6

Class 27 Output:
addr = 110 data = 116

Class 28Output:
addr = 0 data = 110

addr.rand_mode() = 0 data.rand_mode() = 1

Class 29 Output:
addr.rand_mode() = 1 data.rand_mode() = 1

addr = 0 data = 0

addr.rand_mode() = 0 data.rand_mode() = 0

Class 30 Output:
Inside pre_randomize

Inside post_randomize

value of addr = 110, data = 129

Class 31 Output:
addr = 14

addr = 10

addr = 9

addr = 8

addr = 9

addr = 6

addr = 10

addr = 14

addr = 12

addr = 8

Class 32 Output:
addr = 14

addr = 10

addr = 9

addr = 8

addr = 9

addr = 6

addr = 10

addr = 14

addr = 12

addr = 8

Class 33 Output:
------------------------------------

pkt1:: addr = 14

pkt1:: addr = 10

pkt1:: addr = 9

pkt1:: addr = 8
pkt1:: addr = 9

------------------------------------

pkt2:: addr = 0

pkt2:: addr = 1

pkt2:: addr = 2

pkt2:: addr = 0

pkt2:: addr = 2

------------------------------------

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