UNIT-5

ARM Processor
and Peripherals
 What is ARM Processor?
• ARM Stands for ‘ Advanced RISC Machine’
• It is a RISC Processor
• The First ARM processor actually was meant to be “Acorn
RISC Machine’
• ARM has been designed as a ‘Microprocessor’ and indeed it
is a processor which has very high computing capabilities.
• It has many features for handling complex computations.
• It is an SoC peripherals( System On Chip)
 It is used for small size and high performance applications.
 Simple architecture – low power consumption
 CISC
CISC - Stands for "Complex Instruction Set Computing." This
is a type of microprocessor design.
The CISC architecture contains a large set of computer
instructions that range from very simple to very complex and
specialized.
Characteristics of CISC
• Complex instruction, hence complex instruction decoding.
• Instruction are larger than one word size.
• Instruction may take more than single clock cycle to get
executed.
• Less number of general purpose register as operation get
performed in memory itself.
• Complex Addressing Modes.
• More Data types.
 RISC
• Reduced instruction set computing (RISC) is a computer that uses a
central processing unit (CPU) that implements the processor design
principle of simplified instructions. To date, RISC is the most efficient
CPU architecture technology.
• This architecture is an evolution and alternative to complex instruction
set computing (CISC). With RISC, the basic concept is to have simple
instructions that do less but execute very quickly to provide better
performance.

Characteristics of RISC
• Simpler instruction, hence simple instruction decoding.
• Instruction come under size of one word.
• Instruction take single clock cycle to get executed.
• More number of general purpose register.
• Simple Addressing Modes.
• Less Data types.
• Pipeline can be achieved.
ARM SoC Core with Peripherals
Architecture Versions
Features of the Architecture Variants of ARM
•
ARM
Advanced RISC Machine (ARM) is a processor architecture
based on a 32-bit reduced instruction set (RISC) computer.
• The ARM architecture is the most commonly implemented
32-bit instruction set architecture.
• ARM architecture is implemented on Windows, Unix, and
Unix-like operating systems, including Apple iOS, Android,
BSD, Inferno, Solaris, WebOS, Plan 9 and GNU/Linux.
• Advanced RISC Machine was originally known as Acorn RISC
Machine

ARM features include:

• Load/store-based architecture
• Single-cycle instruction execution
• Consistent 16x32 bit register file
• Link register
• Easy decoding and pipelining
• Power-indexed addressing modes
• Fixed 32-bit instruction set
 Features of ARM processor
• It has 32 bit data bus width, which means that it can
be read and write 32 bits in one cycle.
• The instruction set of ARM has been designed to
facilitate very good computational capability.
• Low power consumption. It operates at relatively low
frequencies from 60 MHz to 1 GHz.
• Pipelining is a fundamental idea in computer
architecture, for increasing speed of operation.
• It has multiple register instructions.
• This is a RISC processor but more advanced
members of the family have DSP instructions as an
enhanced feature.
 3 Stage Pipeline Organization
• 3-stage pipeline: Fetch – Decode - Execute
• Three-cycle latency,
one instruction per cycle throughput

i
n
s
i Fetch Decode Execute
t
r
u
i+1 Fetch Decode Execute
c
t
i i+2 Fetch Decode Execute
o cycle
n
10
t t+1 t+2 t+3 t+4
 5 Stage Pipeline Organization
• 5-stage pipeline: Fetch – Decode – Execute-
Buffer-Write

Fetch Decode Execute Buffer Write

 ARM7 TDMI Processor
• The ARM7TDMI processor is a member of the Advanced
RISC machine family of general purpose 32-bit
microprocessor

• What does mean ARM7TDMI ?

ARM7 - 32-bit Advanced RISC Machine
T - Thumb architecture extension
• Two separate instruction sets
32-bit ARM instructions
16-bit Thumb instructions
D - Debug extension
M - Enhanced multiplier
I - Embedded ICE macrocell extension
• 32-bit ARM instruction set
• 16-bit THUMB instruction set
• 32x8 Multiplier
 ARM Architecture
• Typical RISC architecture:
• Large uniform register file
• Load/store architecture
• Simple addressing modes
• Uniform and fixed-length instruction fields
 When used in relation to the ARM:
Byte means 8 bits
Half word means 16 bits (two bytes)
Word means 32 bits (four bytes)
 Most ARM’s implement two instruction sets
32-bit ARM Instruction Set
16-bit Thumb Instruction Set
14
 The ARM Register Set

 ARM has 37 registers all of which are 32-bits long.

• 1 dedicated program counter (PC)
• 1 dedicated current program status register (CPSR)
• 5 dedicated saved program status registers (SPSR)
• 30 general purpose registers
• 20 registers are hidden from program at different
times(Which are called as Banked Out Registers)
 It may be designated as ‘scratch pad’ registers. These are the
R0-R12
registers into which data and address are loaded.

It is the pointer to stack and it is used to the Stack pointer (SP)

R13

It is the link register. It is used whether there is a procedure call or an

interrupt, that is branching to a location. The value of PC is saved in the
R14
link register, and PC takes on the new branch address. It will store the
return address.

R15 It act as PC
 Operating Modes
• ARM has seven operating Modes
1. User Mode is the usual ARM program execution state, and is used
for executing most application programs.
2. Fast Interrupt (FIQ) mode supports a data transfer or channel
process.
3. Interrupt (IRQ) mode is used for general-purpose interrupt
handling.
4. Supervisor mode is a protected mode for the operating system.
5. Abort mode is entered after a data or instruction Prefetch Abort.
6. System mode is a privileged user mode for the operating system
7. Undefined mode is entered when an undefined instruction is
executed.
Modes other than User mode are collectively known as privileged modes. Privileged modes are used to
service interrupts or exceptions, or to access protected resources
Current Program Status Register (CPSR)
 Conditional Flag
N: Negative Flag : Indicates the status of the MSB of the result
of an operation. If we are dealing signed number N=1 Means
that the sign bit=1 which is a negative result.
C: Carry flag: There is an overflow from MSB of data being
manipulated.
Z: Zero Flag: If the result of ALU operation is zero Z=1
V: Overflow Flag: This is relevant only for signed operations.
Q: Sticky Overflow flag: This flag indicates overflow itself, but
it is sticky in the sense that it remains set until explicitly cleared.
Saved Program Status Register(SPSR) There are five SPSR,
that is one for each of he exception mode of operation. When an
exception that is an interrupt occurs the corresponding SPSR
saves the current CPSR value into it.
 Instruction Set

• Data Processing Instructions

• Load store Instructions - Single Register,
Multiple Register
• Branch Instructions
• Status register access Instructions
 Data Processing Instruction
It performs computations on data which are in registers only.
There are instructions which move data from one register to
another. Such instruction have only two operands that is source
and destination. Instruction which perform arithmetic/logical
operation have three operands , two source operands and one
destination operand.

Register Movement Operations

MOV, MOVN
MOV instruction is register to register data movement
instruction.
MOV destination,Source

MOVN Stands for "Move negated' Which implies moving the

complemented value of the source to destination.
MOVN destination,Source
 Data Processing Instruction Cont…

Example
MOV r0,r2 : r0:=r2
MVN r0,r2 : r0 := not r2
Arithmetic Operations
These instruction perform binary arithmetic(addition,
subtraction and reverse subtraction) on two 32 bit operands.
The operand may be unsigned 2’s complement signed integer,
the carry in when used the current value of C bit in CPSR.
ADD r0,r1,r2 r0:=r1+r2
ADC r0,r1,r2 r0:=r1+r2+c
SUB r0,r1,r2 r0:=r1-r2
SBC r0,r1,r2 r0:=r1-r2+c-1
 RSB r0,r1,r2 r0:=r2- r1 : Reverse Subtraction

RSC r0,r1,r2 r0:=r2-r1+c-1 : Reverse subtraction with carry

Bit Wise Logical Operation
This will perform Boolean logic operation.
AND r0, r1, r2 r0:=r1 and r2
ORR r0, r1, r2 r0:=r1 or r2
EQR r0, r1, r2 r0:=r1 xor r2
BIC r0, r1, r2 r0:=r1 and not r2 : Bit Clear
Comparison Operations
These instruction do not produce result.
CMP r1, r2 set cc on r1 – r2
CMN r1,r2 set cc on r1 + r2 | Compare Negated

TST r1, r2 set cc on r1 and r2 | Test bit

TEQ r1,r2 set cc on r1 xor r2 | Test equal
Immediate Operands
ADD r3, r3,#1 ; r3:= r3+1
AND r8,r7, #&ff ; r8 := r7 (7:0)
 Shifted Register Operands
A third way to specify a data operation is similar to the first, but
allows the second register operand to be subject to a shift operation before it
is combined with the first operand.
# indicate immediate quantity
LSL : logical shift left by 0 to 31 places
LSR : Logical shift right by 0 to 32 places
ASL : Arithmetic shift left this is similar for LSL
ASR : Arithmetic shift right 0 to 32 places
ROR : rotate right by 0 to 32 places
RRX : rotate right extended by 1 place; vacated bit filled with old value of C flag.

Example
ADD r5,r5,r3,LSL r2 ; r5:= r5+r3x 2r2
MUL r4,r3,r2 ; r4 : = (r3 x r2) ( 31:0)
MLA r4,r3,r2,r1 ; r4 := ( r3x r2+r1) ( 31:0)
 Load and Store Instruction
1. Single register load and store instruction
2. Multiple register load and store instruction.
Single register load and store instruction
These instruction compute an address for the transfer using a base
register, which should contain an address near to the target address, and an
offset which may be another register or an immediate value.

LDR r0, [r1] : r0:= mem 32[r1]

STR r0,[r1] : mem32[r1] :=r0
Multiple register data transfer
• IA – increment after
• IB increment before
• DA- decrement after
• DB – decrement before

LDMDA RO, (R4-R9) | Multiple Load

LDMIA RO, { R9, Rl - R5}
LDMIA r1, {r0,r2,r5} | r0 := Mem32 [r1]
r2 := mem32[r1+4]
r5 := mem 32 [r1+8]

STMIA Rl, (R2-R4} | Multiple Store

This will be equivalent to the instructions
STR R2, [Rl] STR R3, [R1. #4]
STR R4, [Rl.#8]]
Branch Instruction

Jump Instruction
Call instruction
RET instruction
Example
CMP r0, #5
BEQ Bypass
ADD r1, r1, ro
SUB r1,r1,r2
Bypass
 Status Register Instruction
• Application Program Status register (APSR)
• Interrupt Program Status register (IPSR)
• Execution Program Status register (EPSR)
Example
• MRS r0, APSR ; Read Flag state into R0
• MRS r0, IPSR ; Read Exception/Interrupt state
• MRS r0, EPSR ; Read Execution state
• MSR APSR, r0 ; Write Flag state
• MRS r0, PSR ; Read the combined program status word
• MSR PSR, r0 ; Write combined program state word
• MRS r0, PSR; Read the combined program status word
• MSR PSR, r0; Write combined program state word
 Stacks and Subroutines
For most processors, procedures use a stack to store the return
address. A procedure is taken up by a 'CALL' instruction. This
causes the action of pushing the current value od PC onto the
stack. The procedure end with the 'RETURN' instruction.
 In Such case a stack is a necessity. Each time a
procedure is called the PC value is saved in the LR as
is the usual case. When a nested procedure comes in
the content of the link register is pushed on to the
stack, and poped out from the stack when exiting the
procedure..
The main program has a procedure named
PROC1 which is called by the instruction BL PROC1.
This instruction causes the current PC value to be
copied to LR.
We Push LR and the working registers to stack
using the instruction
STMDB SP,[REGS,LR]
thus the content of LR is safely stored in the stack.
 Features of LPC 2148 Family Processor
• The core ARM 7TDMI-S in a tiny LQFP64 package.
• 8 KB to 40 KB of on-chip static RAM.
• 32 KB to 512 KB of on-chip flash memory.
• 128-bitwide interface/accelerator enables high-speed 60MHz operation.
• USB 2.0 Full-speed compliant device controller with 2 KB of endpoint RAM. In addition,
provides 8 KB of on-chip RAM accessible to USB by DMA.
• 10-bit ADCs provide a total of 6/14 analog inputs.
• Single 10-bit DAC provides variable analog output (LPC2142/44/46/48 only).
• Two 32-bit timers/external event counters (with four capture and four compare channels
each), PWM unit (six outputs) and watchdog.
• Low power real-time clock (RTC) with independent power and 32 kHz clock input.
• Multiple serial interfaces including two UARTs (16C550), two fast 1 2C-bus (400 Kbit/s), SPI
and SSP with buffering and variable data length capabilities.
• Vectored interrupt controller (VlC) with configurable priorities and vector addresses.
• Up to 45 of 5 V tolerant fast general purpose I/O pins in a tiny LQFP64 package.
• Up to 21 external interrupt pins available.
• 60 MHz maximum CPU clock available from programmable on-chip PLL.
• On-chip integrated oscillator operates with an external crystal from 1 MHz to 25MHz.
• Power saving modes include idle and power-down.
• Processor wake-up from power-down mode via external interrupt or BOD.
• Single power supply chip with POR and BOD circuits.
Architecture of LPC 2148
Memory
The memory available includes up to 40KB static RAM and
512KB flash. In the case of 8KB Static RAM block intended to be
utilized mainly by the USB can also be used as a general purpose
RAM for data storage and code storage and execution,
Memory Map
Total memory space is 4GB.It is a memory mapped I/O
system in which peripherals and memory share the same memory
space.
System Functions
• It will include a crystal oscillator and PLL.
• The oscillator frequency can be in the range of 10 to 25 MHz
which can be multiplied up, to get a system frequency up to 60
MHz using PLL.
Reset
There are two ways of resetting
- Hard reset using the active low reset pin
- Soft reset using watchdog timer.
Power Control
It is a low power dissipation.
There are 2 Modes of operation

Idle Mode
In the idle mode, instruction execution is suspended until
either a reset or interrupt occurs.

Power Down Mode

In the power-down mode, the oscillator is shut down and
the chip receives no internal clocks.

Internal Bus
- AMBA Bus
- VPB Bus
AMBA BUS
AMBA stands for
Advanced Microcontroller Bus Architecture.
In a number of buses can be seen which from part of AMBA.
The fastest bus is the system or the local bus which connects
the processor core with memory as memory access have to be
very fast.

VPB Bus
It shows that there is a bridge that interface between the VPB
and AHB ( Advanced High performance Bus). There is a VPB
divider. This is a register whose settings can be used to divide
the output frequency of PLL to get reduced clock frequency
(1/2 to 1/4) for the VPB peripherals.
Memory Accelerator Module
 Peripherals

GPIO (General Purpose I/O)

There are two general purpose 32 bit ports, P0, P1.
 Timer Unit
This means that a counter is used to count external
events via the capture inputs. A Counter is also called
a 'Capture timer'.
There are two such units Timer 0, Timer 1. There are a
number of registers associated with timer operations.
The first step in timer operation is to load a number
into what is called a 'Match register'. Then a timer
count register is started. This register keeps
incrementing for each PCLK cycle or a lower rate
prescaled cycle.
 Important SFRs of Timer 0
Timer Count Register - TOTC
It is a 32 bit register, which gives it a range of counting
from 0 to 0xFFFF FFFF and then wraps back to the value
0x0000 0000. This register is used to increment on every tick of
clock.
Timer Control Register - TOTCR
It is a 8 bit register in which only the lowest two bits need
be used.
Match Register(MR0 to MR3)
There are four 32 bit match register available MR0 to
MR3.
Match Control Register- T0MCR
It is a 16 bit register used to specify the event to occur
when the match occurs.
 Pulse Width Modulation
Pulse width modulation is basically a scene in
which it is possible to control the period and
duty cycle of a square wave. The duty cycle is
defined as the ratio of the ON time of the pulse
and the period expressed as a %.
UART
ARM Cortex 3 Processor