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Module4-1

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Module 4

Procedural Statements and


Routines
Prepared
By
Jagannath B R
Assistant Professor
Department of ECE
VVIET
Procedural Statements and Routines

3.1 Introduction

• As you verify your design, you need to write a great deal of code, most of which
is in tasks and functions.
• System Verilog introduces many incremental improvements to make this easier
by making the language look more like C, especially around argument passing
Functions
The primary purpose of a function is to return a value that can be used in an expression
and cannot consume simulation time.
•A function cannot have time controlled statements like @, #, fork join, or wait
•A function cannot start a task since tasks are allowed to consume simulation time
Returning a value
The function definition will implicitly create an internal variable of the
same name as that of the function. Hence it is illegal to declare another
variable of the same name inside the scope of the function. The return
value is initialized by assigning the function result to the internal variable

Sum =a+b
Function Rules
•A function cannot contain any time-controlled
statements like #, @, wait, posedge, negedge
•A function cannot start a task because it may
consume simulation time, but can call other
functions
•A function should have atleast one input
•A function cannot have non-blocking assignments
or force-release or assign-deassign
•A function cannot have any triggers
•A function cannot have an output or inout
Recursive Functions
Functions that call itself are called recursive
functions.
In the example shown below, a recursive
function is written to compute the factorial of
a given number.
Task
A function is meant to do some processing on the input and return a single
value, whereas a task is more general and can calculate multiple result
values and return them using output and inout type arguments.
Tasks can contain simulation time consuming elements such
as @, posedge and others.

Syntax
A task need not have a set of arguments in the port list, in which case it can
be kept empty.
// Style 1
Static Task
If a task is static, then all its member variables will be shared across different
invocations of the same task that has been launched to run concurrently

The task-enabling arguments (x, y, z)


correspond to the arguments (a, b, c) defined
by the task. Since a and b are inputs, values
of x and y will be placed
in a and b respectively. Because c is declared
as an output and connected with z during
invocation, the sum will automatically be
passed to the variable z from c.
Automatic Task
The keyword automatic will make the task reentrant,
otherwise it will be static by default. All items
inside automatic tasks are allocated dynamically for each
invocation and not shared between invocations of the
same task running concurrently. Note that automatic task
items cannot be accessed by hierarchical references.
For illustration, consider the static task display which is
called from different initial blocks that run concurrently.
In this case, the integer variable declared within the task
is shared among all invocations of the task and hence
thev displayed value should increment for each
invocation.
Global Tasks
Tasks that are declared outside all modules are
called global tasks as they have a global scope and can be
called within any module.
Function Task
Cannot have time-controlling Can contain time-controlling
statements/delay, and hence statements/delay and may
executes in the same only complete at some other
simulation time unit time
Cannot enable a task, Can enable other tasks and
because of the above rule functions
Should have atleast one input
Can have zero or more
argument and cannot have
arguments of any type
output or inout arguments
Cannot return a value, but
Can return only a single value can achieve the same effect
using output arguments
Tasks can be disabled using the disable keyword.
3.2 Procedural Statements
 System Verilog adopts many operators and statements from C and C++.
 You can declare a loop variable inside a for loop that then restricts the scope of the loop variable
and can prevent some coding bugs.
 The increment ++ and decrement -- operators are available in both pre- and post- form.

 A label on a begin or fork statement, you can put the same label on the matching end or join
statement.
 This makes it easier to match the start and finish of a block.
 You can also put a label on other System Verilog end statements such as endmodule, endtask,
endfunction, and others that you will learn in this book.
 Example 3-1 demonstrates some of the new constructs.
3.3 Tasks, Functions, and Void Functions

 Verilog makes a very clear differentiation between tasks and functions.


 The most important difference is that a task can consume time while a
function cannot.
 A function cannot have a delay, #100, a blocking statement such as @(posedge
clock) or wait(ready), or call a task.
 Additionally, a Verilog function must return a value, and the value must be
used, as in an assignment statement.
 In SystemVerilog, if you want to call a function and ignore its return value, cast
the result to void.
 This might be done if you are calling the function to use a side effect.
If you have a System Verilog task that does not consume time, you
should make it a void function that is a function that does not
return a value. Now it can be called from any task or function.
3.4 Task and Function Overview SystemVerilog makes several small improvements to tasks and functions
to make them look more like C or C++ routines
3.5 Routine Arguments
Many of the SystemVerilog improvements for routine make it easier to declare arguments and
expand the ways you can pass values to and from a routine.
3.5.1 C-style Routine Arguments
SystemVerilog and Verilog-2001 allow you to declare task and function arguments more cleanly
and with less repetition.
The following Verilog task requires you to declare some arguments twice, once for the direction,
and once for the type
3.5.2 Argument Direction
You can take even more shortcuts with declaring routine arguments.
The direction and type default to “input logic” and are sticky, so you don’t have to repeat these for similar
arguments. Here is a routine header written using the Verilog-1995 style.
3.5.3 Advanced Argument Types
Verilog had a simple way to handle arguments: an input or inout was copied to a local variable at the start of
the routine, while an output or inout was copied when the routine exited. No memories could be passed into a
Verilog routine, only scalars.
SystemVerilog, you can specify that an argument is passed by reference, rather than copying its value. This
argument type, ref, has several benefits over input, output, and inout. First, you can now pass an array into a
routine.

SystemVerilog allows you to pass array arguments without the ref direction, but the array is copied onto the stack, an
expensive operation for all but the smallest arrays
Example 3-10 also shows the const modifier.
 a result, the array a is initialized when print_sum is called, but cannot be modified in the routine.
 Always use ref when passing arrays to a routine. If you don’t want the routine to change the array values, use
the const ref type. With this, the compiler checks that your routine does not modify the array.
 The second benefit of ref arguments is that a task can modify a variable and is instantly seen by the calling
function. This is useful when you have several threads executing concurrently and want a simple way to pass
information.
3.5.4 Default Argument Values
In System Verilog you can specify a default value that is used if you leave out an
argument in the call
3.5.4 Default Argument Values
3.5.5 Common Coding Errors
The most common coding mistake that you are likely to make with a routine is forgetting that
the argument type is sticky with respect to the previous argument, and that the default type
for the first argument is a single-bit input. Start with the following simple task header.

The two arguments are input integers. As you are writing the task, you realize that you need access
to an array, so you add a new array argument, and use the ref type so it does not have to be copied
What argument types are a and b? They take the direction of the previous argument that is a ref. Using ref for a simple
variable such as an int is not usually needed, but you would not get even a warning from the compiler, and thus would
not realize that you were using the wrong type

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