The Processor

Lecture #10
Computer Organization and Assembly Language
A Basic MIPS Implementation
• This chapter contains an explanation of the principles and
techniques used in implementing a processor
• We will be examining an implementation that includes a
subset of the core MIPS instruction set:
• The memory-reference instructions load word (lw) and store word
(sw)
• The arithmetic-logical instructions add, sub, AND, OR, and slt
• The instructions branch equal (beq) and jump (j)
• What will not be covered in subset of core MIPS?
• It does not include all the integer instructions
• For example, shift, multiply, and divide are missing
• It does not include any floating-point instructions
• However, it illustrates the key principles used in creating a
datapath and designing the control
A Basic MIPS Implementation
• What will we be focusing?
• How the instruction set architecture determines many
aspects of the implementation
• How the choice of various implementation strategies affects
the clock rate and CPI for the computer
• Most concepts used to implement the MIPS subset are
the same that are used to construct a broad spectrum
of computers
• For example, high-performance servers, general-purpose
microprocessors and embedded processors
An Overview of the Implementation
• What are the first two common step in executing an
instruction?
• For every instruction, the first two steps are identical:
1. Send the program counter (PC) to the memory that
contains the code and fetch the instruction from that
memory
2. Read one or two registers, using fields of the instruction to
select the registers to read
1. For the load word instruction, we need to read only one register
2. However, for most other instructions require reading two registers
An Overview of the Implementation
• What are the next steps in instruction execution and are they identical?
• After first two steps, the actions required to complete the instruction depend
on the instruction class
• For example, for each of the three instruction classes (memory-reference,
arithmetic-logical, and branches), the actions are largely the same,
independent of the exact instruction
• In this stage, arithmetic-logical instructions perform their operation (e.g., addition,
subtraction, bitwise operations) on the operands
• Memory-reference instructions calculate the effective memory address (e.g., by adding
an offset to a base register)
• Branch instructions evaluate the branch condition and determine whether to take the
branch
• While the specific operations differ between instruction classes, they all involve some
form of computation or decision-making
• The simplicity and regularity of the MIPS instruction set simplifies the
implementation by making the execution of many of the instruction classes
similar
• For example, all instruction classes, except jump, use the arithmetic-
logical unit (ALU) after reading the registers
• The memory-reference instructions use the ALU for an address
calculation, the arithmetic-logical instructions for the operation
An Overview of the Implementation
• What is the next step after using ALU?
• The actions required to complete various instruction classes
differ. For example,
• A memory-reference instruction will need to access the memory
either to read data for a load or write data for a store
• An arithmetic-logical or load instruction must write the data from
the ALU or memory back into a register
• A branch instruction may need to change the next instruction address
based on the comparison
• Otherwise, the PC should be incremented by 4 to get the address of the
next instruction
An Overview of the Implementation
• Previous figure shows the high-level view of a MIPS
implementation, focusing on the various functional
units and their interconnection.
• Although this figure shows most of the flow of data
through the processor, it omits two important aspects
of instruction execution
• Lets observe in the next slides
 An Overview of the Implementation
Explanation
• Program Counter
• All instructions start by using the program counter to supply the
instruction address to the instruction memory
• PC always starts from Zero
• Instruction Fetch
• After the instruction is fetched, the register operands used by an
instruction are specified by fields of that instruction
• Operation
• Once the register operands have been fetched, they can be operated on
to compute a memory address (for a load or store), to compute an
arithmetic result (for an integer arithmetic-logical instruction), or a
compare (for a branch)
• If the instruction is an arithmetic-logical instruction, the result from
the ALU must be written to a register
• If the operation is a load or store, the ALU result is used as an address
to either store a value from the registers or load a value from memory
into the registers. The result from the ALU or memory is written back
into the register file
• Branches require the use of the ALU output to determine the next
instruction address, which comes either from the ALU (where the PC
and branch offset are summed) or from an adder that increments the
current PC by 4
• Block Diagram
• The thick lines interconnecting the functional units represent buses,
which consist of multiple signals.
• The arrows are used to guide the reader in knowing how information
flows.
An Overview of the Implementation
• First Omission: It can be
observed that the data going to
a particular unit as coming from
two different sources. For
example,
• The value written into the PC can
come from one of two adders,
• The data written into the register
file can come from either the ALU
or the data memory
• The second input to the ALU can
come from a register or the
immediate field of the instruction
• Can these data line be wired
together?
• No. These data lines cannot simply
be wired together
• What could be the solution?
• A multiplexor or data selector can
choose among the multiple sources
and steers one of those sources to
its destination
An Overview of the Implementation
• Second omission is
control unit which
depends on the type of
instruction. For example,
• The data memory must
read on a load
• The data memory must
write on a store
• The register file must be
written only on a load or
an arithmetic-logical
instruction
• The ALU must perform
one of several operations
such as AND, OR, add, sub
etc.
An Overview of the Implementation
• MIPS subset with following
changes:
• Three multiplexors added
• Control lines
• A control unit
• Input: Instruction is used to
determine how to set the
control lines for the functional
units and two of the
multiplexors.
• How the third multiplexor
is being controlled?
• The third multiplexor which
determines whether PC + 4 is not
branch instruction
• If there is branch instruction beq,
then branch destination address is
written into the PC. This is done by
setting Zero output of ALU.
• Remember Zero is a flag register in
MIPS and it contains ‘1’ when result
is zero
.
An Overview of the Implementation
• What is the purpose of top multiplexor?
• It controls what value replaces the PC
• Either PC + 4 or the branch destination address
• It is controlled by AND gate together with Zero Flag output of the ALU and a
control signal that indicates that the instruction is a branch
• What is the purpose of middle multiplexor?
• It returns output to the register file in case of Arithmetic-Logical Instruction
or the output of the data memory (in the case of a load) for writing into the
register file
• What is purpose of bottommost multiplexor?
• It determines whether the second ALU input is from the registers (for an
arithmetic-logical instruction or a branch) or from the offset field of the
instruction (for a load or store)
• Control Lines determines
• The operation performed at the ALU
• Whether the data memory should read or write
• Whether the registers should perform a write operation
An Overview of the Implementation
• In this first design, every instruction begins execution
on one clock edge and completes execution on the next
clock edge.
• While easier to understand, this approach is not
practical, since the clock cycle must be severely
stretched to accommodate the longest instruction
• After designing the control for this simple computer,
we will look at pipelined implementation with all its
complexities, including exceptions.
Logic Design Conventions
• There are two important aspects to know while
implementing computer
1. How the hardware logic implementing the computer will operate?
2. How is the computer clocked?
• The data path elements in the MIPS implementation
consist of two different types of logic elements
1. Combinational elements that operate on data values
2. State elements that contain state
• What are combinational elements?
• Those elements whose outputs depend only on the current inputs
• Given the same input, a combinational element always produces the same
output
• For example, ALU is a combinational element. Given a set of inputs,
it always produces the same output because it has no internal
storage
Logic Design Conventions
• What are state elements?
• A state element has some internal storage
• If the computer lost power, we could restart it accurately by
loading the state elements with the values they contained
before restart
• If we saved and restored the state elements, it would be as if
the computer had never lost power
• Thus, these state elements completely characterize the
computer
• For example, the instruction memory, data memory,
registers are all examples of state elements
Logic Design Conventions
• How many essential inputs and outputs of state element?
• It has at least two inputs and one output
• Input: Data value and Clock
• What is the purpose of the clock?
• It determines when the data value is written
• For example, the output from a state element provides the value that was
written in an earlier clock cycle
• For example, a D-type flip-flop has exactly two inputs (a value and a
clock) and one output
• MIPS implementation uses two other types of state elements:
1. Memories
2. Registers
• The clock is used to determine when the state element should be
written
• a state element can be read at any time
Logic Design Conventions
• State elements are also called sequential
• Because their outputs depend on both their inputs and the
contents of the internal state
• For example, the output from the functional unit
representing the registers depends both on the register
numbers supplied and on what was written into the
registers previously
Clocking Methodology
• What is a clocking methodology?
• It defines when signals can be read and when they can be
written
• Why is important to specify the timing of reads and
writes?
• Because if a signal is written at the same time it is read, the
value of the read could correspond to the old value, the newly
written value, or even some mix of the two
• Computer designs cannot tolerate such unpredictability
• A clocking methodology is designed to make hardware
predictable
Clocking Methodology
• For simplicity, we will assume an edge-triggered clocking
methodology
• What is an edge-triggered clocking methodology?
• It means that any values stored in a sequential logic element are
updated only on a clock edge, which is a quick transition from low
to high or vice versa
• Because only state elements can store a data value, any
collection of combinational logic must have its inputs come
from a set of state elements and its outputs written into a
set of state elements
• The inputs are values that were written in a previous clock
cycle, while the outputs are values that can be used in a
following clock cycle.
Clocking Methodology
Explanation
• Previous Figure shows the two state elements surrounding a
block of combinational logic, which operates in a single
clock cycle
• All signals must propagate from state element 1, through the
combinational logic, and to state element 2 in the time of one
clock cycle
• The time necessary for the signals to reach state element 2 defines
the length of the clock cycle
• For simplicity, we do not show a write control signal when
a state element is written on every active clock edge
• In contrast, if a state element is not updated on every clock,
then an explicit write control signal is required
• Both the clock signal and the write control signal are inputs,
and the state element is changed only when the write
control signal is asserted and a clock edge occurs.
Clocking Methodology
Explanation
• We will use the word asserted to indicate a signal that is logically high
and assert to specify that a signal should be driven logically high, and
deassert or deasserted to represent logically low
• We use the terms assert and deassert because when we implement
hardware, at times 1 represents logically high and at times it can
represent logically low
• An edge-triggered methodology allows us to read the contents of a
register, send the value through some combinational logic, and write
that register in the same clock cycle
• Next Figure 4.4 gives a generic example. It doesn’t matter whether we
assume that all writes take place on the rising clock edge (from low to
high) or on the falling clock edge (from high to low), since the inputs
to the combinational logic block cannot change except on the chosen
clock edge
• In this book we use the rising clock edge
• With an edge-triggered timing methodology, there is no feedback
within a single clock cycle, and the logic in Figure 4.4 works correctly.
Clocking Methodology
Explanation
• For the 32-bit MIPS architecture, nearly all of these state
and logic elements will have inputs and outputs that are
32 bits wide, since that is the width of most of the data
handled by the processor
• The figures will indicate buses, which are signals wider than 1 bit,
with thicker lines
• At times, we will want to combine several buses to form a
wider bus; for example, we may want to obtain a 32-bit
bus by combining two 16-bit buses
• In such cases, labels on the bus lines will make it clear that we are
concatenating buses to form a wider bus. Arrows are also added to
help clarify the direction of the flow of data between elements
• Finally, color indicates a control signal as opposed to a signal that
carries data; this distinction will become clearer as we proceed
through this chapter.