1) 2 to 4 decoder

module decoder2to4(a,enable,y);
input enable;
input [1:0] a ;
output [3:0] y;
reg [3:0] y;
always @(a,enable)
begin
if (enable==1'b1)
begin
case(a)
2'b00:y = 4'b0001;
2'b01:y = 4'b0010;
2'b10:y = 4'b0100;
2'b11:y = 4'b1000;
endcase
end
else
y=4'bZZZZ;
end
endmodule
2) 8 to 3 encoder
module enc_wop(en,a,b);
input en;
input[0:7]a;
output[2:0]b;
reg[2:0]b;
always @
(en,a)
begin
if (en==1'b1)
begin
case (a)
8'b 00000001 :b=3'd7;
8'b 00000010 :b=3'd6;
8'b 00000100 :b=3'd5;
8'b 00001000 :b=3'd4;
8'b 00010000 :b=3'd3;
8'b 00100000 :b=3'd2;
8'b 01000000 :b=3'd1;
8'b 10000000 :b=3'd0;
default:b=3'bz;
endcase
end

else if (en==1'b0)
b=3'bz;
end
endmodule
3) Encoder with priority

module Encoder8to3ver(en,a,b);
input en;
input [0:7] a;
output [2:0] b;
reg [2:0] b;
always @(en,a)
begin
if(en==1)
begin
casex(a)
8'bXXXXXXX1:b=3'd7;
8'bXXXXXX10:b=3'd6;
8'bXXXXX100:b=3'd5;
8'bXXXX1000:b=3'd4;
8'bXXX10000:b=3'd3;
8'bXX100000:b=3'd2;
8'bX1000000:b=3'd1;
8'b10000000:b=3'd0;
endcase
end
else
b=3'dZ;
end
endmodule
4) 8:1 Multiplexer
module mux8x1(i, y,
s); input [7:0] i;
outputreg y;
input [2:0] s;
always @
(s,i) begin
case (s)
3'd0: y = i[0];
3'd1: y = i[1];
3'd2: y = i[2];
3'd3: y = i[3];
3'd4: y = i[4];
3'd5: y = i[5];
3'd6: y = i[6];
default:y = i[7];
endcase
end

endmodule
 5) 2:1 Multiplexer

module MUX2_1 (A, B, SEL, En, Y);

input A, B, SEL,
En; output Y;
reg Y;
always @ (SEL, A, B,
En) begin
if (En == 0 & SEL == 1)
begin
Y = B;
end
else if (En == 0 & SEL == 0)
Y = A;
else
Y = 1'bz;
end
endmodule

6) Binary to Gray code conversion

Module bintogrey(b,g);
input [3:0] b;
output [3:0] g;
wire [3:0] g;
assign g[3] = b[3];
assign g[2:0] = b[3:1] ^
b[2:0]; endmodule
7) 1:8 Demultiplexer
module Demux1to8 (i, y,
s); input i;
outputreg [7:0] y;
input [2:0] s;
always @
(s,i) begin
case (s)
3'd0: y[0] = i;
3'd1: y[1] = i;
3'd2: y[2] = i;
3'd3: y[3] = i;
3'd4: y[4] = i;
3'd5: y[5] = i;
3'd6: y[6] = i;
default: y[0] =
i; endcase
end
endmodule
8) 4 bit Comparator
module comparator(a,b,x,y,z);
input [3:0] a;
input [3:0]
b; output x;
output y;
output z;
regx,y,z;
always @(a , b)
begin
x =
1'b0; y
= 1'b0; z
= 1'b0;
if(a < b)
x = 1'b1;
else if(a == b)
y = 1'b1;
else if(a > b)
end z = 1'b1;
endmodule
9) Full adder circuit using dataflow model
module full_adder_dataflow (a,b,cin,sum,carry);
inputa,b,cin;
outputsum,carry;
assign sum =a ^ b ^ cin;
assign carry =(a&b) | (b&cin) | (cin&a);
endmodule
10) Verilog- code to implement Full Adder in by instantiating Half adder
and logic gate
module full_adder_struct (a,b,cin,sum,carry);
inputa,b,cin;
outputsum,carry;
wirep,q,r;
half_adder A1 (a,b,p,q);
half_adder A2 (p,cin,sum,r);
or (carry,q,r);
endmodule

module half_adder (a,b,sum0,carry0);

inputa,b;
output sum0,carry0;
xor (sum0,a,b);
and (carry0,a,b);
endmodule
11) 4-Bit ALU
module alu(a,b,opcode,enable,y, prod);
input [3:0] a,b;
input enable;
input [3:0] opcode;
output [4:0] y;
output [7:0] prod;
reg [4:0] y;
reg [7:0] prod;
always @ (a,b,enable,opcode)
begin
if(enable==1)
begin
case(opcode)
4'b0000 : y=a+b;
4'b0001 : y=a-b;
4'b0010 : prod=a[3:0]*b[3:0];
4'b0011 : y=~a;
4'b0100 : y=a&b;
4'b0101 : y=a|b;
4'b0110 :y=~(a&b);
4'b0111 :y=~(a|b);
4'b1000 :y=(a^b);
default :y=5'bx;
endcase
end
else
y=5'bz;
end
endmodule
12) Verilog code to implement SR- FLIP-FLOP

module srff(q,q1,r,s,clk);
output q,q1;
input r,s,clk;
reg q,q1;
initial
begin
q=1'b0;
q1=1'b1;
end
always @(posedge clk)
begin
case({s,r})
{1'b0,1'b0}: begin q=q; q1=q1; end
{1'b0,1'b1}: begin q=1'b0; q1=1'b1; end
{1'b1,1'b0}: begin q=1'b1; q1=1'b0; end
{1'b1,1'b1}: begin q=1'bx; q=1'bx; end
endcase
end
endmodule

13)Verilog code for D flip-flop.

moduledff (d,clk,q,qb);
inputd,clk;
outputregq,qb;
always @
(d,clk) begin
if(clk==1)
begin
q=d;
qb=~d;
end
end
endmodule
14) Verilog code to implement JK- Flip Flop.

module jk(q,q1,j,k,c);
output q,q1;
input j,k,c;
reg q,q1;
initial begin q=1'b0; q1=1'b1; end
always @ (posedge c)
begin
case({j,k})
{1'b0,1'b0}:begin q=q; q1=q1; end
{1'b0,1'b1}: begin q=1'b0; q1=1'b1; end
{1'b1,1'b0}:begin q=1'b1; q1=1'b0; end
{1'b1,1'b1}: begin q=~q; q1=~q1; end
endcase
end
endmodule