Lê Thành Nam_104999380 Faculty of Science, Engineering and Technology

Computer Systems
Week 3
Overview
In this laboratory session we start using Flip Flops to build useful things like counters
registers, and shift registers.
Purpose: To consolidate your knowledge of Flip Flops, and how they can be used.
Task:

Time: This lab is due by the start of your week 3 lab.

Assessment: This lab is worth 1% (up to a maximum of 5%) of your assessment
for this unit, and only if demonstrated to your lab demonstrator in the
week it is due.
Resources: ■ Flip Flop tutorials
■
Intro to Flip Flops

Submission Details
You must submit the following files to Canvas:
■
A document containing all required work as described below.
 Computer Systems Week 3 Laboratory

Instructions

1. Start Logisim and open a new canvas

Part 1: Storing bits with Flip Flops

Any computing hardware that seeks to perform meaningful calculations using bits
requires cir- cuitry to store them - that is, circuits that can maintain a given state. In
lectures we discussed Flip Flops, which are simple block circuits designed to maintain
a particular binary state, and transition between binary states depending on the inputs
given.
2. Review this week’s lecture slides, and if needed, also take a look at the quick
video tutori- als linked under resources at the beginning of this lab sheet.
3. Create a clear canvas.
4. Using the lecture slides as a guide, wire up your own R-S Flip Flop using a pair
of 2-input NOR gates (do not use Logisim’s S-R Flip-Flop!). You should
have 2 input pins, one for the “Set” pin, and one for the “Reset”, and two output
LEDs: Q and Q’ .
5. When you’ve finished wiring it up, set both input pins to 1. The LEDs should
both be dark (assuming you’ve wired it correctly).
Export your circuit as an image and include it in your submission document.

6. Set the pins in the following order and record the states for Q and Q’
Set Reset Q Q’

1 0 1 0
1 1 0 0
0 1 0 1
1 1 0 0

1. Case 1: Set = 1; Reset = 0

Page 2 of
16
 Computer Systems Week 3 Laboratory

2. Case 2: Set = 1; Reset = 1

3. Case 3: Set = 0; Reset = 1

4. Case 4: Set = 1; Reset = 1

Page 3 of
16
Computer Systems Week 3 Laboratory

7. Describe in a sentence, the behaviour of the circuit when one of the inputs is 1
(but not both) and why this is useful for digital circuit design.

- When one input of the R-S flip-flop is 1 (Set or Reset), but not both, the circuit sets or
resets the output Q to 1 or 0 respectively, while maintaining a stable state until the next
input change; this is useful in digital circuit design for reliably storing and controlling
binary data with clear and predictable state transitions.

8. What do you notice about the two times you set both inputs to 1. Briefly
explain what is happening here and why this is an issue for digital circuit
design ?
- When both inputs of the R-S flip-flop are set to 1 simultaneously, both outputs
(Q and Q') are forced to 0, which creates an undefined or invalid state because Q
and Q' are supposed to be complementary (one should always be the inverse of
the other). This is an issue for digital circuit design because it breaks the
fundamental rule of flip-flop behavior, leading to unpredictable circuit
performance, potential data loss, and malfunctioning of sequential logic systems
that rely on stable and defined outputs.
Discuss 7 and 8 with your lab demonstrator and provide your answer in your
submis- sion document, along with the truth table in Step 6.

Page 4 of
16
 Computer Systems Week 3 Laboratory

9. So the unclocked R-S flip flop has issues. Lets talk about the D Flip-Flop then.
Review the lectures on the D Flip-Flop, and when you feel comfortable, wire up
a D Flip Flip using AND gates and NOR gates, with output LEDS labeled Q and
Q’.
■
For this you will have only 1 input pin, as well as a clock input. The clock can
be pulsed on and off by clicking it with the operation pointer (the finger in the
top left of screen), or you can simple enable clock ticking from the menu
(under “Simulate”).
Export your circuit as an image and include it in your submission document.
10. Explore the behaviour of the D Flip Flop by filling out the following truth table
Clock Pin Q Q’

0 0 0 1
0 1 0 1
1 1 1 0
1 0 0 1

1. Case 1: Clock = 0; Pin = 0

2. Case 2: Clock = 0; Pin = 1

3. Case 3: Clock = 1; Pin = 1

Page 5 of
16
 Computer Systems Week 3 Laboratory

4. Case 4: Clock = 1; Pin = 0

11. Briefly explain the behaviour of a D Flip Flop and how it is useful for digital circuit
design.

- Behaviour:

A D Flip-Flop stores the value of the D input at the moment of the clock's edge (usually rising
edge) and outputs it at Q, keeping Q stable until the next clock pulse. This predictable behavior
makes it ideal for data storage and synchronization in digital circuits.

- Usefulness:

 Data Latching: Holds data until the next clock pulse, making it useful for registers and
memory.
 Edge-Triggered Operation: Synchronizes data with the clock signal, ensuring reliable
timing.
 Simplifies Circuit Design: Only one data input (D) eliminates uncertain states, making
sequential logic design straightforward and efficient.

12. What is the role of the clock? How does it impact the changing of state of Q and Q’?

Role of the Clock:

Page 6 of
16
 Computer Systems Week 3 Laboratory
 Synchronizes State Changes: The clock signal controls when the flip-flop reads the
input values and updates the outputs, usually on the rising or falling edge of the clock
pulse.

Impact on Q and Q’:

 State Transition Control: The flip-flop only updates Q and Q' during a clock edge
(rising or falling). Without a clock edge, Q and Q' remain unchanged regardless of input
values.
 Predictable Timing: This edge-triggered behavior allows flip-flops to change state only
at specific moments, preventing erratic changes and maintaining data integrity within
sequential circuits.

13. Why is it generally preferred over the R-S Flip Flop?

The D Flip-Flop is generally preferred over the R-S Flip-Flop because it simplifies circuit
design and avoids potential issues associated with R-S flip-flops. Here’s why:

Eliminates Invalid States: The RS flip-flop has an undefined state when both R (Reset)
and S (Set) inputs are 1 simultaneously. The D flip-flop, with its single data input (D),
avoids this issue entirely, making it more reliable.

Simplified Input: The D flip-flop has only one input (D) compared to the RS flip-flop's
two inputs (R and S), making it simpler to use in designs since you only need to control
one signal.

Predictable Behavior: The D flip-flop directly transfers the D input to the output Q on a
clock edge, leading to a straightforward and predictable operation. This is more intuitive
than the RS flip-flop, where the behavior depends on the combination of R and S inputs.

Data Synchronization: D flip-flops are excellent for synchronizing data with clock
signals, making them ideal for applications like registers, counters, and memory
elements where data integrity and precise timing are crucial.

Discuss 11 -13 with your lab demonstrator and provide your answer in your submission
document, along with the truth table above.

14. J-K Flip Flops are like your general purpose Flip Flop because they are
programmable. Review the video on JK Flip Flops, and when you’re feeling
comfortable, wire up a J-K FF using NAND gates. Two of your NAND gates
will need to deal with three inputs.
Logisim will not be able to simulate this circuit, but export your completed circuit
as an image and include it in your submission document.

Page 7 of
16
Computer Systems Week 3 Laboratory

15. Complete and include this truth table for JK Flip Flops in your
submission docu- ment.
J K Q (when clocked) Q’ (when clocked)

0 0 No change No change
1 0 1 0
0 1 0 1
1 1 1 (Oscillation 1 (Oscillation
apparent) apparent)
1. Case 1: J = 0; K = 0

2. Case 2: J = 1; K = 0

Page 8 of
16
Computer Systems Week 3 Laboratory

3. Case 3: J = 0; K = 1

4. Case 4: J = 1; K = 1

16. How can a J-K Flip Flop be made to behave like a D Flip Flop?
- To make a J-K Flip Flop behave like a toggle (T Flip Flop), we need to do 2 changes. One,
connect the two inputs J and K into one input only. Second, set that new input as Toggle
(T) input. The circuit will be like this after making two changes on the original J-K Flip
Flop in Question 14, 15:
Case 1: When Input = 1 that J = 0 and K = 1 so the Output will set Q = 1 and Q’ = 0

Page 9 of
16
Computer Systems Week 3 Laboratory

Case 2: When Input = 0 that J = 1 and K = 0 so the Output will set Q = 0 and Q’ = 1

17. How can a J-K Flop Flop be made to behave like a toggle (T Flip Flop)?

Page 10 of
16
Computer Systems Week 3 Laboratory

Discuss these questions with your lab demonstrator and provide your answer
in your submission document, along with the truth table in Step 15.

Part 2 - Register this!

18. Registers are just adjacent Flip-Flops that store collections of bits. You’re about
to wire up a register in Logisim, but first review the lecture slides, and if needed,
take a look at the resources above to remind yourself how Flip Flops work.
We’re going to work with D Flip Flops here.
19. We’re not going to wire our own Flip Flops anymore. We’re going to use
Logisism’s. Fa- miliarise yourself with Logisim’s D Flip Flop. Bring one into
your canvas, and connect up an input pin, and a clock, and connect an LED to
the output “Q”. Have a play and verify it works as you expect (ask your lab
demonstrator for assistance if needed).
20. Now wire-up a 4-bit big-endian register with D Flip Flops in Logisim. Do this
by using 4 pins for each input, and connect 4 LEDS to the output.
21. When complete, demonstrate your register to your lab demonstrator by showing
them dif- ferent combinations of input bits, and how this changes the output
when the clock pulses.
Export your circuit as an image and include it in your submission document.

22. Use your register to fill out the following test schedule:

Ox Input Binary Output Binary

Page 11 of
16
Computer Systems Week 3 Laboratory
0 0000 0000

1 0001 0001

2 0010 0010

3 0011 0011

5 0101 0101

A 1010 1010

B 0010 0010

Page 12 of
16
Computer Systems Week 3 Laboratory
C 0011 0011

D 0100 0100

E 0101 0101

F 0110 0110

Complete this table and place a copy of it in your submission document

Page 13 of
16
Computer Systems Week 3 Laboratory

Provide your answers in your submission document

When complete:
■
Submit your answers (screen shots, etc) in a single document using Canvas
■
Show your lab demonstrator your working circuits in class (you must do this to
get the cred- it). Your lab demonstrator may request you to resubmit if issues
exist.

Page 14 of
16