Chapter 3

Intel
Memory Interfacing
&
DIO Interfacing
Pin Configuration of 8086

20 bits

16 bits
 8088 vs 8086

Address Bus
A19 – A0

8088
Data Bus
D7 – D0

RD

WR

IO/M
 Write Cycle – Simplified
ONE BUS CYCLE

4 clock cycles. T1 T2 T3 T4

CLK

Address Valid Address

stable states.
Data Data Written to Memory

WR

eg. MOV [5678H],AL

 Read Cycle – Simpified
1234H 28
ONE BUS CYCLE
1235H ?

T1 T2 T3 T4

CLK

Address 1234H Valid Address

Data Data from Memory 28H

RD

eg. MOV AL, [1234H]

 Memory Pins

Address Bus
An – A0

Memory
Data Bus
D7 – D0

RD

WR

CS
 Basic Connections

Address Bus
A19 – A0

8088 Memory

Data Bus
D7 – D0

RD RD
RD

WR WR
WR

IO/M CS
IO/M
 Why decode
• Different memory types in a system
– Eg. ROM (BIOS) and RAM
• Different number of chips required to add
up to the amount needed.
– Example
– 16K memories are available but 64K is
required.
– So need to use 64/16 = 4 chips.
 Decoding
Decoding Circuit
IO/M
Address Bus
A19 – A14

Address Bus
A13 – A0

CS CS CS CS

RAM0 RAM1 RAM2 RAM3

8088 (16K) (16K) (16K) (16K)
BANK0

BANK1
Data Bus
D7 – D0

RD

WR
 Decoder design
• The CPU is able to address 220 or 1Mega
byte – (A0 to A19).
• Each RAM is 16K or 214 – (A0 to A13).
• To select one of the 4 RAMs, need to use
2 lines which is (A14 & A15).
• So the 4 unused line (A16, A17, A18 &
A19) will provide 16 possible combinations
of memory locations.
 Decoder design
164 = 65536 = 216 = 10000H = (00H to FFFFH).
A19 A18 A17 A16 Address Range

0 0 0 0 000000 to 00FFFF
BANK0
64KB
0 0 0 1 010000 to 01FFFF
BANK1 64KB
0 0 1 0 020000 to 02FFFF
BANK2 64KB
0 0 1 1

- - - - ------------------------

1 1 1 1 0F0000 to 0FFFFF

64K = 64 * 1024 = 65536. (16KB * 4 pcs)

 Decoder design
A19 A18 A17 A16 Address Range

0 0 0 1 Selected.
< assuming 0001.
BANK1
 Decoder design
A19 A18 A17 A16 A15 A14

0 0 0 1 0 0 RAM0 – 010000 to 013FFF

16KB
0 0 0 1 0 1 RAM1 – 014000 to 017FFF
16KB
0 0 0 1 1 0 RAM2 – 018000 to 01BFFF
16KB
0 0 0 1 1 1 RAM3 – 01C000 to 01FFFF
16KB

13FFF – 10000 = (3FFF + 1) = 4000H = 16384D / 1024D = 16K.

 Decoder Design - AND
IO/M
A19 0
A18 0
A17 0

A16 1
A15
A14

00 01 10 11

RAM0 RAM1 RAM2 RAM3

010000 to 014000 to
013FFF 017FFF
Analyse what happens in the timing
diagram and hardware circuit.
• MOV AL,[423CH]
• Assuming that DS is 1000H
• And that [1000:423CH] contains 78H

Address: 10000
423C +
------------
1423C => Physical address
 Read Cycle – Simpified
ONE BUS CYCLE

T1 T2 T3 T4

CLK

Address 1423C Valid Address

Data Data from Memory 78

RD
 Decoder design
A19 A18 A17 A16 A15 A14

0 0 0 1 0 0 RAM0 – 010000 to 013FFF

0 0 0 1 0 1 RAM1 – 014000 to 017FFF

0 0 0 1 1 0 RAM2 – 018000 to 01BFFF

0 0 0 1 1 1 RAM3 – 01C000 to 01FFFF

 Decoder Design - AND
0
IO/M
A19 0 1
A18 0
A17 0

A16 1
A15 0
A14 1

01


RAM0 RAM1 RAM2 RAM3

RAM1
selected
 Decoding
Decoding Circuit
IO/M
Address Bus
A19 – A14

Address Bus
1423C A13 – A0

CS CS CS CS

78
RAM0 RAM1 RAM2 RAM3
8088 (16K) (16K) (16K) (16K)

Data Bus
D7 – D0

RD

WR
 Decoder Design – 74LS138
S2S1S0
E3 74LS138
Enable 111
E2 Y7
Inputs 110
E1 Y6
101
Y5
100
Y4
011 Outputs
S2 Y3 010
Y2 Active
Selection 001
S1 Y1 LOW
Inputs 000
Y0
S0
 Inputs Outputs
E3 E2 E1 S2 S1 S0 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0
0 X X X X X 1 1 1 1 1 1 1 1
X 1 X X X X 1 1 1 1 1 1 1 1
X X 1 X X X 1 1 1 1 1 1 1 1
1 0 0 0 0 0 1 1 1 1 1 1 1 0
1 0 0 0 0 1 1 1 1 1 1 1 0 1
1 0 0 0 1 0 1 1 1 1 1 0 1 1
1 0 0 0 1 1 1 1 1 1 0 1 1 1
1 0 0 1 0 0 1 1 1 0 1 1 1 1
1 0 0 1 0 1 1 1 0 1 1 1 1 1
1 0 0 1 1 0 1 0 1 1 1 1 1 1
1 0 0 1 1 1 0 1 1 1 1 1 1 1

Individual output pin is Active-LOW.

 Inputs Outputs
E3 E2 E1 S2 S1 S0 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0
0 X X X X X 1 1 1 1 1 1 1 1
X 1 X X X X 1 1 1 1 1 1 1 1
X X 1 X X X 1 1 1 1 1 1 1 1
1 0 0 0 0 0 1 1 1 1 1 1 1 0
1 0 0 0 0 1 1 1 1 1 1 1 0 1
1 0 0 0 1 0 1 1 1 1 1 0 1 1
1 0 0 0 1 1 1 1 1 1 0 1 1 1
1 0 0 1 0 0 1 1 1 0 1 1 1 1
1 0 0 1 0 1 1 1 0 1 1 1 1 1
1 0 0 1 1 0 1 0 1 1 1 1 1 1
1 0 0 1 1 1 0 1 1 1 1 1 1 1

Individual output pin is Active-LOW.

 Decoder Design – 74LS138
_
IO/M
A19 NAND
A18
E1 74LS138
A17 E2 Y7
A16 E3 Y6
Y5
If only 4 RAMs are used. Y4
? S2 RAM3
Y3
RAM2
Y2 RAM1
A15 S1 Y1 RAM0
Y0
A14 S0
 Decoder Design – 74LS138
S S S Y Y Y Y Y Y Y Y
_ 2 1 0 7 6 5 4 3 2 1 0
IO/M X X X 1 1 1 1 1 1 1 1
IO/M
A19 X X X 1 1 1 1 1 1 1 1
A18
E1 74LS138 X X X 1 1 1 1 1 1 1 1
A17 E2 Y7
A16 E3 Y6 0 0 0 1 1 1 1 1 1 1 0
Y5
‘0’ GND = ‘0’ Y4
0 0 1 1 1 1 1 1 1 0 1
S2 Y3 RAM3
Y2 RAM2
A15 S1 Y1 RAM1 0 1 0 1 1 1 1 1 0 1 1
Y0 RAM0
A14 S0 0 1 1 1 1 1 1 0 1 1 1
1 0 0 1 1 1 0 1 1 1 1

Requires only 4 RAMs, 1 0 1 1 1 0 1 1 1 1 1

Short pin S2 to GND. 1 1 0 1 0 1 1 1 1 1 1
1 1 1 0 1 1 1 1 1 1 1
 Decoder Design – 74LS138
S S S Y Y Y Y Y Y Y Y
_ 2 1 0 7 6 5 4 3 2 1 0
IO/M X X X 1 1 1 1 1 1 1 1
IO/M
A19 X X X 1 1 1 1 1 1 1 1
A18
E1 74LS138 X X X 1 1 1 1 1 1 1 1
A17 E2 Y7 RAM3
A16 E3 Y6 RAM2 0 0 0 1 1 1 1 1 1 1 0
Y5 RAM1
‘1’ Vcc = ‘1’ Y4 RAM0 0 0 1 1 1 1 1 1 1 0 1
S2 Y3
Y2
A15 S1 Y1
0 1 0 1 1 1 1 1 0 1 1
Y0
A14 S0 0 1 1 1 1 1 1 0 1 1 1
1 0 0 1 1 1 0 1 1 1 1
1 0 1 1 1 0 1 1 1 1 1
Or pin S2 connect to Vcc
using upper outputs. 1 1 0 1 0 1 1 1 1 1 1
1 1 1 0 1 1 1 1 1 1 1
 Decoder design 3
• If there are 8 RAMs instead of 4, the
74LS138 can be easily modified.
IO/M
A19
_ A18
E1 74LS138
IO/M A17 E2 Y7 RAM7
1 – IO ‘1’ E3 Y6 RAM6
Y5 RAM5
0 -- M Y4 RAM4
A16 S2 Y3 RAM3
Y2 RAM2
A15 S1 Y1 RAM1
Y0 RAM0
A14 S0
-
Exercise
4
Design a memory system for the 8088 with
one 64K ROM from (0E0000H to 0EFFFFH)
and one 64K RAM from (0A0000H to
0AFFFFH).
A19 18 17 16 A15 14 13 12 A11 . . A8 A7 . . A4 A3 A2 A1 A0

E0000H = 1 1 1 0 0 0 0 0 0000 0000 0 0 0 0 B

A19 18 17 16 A15 14 13 12 A11 . . A8 A7 . . A4 A3 A2 A1 A0

A0000H = 1 0 1 0 0 0 0 0 0000 0000 0 0 0 0 B

AFFFFH = 1 0 1 0 1 1 1 1 1111 1111 1 1 1 1 B
-
3 Memory Map
A19 A18 A17 A16 Address Range

1 0 0 0 080000 to 08FFFF

1 0 0 1 090000 to 09FFFF

1 0 1 0 0A0000 to 0AFFFF (RAM)

64KB
- - - - ------------------------

1 1 1 0 0E0000 to 0EFFFF (ROM)

64KB
1 1 1 1 0F0000 to 0FFFFF
-
Memory Map
2 S2 S1 S0
A19 A18 A17 A16 Address Range

1 0 0 0 080000 to 08FFFF

1 0 0 1 090000 to 09FFFF

1 0 1 0 0A0000 to 0AFFFF (RAM)

64KB
- - - - ------------------------

1 1 1 0 0E0000 to 0EFFFF (ROM)

64KB
1 1 1 1 0F0000 to 0FFFFF
-
1
A19
E3 74LS138
IO/M E2 Y7 Fxxxx
E1 Y6 E (ROM)
Y5 D
‘0’ Y4 Cxxxx
A18 S2 Y3 B
Y2 A (RAM)
A17 S1 Y1 9
Y0 8xxxx
A16 S0

RAM and ROM are memory chips: IO/M = ‘0’

--- Week 5 Break ---
 Intel
DIO interfacing
 74LS244
OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
1G

ENB
1Y1 1A1

ENB
1Y2 1A2

ENB
1Y3 1A3

ENB
1Y4 1A4

ENB
2Y1 2A1

ENB
2Y2 2A2

ENB
2Y3 2A3

ENB
2Y4 2A4

2G
 Basic connections
Address Bus
Decoder

CPU
74LS244
Data Tristate
Bus buffer
Inputs
eg. Switches,
or Sensors.

Data Bus Memory

 74LS373
Octal D-Type Transparent Latches

D0 Q0

D1 Q1

D2 Q2

D3 Q3

D4 Q4

D5 Q5

D6 Q6

D7 Q7

OC
74LS373
EN
 Basic connections

Decoder

CPU
74LS373
Data Latch
Bus Outputs

eg. LEDs
or Motor.
 Why not use 74LS244 also?
• When 74LS244 is not selected, the
outputs are in a tri-state.
• When 74LS373 is not selected, the
previous data is latched to the output
• Conclusion.
• Use 74LS244 for inputs and 74LS373 for
outputs.
 Memory vs IO
IO/M = 0

FFFFF

IO/M = 1

Memory FFFF
1M
IO
2 20
64K

216
00000 0000

(1M = 220) (64K = 216)

 Memory vs IO
IO/M = 0

FFFFF
IO/M = 1

200H =
address Memory FFFF
for 1M
memory. IO
64K 200H =
00200 0200 address
0000 for I/O.
00000

Eg. MOV AL,[0200h] Eg. IN AL,0200h

 Inputs
• Connect 8 switches to the CPU using the
address 7AH.
 Connections - Input
• IO/M is HIGH.
• RD is LOW.
• Address bus must match the location
selection – (7Ah or 01111010b).
• In our examples, we will only use A0 to A7
instead of the full A0 to A15 in order to
simply the diagrams.

(64K = 216)
 Vcc

R
SW
ENB
D0

ENB
D1

ENB
D2

D3
ENB
Switches
ENB (active-
D4

ENB
low)
D5

ENB
D6

ENB
D7

1G

2G

A0
A1
A2
IO address A3
A4

7Ah
A5
A6
A7
IO/M
RD
Simplified drawing: Vcc

R
Buffer SW
ENB
D0

ENB
D1

ENB
D2

D3
ENB
Switches
ENB (active-
D4 74LS244
ENB
low)
D5

ENB
D6

ENB
D7

1G

2G

A0
A1
A2
IO address A3
A4

7Ah
A5
A6
A7
IO/M
RD
 R
Data from switches.
ENB
D0
0 (lsb)
ENB

Data = AL
D1
1
0
ENB
D2

0
ENB

data D3

1
ENB
D4

0
ENB
D5

D6
ENB
1
D7
ENB
0 (msb)
1G SW
IN AL,7AH 2G

A0

address A1
A2
A3
A4
A5
A6
A7
IO/M
RD 7AH is address, not data.
 Vcc

R
What is the result Active
LOW.
in AL if the following ENB

switches are closed?

D0

ENB
0
D1

ENB
1
IN AL,7AH
D2
0
ENB
D3
0
1
ENB
D4

AL = 0x52 D5
ENB

0
D6
ENB
1
> 01010010B D7
ENB
0
1G SW
2G

A0
A1
A2
A3
A4
A5
A6
A7
IO/M
RD
How can the program
checks whether the R
switch S2 is closed? SW
ENB
D0

IN AL,7AH
ENB
D1

ENB S2
AND AL,0X04 D2

ENB

JZ CLOSE D3

ENB

76543210 D4

ENB

0X52 = 01100010 D5

ENB

0X04 = 00000100 D6

ENB

--------------- D7

00000000
1G

2G

S2 is closed.
A0
A1
A2

Active LOW.
A3
A4
A5
A6
A7
IO/M
RD
How can the program
R
checks whether the
switch S7 is closed? SW
ENB
D0

ENB
D1

IN AL,7AH D2
ENB

CMP AL,0X80 D3
ENB

JZ CLOSE D4
ENB

ENB
D5

0X62 = 01100010 D6
ENB

0X80 = 10000000 D7
ENB

S7
--------------- 1G

00000000 2G

A0
A1

S7 is closed.
A2
A3
A4

Active LOW.
A5
A6
A7
IO/M
RD
 Outputs
• Connect 8 LEDs to the CPU using the
address 12H.
 R

LED
Latch
D0 Q0

D1 Q1

D2 Q2

D3 Q3

D4 Q4

D5 Q5

D6 Q6

A0 D7 Q7
A1
A2 ‘0’ OC
A3 74LS373
A4 EN
A5
A6
A7
IO/M
WR
 R

LED
Latch
Data = AL D0 Q0

D1 Q1

D2 Q2

D3 Q3

D4 Q4

OUT 12H,AL D5 Q5

D6 Q6

A0 D7 Q7
A1
A2 ‘0’ OC
A3 74LS373
A4 EN
A5
IO A6
A7

address
IO/M
WR

= 12H
 +5V

Which LEDs will light up?

current

MOV AL,7EH
OUT 12H,AL
D0
0
7EH = 0111 1110 B D1
Q0
1
Q1

D2
1
Q2
LEDs are active low. D3
1
Q3

D4
1
Q4

D5
1
Q5

D6
1
Q6

D7
0
A0 Q7
A1
A2 ‘0’ OC
A3 74LS373
A4 EN
A5
A6
A7
IO/M
WR
 Exercise 1
• Connect a 7-segment LED to the IO
address 78H and write the program to
display
 Active HIGH.

a 1 a
MOV AL,6DH b 0
OUT 78H,AL c 1 f b
gfedcba d 1
g
e 0
01101101 f 1 e c
g 1
- 0 d

LED ‘5’ = 01101101B = 6DH.

 Exercise 2
• Add 8 switches to address 071H and write
the program to :
(i) display ‘0’ if the switch S4 is off and
(ii) display ‘1’ if the switch S4 is on.

SW 4 = 00010000B = 10H.

LED ‘0’ = 00111111B = 3FH.

LED ‘1’ = 0000110B = 06H.

 solution
AGAIN: IN AL,71H
AND AL,10H ; Checks S4
JNZ ZERO
MOV AL,06H ; LED ‘1’
JMP DISP
ZERO: MOV AL,3FH ; LED ‘0’
DISP: OUT 78H,AL
JMP AGAIN
- Determine the IO addresses
4 selected by this circuit
0
0
0
0
0
1
1
0

06E0h – 06FFh
06C0h – 06DFh
1
06A0h
0680h
1 0660h
1
0640h – 065fh
0620h – 063fh
0 0600h – 061fh

(A4-A0 not used.)

- Determine the IO addresses
3 selected by this circuit
0
A15 14 13 A11 10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
0 A12
0 0000011011000000B
0
0 0
0000011011011111B
1
1 = 06C0H to 06DFH.
0

S2S1S0
1
111
1 110 06C0h – 06DFh
101
100
1 011
010
001
1
000
0

(A4-A0 not used.)

- Determine the IO addresses
2 selected by this circuit
0
1
0
0
0
0
1
0
0

(A7-A4 and A0 not used.)

- Determine the IO addresses
1 selected by this circuit
A15 14 13 A11 10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
0 A12
1 0100010000001010B
0
0
0
0100010011111011B
0
1 = 440AH to 44FBH.
0
0

S2S1S0
1 111
110
1
101 440A – 44FB
100
1 011
010
0 001
000
1

(A7-A4 and A0 not used.)

--- Week 6 Break ---