The Questa

Verification Solution

Benefits The Questa® Verification Solution from identify bugs as early as possible in the
Siemens EDA, a part of Siemens Digital process. Questa lets you apply CDC verifi-
Industry-Leading Solutions
Industries Software, continues to evolve cation, formal verification, mixed-signal
• Portable stimulus and
in response to the growing complexity of verification, portable stimulus, and other
coverage closure
SoC designs. Besides the sheer size of powerful technologies to maximize the
• Integrated verification designs, the inclusion of multiple embed- effectiveness of your verification at the
management and analysis ded processors and advanced intercon- block- and subsystem-level so your sys-
nect systems, increasing software tem-level verification can focus on sys-
• High performance/capacity
content and the configurability required tem-level functionality, including
unified debug
by multi-platform based designs require a software, without having to worry about
• Power-aware verification functional verification solution that uni- lower-level bugs taking away from your
fies a broad arsenal of verification solu- productivity. No one wants to compro-
Best-in-Class Technology tions. The key to verification success is to mise product quality. However, time-to-
• High-performance multi- decompose the problem and use the best market pressures dominate SoC projects.
language simulator solution for each aspect of the system. To deliver quality within schedule
This places tremendous importance on requires improving the time to achieve
• Formal-based apps the verification plan and the ability to coverage and quality goals and improv-
and formal verification collect metrics throughout the process ing debug productivity.
• HW/SW co-verification and across all verification tasks to track
The solution is composed of several
progress against the plan, allocate and
• UVM methodology technologies, each powerful on its own.
manage resources efficiently, and iden-
Applied together, along with a compre-
tify trends as the project progresses
Enterprise Verification Platform hensive database and best-in-class verifi-
against schedule.
• Unified verification from cation management tools, these
simulation to emulation Software has become a major compo- technologies deliver a powerful answer
nent of SoC system functionality, to the spectrum of verification problems.
• Simulation acceleration with creating new requirements for block-to-
Veloce TBX for up to 1000X Unified Simulation is built on a best-in-
system verification reuse and the need
performance gain class simulator. The Questa Advanced
for system verification and debug. While
Simulator achieves industry-leading per-
• Common coverage database software testing of SoC integration and
formance and capacity through very
and flows basic functionality as well as the verifica-
aggressive, global compile and simula-
tion of low level driver software can be
• Unified Verification IP for tion optimization algorithms for
accomplished in simulation, long, com-
acceleration and reuse SystemVerilog and VHDL. Questa also
plex sequences that exercise system
supports very fast turnaround time
functionality demand acceleration with
flows and effective library management
full debug visibility. To avoid wasting
while maintaining high performance
cycles at the system level, it is critical to
with unique capabilities to pre-optimize

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 FUNCTIONAL
VERIFICATION

The Questa Verification Solution

and reuse, enabling dramatic regression The Questa Memory Library comprises an inject metastability into functional sim-
throughput improvements of up to 3X extensive range of fast and accurate DRAM ulation for reconvergence verification
when running a large suite of tests. The and Flash memory models. These can be and waiver validation. Finally, Signoff
Questa Visualizer debug environment dropped into any testbench to verify any CDC analysis identifies clock domain
provides high performance, high- memory subsystem. For speed, we provide crossing issues in the final netlist of a
capacity debugging for both Questa and backdoor access and on-the-fly reconfigu- design that weren’t present in the
Veloce, enabling the use of the same ration. For correctness and completeness, source RTL that may have been gener-
debug environment from simulation to we provide extensive assertions and cover- ated by the implementation process,
emulation and other engines. age. For debugging, we provide powerful and does so efficiently by preserving
transaction-to-pins debug capabilities. constraints and setup from the original
Portable Stimulus and Intelligent RTL CDC environment.
Testbench Automation.
Questa inFact automatically generates Questa Formal Verification solutions
verification stimulus and can be applied at complement simulation with a full
the block, subsystem and SoC levels. spectrum of formal tools ranging
The technology avoids redundancy from automated apps to direct
and can achieve target coverage model checking. At the core of
more than 10X faster than is the platform is a set of high
possible with constrained ran- performance formal analysis
dom testing. The technology engines that offer exhaus-
can be applied to shorten tive verification early in
time to coverage or to the design cycle with cus-
achieve more comprehensive tom coded SVA/PSL/OVL
verification by enabling more assertions. Building on
tests to run in the same this foundation, the
amount of time. Questa Formal Apps boost
verification efficiency and
Verification IP is designed
design quality by exhaus-
to simplify the verification of
tively addressing verification
standard protocol interfaces
tasks that are difficult to com-
that are complex and would
plete with traditional methods,
take significant effort otherwise.
yet do not require formal or
It is highly configurable and con-
assertion-based verification experi-
sists of reusable testbench building
ence. The Questa Formal App suite
blocks. Questa Verification IP (QVIP) is a
performance-optimized library of stan- includes applications to address tasks
dard SV UVM components for simula- such as: static and conditional connec-
tion with support for Arm® AMBA®, Questa CDC and RDC Solutions iden- tivity checking, secure path integrity
Ethernet, MIPI®, PCIe® and USB and tify errors that have to do with clock checking, unreachable code identifica-
many other protocols including some of and reset domain crossings – signals (or tion, X-state propagation, state-space
the leading edge protocols like PCIe Gen groups of signals) that are generated in analysis, and register verification.
5. Using QVIP frees up engineers to one domain and consumed in another. Additionally, the Questa Sequential
focus on design-specific verification and It does so with structural analysis and Logic Equivalence Checking (SLEC) App
enables tests to be reused in accelera- recognition of clock or reset domains, uses formal methods to perform
tion with Veloce. QVIP includes synchronizers, and low power struc- exhaustive comparisons between inputs
advanced transaction-level debug, com- tures (via UPF). The technology checks to reveal any behavioral discrepancies
prehensive protocol assertions, func- all potential failure modes and presents that could arise in clock gating, ECO
tional coverage, test plans and test to the user familiar schematic and integration, re-pipelining, or fault miti-
sequences that together can be used to waveform displays. Additionally, in con- gation logic. For interactive formal
validate protocol compliance and accel- cert with simulation this technology can model checking, users write properties
erate time-to-RTL-signoff. for assertions (tests), assumes (con-
straints), and coverage, then run
 FUNCTIONAL
VERIFICATION

Questa PropCheck to reveal any discrep- verification supporting multiple levels bugs. Low-power and UPF debug is fully
ancies between the specification and of abstraction and performance from integrated and overlaid with RTL views.
DUT. Model checking can also address Spice netlists to Real Number Models. Visualizer is SystemVerilog class-based
issues of interface protocols, functional and UVM-aware to speed up overall
Questa HW/SW Verification provides
coverage, control logic, data integrity, debug time, even on today’s most com-
processor-based system-level verification,
and post-silicon debug, which, plex SoCs and FPGAs.
using software tests to verify RTL and
together, provide the most exhaustive
hardware/software integration. The tech- Siemens EDA Verification Expertise
possible analysis of a design. Formal-
nology comes with a host of advantages provides ample resources to help you
optimized Verification IP is available for
such as ensuring chip power manage- get started adopting advanced verifica-
popular standard protocols.
ment, loading and booting operating sys- tion techniques.
Questa Low Power Verification tems, and running software applications.
enables early (RTL) verification of active It accelerates simulation, enables instant The Verification Academy is organized
power management applied to a com- replay, and offers virtual emulation — all into a collection of free online courses
plex design, to ensure that the power of which serve to trim debugging time. and resources, focusing on key aspects
management architecture and behavior of advanced functional verification
Questa Verification Management and designed to mature an organization’s
are correct and that the design will
Coverage manages the data complexity, verification process. Course topics
operate correctly under active power
guides the process and provides automa- include Assertion-Based Verification,
management. Questa PowerAware sim-
tion across all verification engines to Clock-Domain Crossing Verification,
plifies the verification process through a
improve verification productivity. It
comprehensive suite of static checkers Formal Assertion-Based Verification,
offers analysis and optimization features
for checking the consistency of the Formal Coverage, Metrics in SoC
built upon the Unified Coverage
power management architecture and Verification, Portable Stimulus, Power
Interoperability Standard database
dynamic checks for automated error Aware Simulation, UVM Debug, and
(UCISDB), with results and trend analysis,
detection. Questa PowerAware also pro- many more. Each course consists of mul-
test plan tracking and run management.
vides visualization of power manage- tiple sessions allowing the viewer to pick
Questa Verification Management effi-
ment architecture and behavior, and choose topics of interest as well as
ciently ties all verification-related tasks
coverage data collection, and test plan revisit topics for future reference.
together and gives all parties — system
generation for power states and state
architects, software engineers, designers The Verification Academy is the most
transitions. Based on the latest industry-
and verification specialists — real-time complete UVM online resource collec-
standard IEEE 1801-2015 UPF for speci-
visibility into the project. This visibility tion. You’ll find everything you need to
fication of active power management,
helps to hit market windows on sched- get up to speed on UVM, whether it’s
Questa PowerAware integrates well
ule, manage risk and improve throughput downloading the kit(s) or participating
with other UPF-based tools to support
and debug turnaround times. in online or in-person training. The
multi-tool and multi-vendor low power
design and verification flows. Questa Visualizer is a context-aware UVM courses provide a great overview
debug platform that supports a com- of methodology concepts, introductory
Questa ADMSTM verifies complex ana- to advanced, with videos that walk
plete logic verification flow, including
log/mixed-signal designs. The technol- through useful code examples. The
simulation, emulation, and prototyping
ogy integrates four high performance UVM Online Methodology Cookbook is
as well as design, testbench, low-power,
engines: Eldo® for general purpose ana- an online textbook to show you in
and assertion analysis. Visualizer pro-
log, ADiTTM for fast transistor-level, more detail how to use the various
vides a high performance/high capacity
Eldo RF for modular steady state and features of the methodologies to
debugger that scales from simulation to
Questa Sim for digital. Its combination
emulation. Multiple automated features create reusable verification compo-
of languages and algorithms allows for
quickly find RTL, gate-level, and protocol nents and environments.
both top-down design and bottom-up
 FUNCTIONAL
VERIFICATION

Consulting and Training. Siemens EDA

Consulting Verification Services offers
solution-driven consultants who will
dramatically reduce your verification
process times while improving quality.
Unlike other EDA consulting services or
third party consultants, Siemens EDA
Consulting’s highly experienced
Verification Services team offers cus-
tomized solutions and proven, struc-
tured processes to ensure projects are
delivered on time and to specification,
and with greater probability of first-pass
success. Siemens EDA Education
Services offers a full range of learning
solutions developed specifically for elec-
tronics designers and engineers The Siemens EDA Enterprise Verification Platform (EVP) delivers high performance verification from
engaged in advanced verification. Users prototype to silicon.
can choose the type of training that
best suits their needs and schedule.
These choices include unique Live
Online Training, training and seminars
given in Siemens EDA training centers
around the world, and on-site training
and mentoring specifically designed for
your company.
The Enterprise Verification Platform.
Built upon several powerful technolo-
gies, the Enterprise Verification
Platform transforms verification, dra-
matically increasing productivity and
more efficiently managing resources,
enabling users to select the best appli-
cation or tool for the job and combine
results from all the engines to dynami-
cally track the progress of the entire
verification program.

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