SEGMENTATION A programmer thinks of it as a main program with a set of methods. yrocedures, or functions. It may also include various data structures: objects. arra,s, stacks. variables, and so on and these modules or data elements is referred to by name. Segments vary in length, and the lengta of each is intrinsically defined by its purpose in the program. Elements within a segment are identified by their offset from the beginning of the segment. Segmentation is a memory-management scheme that supports the programmer view of pe ‘smo ened a EE phic memory Each segment has a name and a length. The programmer therefore specifies each address by two quantities: a segment name and an offset. For simplicity of implementation, segments are numbered and are referred to by a segment number, rather than by a segment name. Thus, a logical address consists of atowo tuple: . Normally, when a program is compiled, the compiler automatically constructs segments reflecting the input program, SEGMENTATION HARDWAR® Segmentation Hardware although the programmer can now refer to objects in the program by a two-dimensional address, the actual physical memory is still, of course, a one dimensional sequence of bytes. Thus, we must define an implementation _to_map two-dimensional _user-defined_addresses_into_one le. dimensional physical addresses, This mapping is effected by a segment t Each entry in the segment table has a segment base and a segment limit. The segment base contains the starting physical address where the segment resides it specifies the length of the segment Segmentation Hardware ‘rap: addressing error physical memory Unit os 30 The use of a segment table is illustrated in Figure. A logical address consists of two parts: a segment number, s, and an offset into that segment. d. The OOsegment number is used as an index to the segment table. The offset d of the logical address must be between 0 and the segment limit tis not, we trap to the operating system, (logical addressing attempt beyond end of segment). ‘When an offset is legal, itis added to the segment base to produce the address in physical memory of the desired byte. The segment table is thus essentially Advantages of Segmentation 1, No internal fragmentation 2. Average Segment Size is larger than the actual page size. 3. Less overhead 4, Itis easier to relocate segments than entire address space. 5. The segment table is of lesser size as compare to the page table in paging. Disadvantages 1. Itcan have external fragmentation. 2. Itis difficult to allocate contiguous memory to variable sized partition. 3. Costly memory management algorithms. Paging: Segmentation permits the physical address space of a process to be noncontiguous. Paging is another memory-management scheme that offers this advantage, However, paging avoids extemal fgmentton and the need for ‘compaction. It also solves the considerable problem of fitting memory chunks cooperation between the operating system and the computer hardware. Basic Method :The basic method for implementing paging involves breaking physical memory into fixed-sized blocks called frames and breaking logical memory into blocks of the same size called pages. When a process is to be executed, its pages are loaded into any available memory frames from their source (a file system or the backing store;. The backing store is divided into fixed-sized blocks that are the same size as the memory frames or clusters of multiple frames. The hardware support for paging is illustrated in Figure: gf Paging Hardware len al ee Every address generated by the CPU is divided into two parts: a page number ysicl Eaurees 10000... 0000 | fet ett | __| =e | Tt r "physical page table ahi stoencaacahnndcageeatt (p) and a page. offset (d). The page number is used as an index into a page table. The page table ‘contains the base address of each page in physical memory. This base address is combined with the page offset to define the physical memory address that is sent to the memory unit. The paging model of memory is shown in Figure:Paging Model of Logical and Physical Memory frame umber o| | 1 1} page o PAE afr 2 page table Unit-4 os The page size (like the frame size) is defined by the hardware, The size of a page is a power of 2, varying between 512 bytes and | GB per page, depending on the computer architecture, The selection of a power of 2 as a page size makes the translation of a logical address into a page number and page offset particularly easy. If the size of the logical address space is 2m, and a page size is 2n bytes, then the high-order m — n bits of a logical address designate the page number, and the n low-order bits designate the page offset. Thus. the logical address is as follows: page number | page offsetwhere p is a0 index into the table and d is the displacement within the page. Paging itself is have no external fragmentation: any free frame can be allocated to a process no extemal rE eee ape that needs it. However, we may have some intemal fragmentation. If process a form of dynamic relocationWhen we use a paging scheme. we Size is independent of page size, we expect intemal fragmentation to average one-half, page process. new-process pagetable 21|- =f les @ ) Free frames (a) before allocation and (b) after When a process arrives in the system to be executed, its size, expressed in pages. is examined. Each page of the process needs one frame. Thus, if the process requires n pages, at least n frames must be available in memory. If n frames are available. they are allocated to this arriving process. The first page of the process is loaded into one of the allocated frames, and the frame number is put in the page table for this process. The next page is loaded into another frame, its frame number is put into the page table, and so on. ‘An important aspect of paging is the clear separation between the programmer's view of memory and the actual physical memory. The programmer views memory as one single space. containing only this oneprogram. The difference between the programmer's view of memory and che actual physical memory is reconciled by the address-translation hardware. The logical addresses ar translated into physical addresses, This mapping is hidden fom the programmer and is controlled by the operating system, Since the operating system is managing physical memory, it must be aware of the allocation details of physical memory—which frames are allocated, which frames are available, how many total frames there are, and so on. This information is generally kept in a data structure called a{frame table) The frame table has one entry for each is ¢ frame, indicating whether the latter is free or allocated and, if it is allocated, to which page of which process or processes. The operating system maintains a copy of the page table for each process. just copy is used to translate logical addresses to physical addresses whenever the operating system must map a logical address to a physical address manually. Paging therefore increases the context-switch time. Hardware Support: Each operating system has its own methods for storing page tables. The hardware implementation of the page table can be done in several ways. In the simplest case, the page table is implemented as a set of dedicated registers. eo aE eeeeEET_E—_SSSS These registers should be built with very high-speed logic to make the paging- address translation efficient. Every access to memory must go through the address translation efficient. ry must 2 igh, paging map, so efficiency is a major consideration. The CPU dispatcher reloads these registers, just as it reloads the other registers. The page table is kept in main memory, and a page-table base register (PTBR) points to the page table. Changing page tables requires changing only this one register, substantially reducing context-switch time. The problem with this approach is the time required to access a user memory location, The standard solution to this problem is to use a special, small, fastlookup hardware cache —re> SS OSestranslation look-aside buffer (TLB). The TLB is associative. high- called 8 : See ee ee ee memory’ Each entry in the TLB consists of two parts: a key (or tag) and a the associative memory is presented with an item, the item is ‘a value. Whe ~Gompaed wis al evs Simian the item is found, the corresponding value field is retumed. The search is fast. If the Page number is not in the TLB (known as a TLB miss), a memory reference to the page table must be made. Depending on the CPU, this may b ically in hardware or via an interrupt to the operating system. When the frame number is obtained, we can use it to access memory. logical address page frame umber number page tablo Figure: Paging hardware with TLB In addition, we add th er and frame number to the TLB, so that they will be found quickly on the next reference, The percentage of times that the page number of interest is found in the TLB is called the hit ratio. Protection: Memory protection in a paged environment is accomplished by protection bits associated with each frame. Normally, these bits are kept in the page table. One bit can define a page to be read—write or read-only, Every reference to memory goes through the page table to find the correct frame number. An attempt toite to a ead only Page causes a hardware trap to the operating system (or wit op tion violation), memory Prove = ae additonal bit 8 generally atac ich entry in the page table: a valid— invalid bit. Whe this bit is set to valid, the associated page is in the process's Jogical address space and is thus a legal (or valid) page. When the bit is set to invalid, the page is not in the process's logical address space. Illegal addresses are trapped == by —use_—of the —valid-invalid bit. | | frame number valid-invalid bit wo] | =] a] =[elelel= EE Figure: Valid (v) or invalid (i) bit in a page table.. Shared Pages: An ad | Advantage of paging is the possibility of sharing common code. This i a 5 consideration jg Particularly important in a time-sharing 1] datas 2) dain 3) eat 4) 02 6] oda 7} ata Figure: Sharing of code in a paging environment. sania een itt NNN‘Operating System = Vitual Memary Operating System - Virtual Memory A computer can address more memory than the amount physically installed on the system. This extra memory is actually called virtual memory and it is a section of a hard disk that's set up to emulate the computer's RAM. The main visible advantage of this scheme is that programs can be larger than physical memory. Virtual memory serves two S. First, it allows us to extend the use of physical memory by using disk. Second, it allows us to have memory protection, because each virtual address is translated to a physical address. Following are the situations, when entire program is not required to be loaded fully in main memory. User written error handiir ines are used only when an error occurred in the data or computation. Certain options and features of a program may be used rarely. ee POEM TORY. a UBM TEP hy Many tables are assigned a fixed amount of address space even though only a small amount of the table js . The ability to execute a program that is only partially in memory would counter many benefits. Less number of /O would be needed to load or swap each user program into memory. ‘A program would no longer be constrained by the amount of physical memory that is available. Each user program could take less physical memory, more programs could be run the ‘same time, with a corresponding increase in CPU utilization and throughput. Modem microprocessors intended for general-purpose use, a memory management unit, or MMU, is built into the hardware, The MMU's job is to translate virtual addresses into physical addresses ‘A basic example is given below — |ntpsutwwwtutorilspoint.comloporating_systemvos_viual_memonyhimanya, 1218 ‘Operating System = Vitual Memory ‘Virtual Address Physical Address 0 4k c aK 12K 16K Secondary Memory Virtual memory is commonly implemented by demand paging. It can also be implemented in a segmentation system. Demand segmentation can also be used to provide virtual memory. Demand Paging ‘A demand paging system is quite similar to a paging system with swapping where processes reside in sec loaded only on demand, not in advance. When a context ‘switch occurs, the o} not copy any of the old program's pages out to the disk or any of the new pragram's pages into the main memory Instead, it just begins executing the 7 program after loading the first page and fetches that program's pages as they are referenced. iches that program's pages as they ara referenced. hips ttotlspont convoperting_systenios_ vital memoryhim128721, 1218 PM Operating System - Vitus Memory Main Memory Secondary Memory el N 0 clalelszlo}~ While executing a program, if the program references a page which is not available in the main memory because it was swapped out a little ago, the processor treats this invalid memory reference as a page fault and transfers control from the program to the operating system to demand the page back into the memory. Advantages Following are the advantages of Demand Paging - «Large virtual memory. + More efficient use of memory. + There is no limit on degree of multiprogramming. Disadvantages + Number of tables and the amount of processor overhead for handling page interrupts are greater than in the case of the simple paged management techniques. ‘tps tutotalspolntcomfoperting_systenvos_vitual memaryhimjonas, 218 PM ‘Operating System -Vitual Memory Page Replacement Algorithm age replacement algorithms are the techniques using which an Operating System decides which memory pages to swap Out, write to disk when a page of memory needs to be allocated. Becino Mf appens whenever a page fault occurs and a free page cannot be used for allocation purpose accounting to reason that pages are not available or the number of free pages is lower than esate anes ‘When the page that was selected for replacement and was paged out, is referenced again, it has to read in from disk, and this requires for /O completion. This process determines the quality of the page replacement algorithm: the lesser the time waitin for page-ins, the better isthe algorithm. ‘A page replacement algorithm looks at the limited information about accessing the pages provided by hardware, and tries to select whi be replaced to minimize the total number of page misses, while balancing it with the costs of primary storage and processor time of the algorithm itself. There are many different page replacement algorithms. We evaluate an algorithm by running it on a particular string of memory reference and computing the number of page faults, Reference String The string of memory references is called reference string. Reference strings are generated artificially or by tracing a given system and recording the address of each memory reference. The, latter choice produces a large number of data, where we note two things. + Fora given page size, we need to consider only the page number, not the entire address. «If we have a reference to a page p, then any immediately following references to page P will never cause a page fault. Page p will be in memory after the fist reference: the immediately following references will not fault. mediately folowing references will not fa . For example, consider the following sequence of addresses - 123,215,600,1234,76,96 «If page size is 100, then the reference string is 1,2,6,12,0,0 First In First Out (FIFO) algorithm + Oldest page in main memory isthe one which will be selected for replacement + Easy to implement, keep a list, replace pages from the tail and add new pages at the head. a noah ttofalspolnt.comloperating_syservos_vetusl_memaryhim i29721, 218M ‘Operating Systm = Vital Memory Referencestring: 0, 2 1, 6, 4,0, 1,0, 3,2, 2,1 i PKK KX Al fA HaB oO yo} 3. fo} 1) Jo] 2 ee oe oe | bP} By} By BP By ee el et Fault Rates 9/12 =0.75 EEEE Optimal Page algorithm An optimal page-replacement algorithm has the lowest page-fault rate of all algorithms. An ‘optimal page-replacement algorithm exists, and has been call IN. Replace the page that will not be used for the longest period of time. Use the time when a Page is punnbec 4 oceuromun - Referencestring: 0, 2,1, 6 4,0, 1,0, 3,1,2,2 Misses OK XXX x 4 = 0 2 [| Ls Fault Rate= 6/12 =0.50 Least Recently Used (LRU) algorithm Page which has not been used for the longest time in main memory is the one which will be selected for replacement. pera ecreianee Easy to implement, keep a list, replace pages by looking back into time, Intpeutwatutotalsplnt.conloperaing_systemvos_viual_memonyhim oj