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fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TCSII.2018.2873797, IEEE
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1

Design of an efficient Multilayer Arithmetic Logic

Unit in Quantum-dot Cellular Automata (QCA)
Shahram Babaie, Ali Sadoghifar, and Ali Newaz Bahar, Member, IEEE

 A QCA cell as the basic element of this technology includes

Abstract— Quantum-dot Cellular Automata (QCA) is a a nano-scale square with four charged containers that are called
new nano-scale technology that due to making significant quantum dots in its corners and two mobile electrons. A single
improvements in the design of electronic circuits can be QCA cell can only accept two completely polarized states
considered as an appropriate alternative to CMOS called cell polarization (p = +1, p = -1); also, switching is
technology. The Arithmetic Logic Unit (ALU) is a carried out through switching the occupancy of the two
fundamental component of the Central Processing Unit electrons. As regards, there is no electrical current in QCA
(CPU) to carry out the arithmetic and logical operations computations; the power consumption is considerably lower
that multiplexer and full adder play an important role in its than conventional CMOS circuits. The four-zone plan, which is
operations. In this paper, based on the extracted features of known as Landauer clocking is the most common scheme that
the arithmetic operations of the ALU, we propose a new is applied in QCA technology that includes Relax, Switch, Hold,
special low-complexity QCA 4:1 multiplexer, which is and Release phases[2]. In addition, there are several ways to
application-specific to the proposed ALU. Moreover, a new cross the wires on each other such as single-layer crossing,
QCA full adder is proposed based on the cell interaction. multilayer crossing, and logical crossing [2].
Likewise, a QCA multilayer ALU structure is designed In this paper, a new application-specific QCA 4:1 multiplexer
based on the validated proposed structures to carry out four is proposed based on the explicit interactions between QCA
logical and eight arithmetic operations. The functional cells. Moreover, according to the extracted certain
correctness of the proposed structures are evaluated by characteristics from the arithmetic operations of ALU, also
QCADesigner tool; also, QCAPro as an accurate power considering that most arithmetic operations of ALU can be
estimator tool is applied to investigate their power carried out through the sum operation, a new QCA full adder is
dissipation. The simulation results demonstrate that the proposed to enhance the related operations. In addition, a new
proposed structures outperform in comparison to multilayer 1-bit ALU is designed based on the proposed full
counterpart designs in terms of cell number, area, latency, adder and the application-specific QCA 4:1 multiplexer to
and power consumption. perform 12 different operations includes four logical and eight
arithmetic operations. Moreover, structural and energy
Index Terms— Quantum-dot Cellular Automata (QCA), efficiency of the proposed structures are evaluated in
Central Processing Unit (CPU), Arithmetic Logic Unit (ALU), comparison to the comparative designs.
Multiplexer, Full adder. The rest of this paper is organized as follows: the related
works are reviewed in section 2. The proposed structures
I. INTRODUCTION including QCA 4:1 multiplexer and full adder are introduced in

G ENERALLY, CMOS as well-known technology is applied in

the design of current Very Large Scale Integration (VLSI)
circuits, which some difficulties of this technology such as
section 3. Moreover, the proposed QCA ALU structure is
provided in section 4. Section 5 inspects complexity of the
proposed structures and compares them with the counterparts.
physical, material, power-thermal, technological and economic Finally, section 6 concludes the paper.
challenges have led to appearing QCA as a new technology to
overcome these limitations. This technology due to its II. RELATED WORKS
proprietary specifications such as extremely small feature size
at the molecular, or even atom level, ultra-low power In recent years, various structures have introduced to improve
consumption, and high component density can be considered an the efficiency of the ALU components. However, there are only
appropriate alternative for transistor-based technology [1].

This paragraph of the first footnote will contain the date on which you A. S. Author is with the Department of Computer Engineering, Tabriz
submitted your paper for review. It will also contain support information, Branch, Islamic Azad University (IAU), Tabriz, Iran (e-mail:
including sponsor and financial support acknowledgment. For example, “This [email protected] ).
work was supported in part by the U.S. Department of Commerce under Grant AN. B. Author is with the Department of Information and Communication
BS123456.” Technology, Mawlana Bhashani Science and Technology University
S. B. Author is with the Department of Computer Engineering, Tabriz (MBSTU), Santosh, Tangail - 1902, Bangladesh (e-mail:
Branch, Islamic Azad University (IAU), Tabriz, Iran (e-mail: [email protected]).
[email protected] ).

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a few structures that have been proposed for QCA ALU include TABLE I
OPERATIONS OF THE PROPOSED QCA ALU.
full adder, multiplexer, and various logic gates in an integrated
structure with the detail of their designs. Moreover, QCA full Operations Mode S1 S0 Cin OUT
adder is an important block in the arithmetic units because
0 0 0 × A⊕ B
multiplication and subtraction operations can be carried out Logical 0 0 1 × A^ B
through the successive sum operation and two’s complement,
respectively. Diverse designs have presented for QCA full 0 1 0 × A˅ B
adder, which classified into the single layer [3]–[8] and multiple 0 1 1 × A'
layer schemes. In addition, the multiplexer is a necessary 1 0 0 0 A
component in the implementation of the Field Programmable 1 0 0 1 A+1
Gate Array (FPGA), Controlled Logic Block (CLB), ALU,
1 0 1 0 A-1
GPU, and memory modules. The existing multiplexers can be Arithmetic
classified into the single layer [9]–[12] and multilayer circuits. 1 0 1 1 A
Likewise, the existing QCA ALUs can be classified into 1 1 0 0 A+B
reversible [13] and non-reversible [14]–[16] designs. 1 1 0 1 A+B+1
Unfortunately, most of the authors of the ALU designs have not 1 1 1 0 A+B'
clear the necessary information about their designs such as the 1 1 1 1 A-B
number of cells, area, and latency. Therefore, comparison our
proposed ALU with most of these designs will be impossible. B. Design of a QCA multiplexer for arithmetic unit
The list of arithmetic and bitwise logical operations of the
III. PROPOSING QCA STRUCTURES proposed QCA ALU is illustrated in Table I. The arithmetic
A. Design of a QCA full adder operations of Table I have specific features, so that sum
operation is fixed in all eight arithmetic functions. Therefore,
Generally, Full Adder (FA) is one of the most frequently
all arithmetic operations can be easily performed with the
utilized components in the arithmetic operations [17]. This
proposed full adder. Moreover, according to these operations,
block in addition to the sum operation can be applied in other
in four cases when Cin is equal to '0' (Cin = 0), corresponding
arithmetic operations such as multiplication, division, and
operations have an addition with '0', also, in other operations
subtraction. The FA is a three-input digital circuit that when Cin is equal to '1' (Cin =1) sum with ‘1’ is fixed. In
calculates the sum of the two digits (A and B) as operands and
addition, operand 'A' and addition with input carry (Cin) are
one bit (Cin) as quoting from the previous adder; also, produces
fixed in all eight arithmetic operations, so that they can be
two outputs i.e., Sum (S) and Carry Out (Cout). In a full adder,
connected to the full adder directly. By deleting operand 'A',
the Carry Out and Sum can be calculated by Eqn. 1 and Eqn. 2,
'addition with ‘0’', and 'addition with ‘1’' from Table I,
respectively.
remaining values including '0', '1', 'B', 'B' should be entered to
the full adder in the various circumstances. Table II illustrates
𝐶𝑎𝑟𝑟𝑦 𝑂𝑢𝑡 = 𝑎𝑏 + 𝑎𝑐 + 𝑏𝑐 = 𝑀(𝑎, 𝑏, 𝑐) (1) the inputs of the full adder in various circumstances and
corresponding Karnough map.
𝑆𝑢𝑚 = 𝑎 ⊕ 𝑏 ⊕ 𝑐 (2)
TABLE II
Where M, represents the majority gate. In the proposed FA, Inputs of the full adder in various circumstances
(a) Truth table (b) Karnough map.
Sum output is generated based on the explicit interactions
between the QCA cells, also Carry output is generated based on
S1 S0 Out
the majority voter. As shown in Fig.1, the proposed full adder
0 0 0
includes two fundamental components i.e., majority voter and
three-input XOR gate. The proposed structure has only 26 cells 0 1 1
and implemented in a single layer. In the QCA designs of this 1 0 B
paper, green, purple, blue, and yellow cells represents the clock
zone ‘0’, ‘1’, ‘2’, and ‘3’, respectively. 1 1
B'
(a) (b)
As a result, in the proposed application-specific QCA 4:1
multiplexer an endeavor is made to provide the expected
outputs. Therefore, the output of the proposed application-
specific QCA 4:1 multiplexer can be generated by Eqn. (3).

𝑍2 = [(𝑆̅1 𝑆̅0 × 0) + (𝑆̅1 𝑆0 × 1) + (𝑆1 𝑆̅0 × 𝐵) + (𝑆1 𝑆0 × 𝐵̅ )]

= [(𝑆̅1 𝑆0 ) + (𝑆1 𝑆̅0 𝐵) + (𝑆1 𝑆0 𝐵̅ )] (3)

(a) (b) The output of the proposed QCA 4:1 multiplexer is Sum-of-
Fig. 1. Proposed QCA full adder structures (a) Logical diagram (b) QCA layout.
Products (SoP) canonical form. Equation 3 can be rewritten in
the standard canonical form as follows in Eqn. 4.

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𝑍2 = [(𝑆̅1 𝑆0 × (𝐵 + 𝐵̅ )) + (𝑆1 𝑆̅0 × 𝐵) + (𝑆1 𝑆0 × 𝐵̅ )] (4)

= [(𝑆̅1 𝑆0 𝐵) + (𝑆̅1 𝑆0 𝐵̅ ) + (𝑆1 𝑆̅0 𝐵) + (𝑆1 𝑆0 𝐵̅ )]

Equation 4 can be rewritten in the simplified form as follows

in Eqn. 5.

𝑍2 = [𝐵(𝑆̅1 𝑆0 + 𝑆1 𝑆̅0 ) + 𝑆0 𝐵̅ (𝑆1 +𝑆1̅ )] (5)

= [𝐵(𝑆1 ⊕ 𝑆0 ) + 𝑆0 𝐵̅ ]

Therefore, the proposed application-specific QCA 4:1

multiplexer is based on the Eqn. 5. The layout of the proposed
QCA 4:1 multiplexer and its logical diagram are shown in Fig.
Fig. 3. Logical diagram of the proposed 1-bit ALU.
2.
(a)

(a) (b) (b)

Fig. 2. (a) QCA layout (b) Logical diagram, of the proposed

application-specific QCA 4:1 multiplexer.

C. Design of a QCA multiplexer for logical unit

The logical unit must able to carry out the XOR, AND, OR,
and NOT operations. This unit is designed based on the cell
interaction. This unit is shown in Fig. 3 and it generates 𝑍1 as (c)
output, which 𝑍1 can be generated by Eqn. 6.

𝑍1 = 𝑆̅1 𝑆̅0 (𝐴 ⊕ 𝐵) + 𝑆̅1 𝑆0 (𝐴𝐵)

+𝑆1 𝑆̅0 (𝐴 + 𝐵) + 𝑆1 𝑆0 (𝐴̅) (6)

= 𝑆̅1 𝑆̅0 𝐴̅𝐵 + 𝑆̅1 𝑆̅0 𝐴𝐵̅ + 𝑆̅1 𝑆0 𝐴𝐵 + 𝑆1 𝑆̅0 𝐴 + 𝑆1 𝑆̅0 𝐵 + 𝑆1 𝑆0 𝐴̅

Equation 6 can be rewritten in the simplified form as follows

in Eqn. 7. (d)

̅ + 𝑆̅0 𝐴
𝑍1 = 𝑆1 𝑆0 𝐴 ̅𝐵̅ + 𝑆̅1 𝑆̅0 𝐴 + 𝑆̅1 𝐴
̅(𝑆0 ⊕ 𝐵
̅) (7)

We have designed Eqn. 7 as logical unit of the proposed ALU

structure. (e)

IV. DESIGN OF QCA ALU BASED ON THE PROPOSED

STRUCTURES
An ALU can carry out basic arithmetic operations such as
sum, subtraction, multiplication, and division, also, bitwise
logical operations such as NOT, AND, and OR on integer Fig. 4. QCA layout of the proposed multilayer 1-bit ALU (a) Layer 1,
binary numbers. Typically, binary information in computers is (b) Layer 2, (c) Layer 3, (d) Layer 4, (e) Layer 5.
represented in 16-, 32- and 64-bit quantities. However, to make
our design, we have concentrated our design concepts in present V. SIMULATION AND EXPERIMENTAL RESULTS
work on using 1-bit quantities. The 16-, 32- and 64-bit ALU can The proposed designs are validated by the QCADesigner
be designed in the same manner. The logical diagram and version 2.0.3 at the clock rate of 1 THz as the QCA simulation
multilayer QCA layout of the proposed 1-bit ALU circuit are engine rate and QCAPro in terms of structural evaluations and
shown in Fig. 3 and Fig. 4, respectively.

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4

measure power consumption, respectively. Moreover, it is

TABLE IV
assumed that the cooling penalty or other temperature related
COMPARISON OF THE DIFFERENT QCA SINGLE LAYER 4:1 MULTIPLEXERS.
problems are considered in these tools. 4:1 multiplexer Cell Area Latency Crossover
designs count (µm2) (clock cycle) type
A. Structural evaluations
[9] 61 0.08 4 Coplanar
In the simulation, an endeavor is made to apply exhaustive [10] 107 0.15 1 Coplanar
vector set to evaluate the correctness of the proposed designs. [11] 114 0.17 5 Not required
The simulation results of the proposed QCA 4:1multiplexer,
[12] 107 0.17 5 Coplanar
FA, and 1-bit ALU are depicted in Fig. 5(a), Fig. 5(b), and Fig.
5(c), respectively. Proposed 42 0.07 1 Not required
multiplexer
B. Comparative Study
TABLE V
In Table III, Table IV, and Table V the proposed QCA FA, COMPARISON OF THE DIFFERENT QCA FULL ADDERS.
4:1 multiplexer, and ALU are compared with the counterpart ALU Number of Area Latency Crossover
designs. The comparison results demonstrate that proposed designs Operations (µm2) (clock cycle) type
designs outperform in terms of complexity, area, and latency. [13] 12 0.624 N/A Coplanar
Moreover, the proposed ALU with 324 cells can perform more [14] 4 0.78 3 Multilayer
operations in comparison to the comparative designs. [15] 5 0.85 3 Coplanar

C. Power dissipation evaluation [16] 12 0.76 5 Multilayer

The energy dissipation analysis of the proposed application- Proposed 12 0.245 2.25 Multilayer
ALU
specific 4:1 multiplexer and full adder in three distinct Ek
values (0.5, 1 and 1.5 Ek) at 2 K temperature are presented in
Table VI. Ek (known as kink energy) is the energetic cost of VI. CONCLUSION
two neighboring cells having opposite polarizations. In general, In this paper, a new multilayer QCA ALU structure has been
increasing the Ek lead to increasing the error rate. Therefore, it proposed to carry out the arithmetic and bitwise logical
has been tried to choose the proper Eks to optimize the error operations. Moreover, due to the exploited features of the
and power in the proposed circuits. The total power dissipation arithmetic operations of the proposed ALU, a new application-
by a QCA cell is calculated using a Hamiltonian matrix that specific QCA 4:1 multiplexer has been proposed. The
uses Hartree-Fock approximation and considers the Coulombic simulation results show The proposed 4:1 multiplexer has
interaction between them by a mean-field approach [18]. designed with 42 cells, 0.07 µm2 area, and 1 clock cycle latency;
TABLE III whereas the best previous design has 61 cells, 0.08 µm2 area,
COMPARISON OF THE DIFFERENT QCA FULL ADDERS. and 4 clock cycles latency. In addition, to reduce the complexity
Full adder Cell Area Latency Crossover
designs count (µm2) (clock cycle) type of the sum related operations, an efficient full adder has been
[3] 35 0.0288 1 Not required proposed. The comparisons results show that the proposed FA
[4] 29 0.02 0.5 Coplanar
has 7 cells less than the best previous single layer design. The
proposed structures have been integrated as 1-bit QCA ALU to
[5] 33 0.02 0.5 Coplanar
perform 12 various operations. Simulation results show that its
[6] 53 0.047 0.75 Coplanar area is 0.245 µm2 and 2.25 clock cycles delay whereas the best-
[7] 41 0.03 4 Not required published design has 0.724 µm2 area.
[8] 46 0.04 4 Not required
Proposed 26 0.03 0.5 Not required
full adder

TABLE VI
ENERGY CONSUMPTION ANALYSIS OF THE DIFFERENT 4:1 MULTIPLEXERS AND FULL ADDERS.
Avg. leakage energy dissipation Avg. switching energy dissipation Avg. energy dissipation of circuit
(meV) (meV) (over all vector pairs)
0.5 Ek 1 Ek 1.5 Ek 0.5 Ek 1 Ek 1.5 Ek 0.5 Ek 1 Ek 1.5 Ek
[9] 19.67 55.91 96.46 59.28 49.57 41.11 78.95 105.48 137.57
[11] 51.68 153.72 272.64 208.34 158.47 134.69 260.02 312.19 407.33
Proposed Multiplexer 15.53 42.26 72.21 45.89 38.91 32.8 61.42 81.17 105.01

[3] 10.66 31.57 55.44 54.19 46.19 40.18 64.85 78.36 95.63
[6] 31.2 83.79 140.62 65.84 60.83 49.51 97.04 144.62 190.13
[7] 14.05 39.32 68.02 50.61 44.67 38.95 64.66 83.99 106.97
Proposed FA 8.83 25.97 45.62 37.24 31.80 26.84 46.07 57.76 72.47

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5

(a)

(a)

(b)

(c)
Fig. 5. Simulation results of the proposed QCA circuits (a) 4:1 multiplexer, (b) full adder, (C) 1-bit ALU.

vol. 512, no. January, pp. 91–99, 2017.

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