RN SHETTY TRUST®

RNS INSTITUTE OF TECHNOLOGY

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DEPARTMENT OF CSE-CYBER SECURITY

Question Bank
SUBJECT CODE AND TITLE BCS302 Digital Design and Computer Organization
SCHEME 2022 BATCH 2023-27
SEMESTER& SECTION III
FACULTY NAME
LATHA P

Module -1

Q. Bloom’s
Questions COs
No. LL

1 List and explain all the basic Postulates and Theorems of Boolean Algebra. L1 CO1
Using the basic theorems and postulates of Boolean algebra, simplify the
2 L3 CO1
following Boolean expression: F = x′y′z + xyz + x′yz + xy′z.
Develop a truth table for the Boolean expression F = x′y′z.
3 L2 CO1
Show the Logic diagram for the Boolean function F1 = x + y′z.
Show the two Implementations of the Boolean function with gates:
4 L3 CO1
Simplify the following Boolean expressions to a minimum number of
5 literals. L3 CO1
1. x(x′ + y) 2. x + x′y 3. (x + y)(x + y′) 4. xy + x′z + yz
Explain with an example the procedure to find the Complement of a
6 L2 CO1
Function.
Find the complement of the functions F1 = x′yz′ + x′y′z and F2 = x(y′z′ +
7 L3 CO1
yz).
Draw the graphic symbols and truth tables of following gates: AND, OR,
8 L2 CO1
invertor, buffer, NAND, NOR, XOR, XNOR.
A. Implement the function F = A(CD + B) + BC’ using AND-OR gates
and NAND gates.
9 B. Implement the Boolean function F(w, x, y, z) = (y + z′)(wx′ + w′x) with L4 CO1
NOR gates.
C. Implement the function F = (AB’ +A’B)(C + D’) with NOR gates.
A. What is a Hardware description language? Explain its importance.
10 B. Explain the VERILOG HDL Design Encapsulation in detail. L4 CO1
C. Give the Verilog Model of a simple circuit.
Module -2
Q. Bloom’s
Questions COs
No. LL
1 Define combinational logic. Explain a combinational circuit with block L2 CO2
diagram.
2 Give the procedure for designing a combinational circuit. L2 CO2
1
3 Explain Code Conversion with an Example. Sketch a neat Logic diagram CO2
L2
for BCD-to-excess-3 code converter.
4 Explain how a half adder and a full adder differ in their functionality. L2 CO2
5 Explain the relationship of VHDL constructs with truth tables, Boolean CO2
L2
equations, and schematics three-state gates.
6 What is Gate-Level Modeling? Give the Truth Table for Predefined CO2
L2
Primitive Gates.
7 Give the gate-level description of a two-to-four-line decoder in VHDL. L2 CO2
8 Explain the working of a Four-bit adder–subtractor (with overflow L3 CO2
detection).
9 With truth table and logic diagram, analyze the working of 3 to 8 line L4 CO2
decoder.
10 Draw and explain the Logic diagram of carry lookahead generator. Discuss L4 CO2
its drawback?
Module -3
Q. Bloom’s
Questions COs
No. LL
1 What is performance measurement? Write the basic performance equation.
L1 CO1
Discuss SPEC rating to assess performance of a computer.
2 What is straight line sequencing? L1 CO1
3 What is word alignment of a machine? What are the consecutive addresses
L1 CO1
of aligned words for 16, 32 and 64 bit word lengths of machines?
4 Define an addressing mode. With example explain any two. L2 CO2
5 Define : Big-Endian, Little-Endian, Word Alignment L2 CO2
6 With suitable diagram discuss the connection between processor and
L2 CO2
memory. Explain the functions of processor registers.
7 Show how the operation C=A+B can be implemented in a single
accumulator computer by (i) Three address instruction (ii) Two address L3 CO2
instruction (iii) One address instruction
8 Indicate the significance of condition code flags. L3 CO2
9 List the basic steps needed to execute the machine instruction Move
L4 CO2
(R3),R2.
10 Register R1 and R2 of a computer contain the decimal values 1200 and
4600. What is the effective address of the memory operand in each of the
following instructions:
A) Load 20(R1), R5 L5&L6 CO2
B) Move #3000, R5
C) Store R5, 30(R1,R2)
D) Add -(R2), R5
E) Sub (R1)+, R5
Module -4
Q. Bloom’s
Questions COs
No. LL
1 Define memory mapped I/O and I/O mapped I/O. L2 CO4
2 What are exceptions? List its types. L2 CO4
3 Define the following: (i) cycle stealing (ii) burst mode (iii) full handshake L2 CO4
4 Explain memory hierarchy and trade off between cost, space, and speed. L3 CO4
5 Define cache memory. Explain the different mapping techniques. L3 CO4

2
 6 Why is bus arbitration required? Explain with block diagram, the bus L2 CO4
arbitration using Daisy Chain .
7 Explain the timing diagram of an input transfer on a synchronous bus. L2 CO4
8 How to solve recursive interrupt problem? L3 CO4
9 How simultaneous requests are handled? L3 CO4
10 The input status bit in an interface circuit is cleared as soon as the input L4 CO4
data buffer is read. Why this is important?
11 Give the timing diagram to illustrate read operation using synchronous bus. L4 CO4
Module -5

Q. Bloom’s
Questions COs
No. LL

1 With a neat sketch of single bus organization of the data path inside a L2 CO4
processor, explain the three steps to be performed by the processor to
execute an instruction.
2 Write and explain the control sequence for execution of a conditional L2 CO4
branch instruction.
3 Discuss register transfer Move R1,R4 with sequence of operations. L2 CO4
4 Explain the control steps for the instruction that performs arithmetic or L3 CO4
logic operation.
5 Explain storing a word in memory with required sequence of operation. L3 CO4
6 Explain fetching a word from memory with required sequence of operation. L3 CO4
7 Write the sequence of control steps to perform actions for the instruction L3 CO4
add R3, (R1) using a single bus structure.
8 Explain the idea of Instruction pipelining. L3 CO4
9 Discuss 4-stage pipeline with neat diagrams and hardware organization. L3 CO4
10 Discuss pipeline performance. Analyze the various hazards. L4 CO4

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