Introduction to Embedded Systems

EHB326E
Lectures

Prof. Dr. Müştak E. Yalçın

Istanbul Technical University

[email protected]

Prof. Dr. Müştak E. Yalçın (İTÜ) EHB326E (V: 0.1) September, 2018 1 / 23
Describing the desired behaviour :Algorithmic State
Machines (ASM)
Flowchart
Convenient way to graphically specify sequence of procedural steps and
decision paths for algorithm
Enumerates sequence of operations and conditions necessary for
execution
Algorithmic State Machine (ASM)
Flowchart defined specifically for digital hardware algorithms
Flowchart vs. ASM
Conventional flowchart
Sequential way of representing procedural steps and decision paths for
algorithm
No time relations in corporated
ASM chart
Representation of sequence of events together with timing relations
between states of sequential controller and events occurring while
moving between steps
Prof. Dr. Müştak E. Yalçın (İTÜ) EHB326E (V: 0.1) September, 2018 2 / 23
Algorithmic State Machines (ASM)
State box Decision box Conditional box

The chart must define a unique next state for each state and set of
condition.
Every path defined by the network of conditions boxes must lead to
another state.
- Block has one entrance and any number of exits paths
- Each block in ASM dedicated to state of system during one clock cycle
- Can label just the “1” and omit the “0”
Prof. Dr. Müştak E. Yalçın (İTÜ) EHB326E (V: 0.1) September, 2018 3 / 23
One’s counter: State and Input-based charts

Source: D. Gajski, Principles of Digital Design

Prof. Dr. Müştak E. Yalçın (İTÜ) EHB326E (V: 0.1) September, 2018 4 / 23
 A conditional output box must
follow a decision box.
Decision box has two or more A conditional output box is
branches. attached to a state box through
The state represented by the one or more decision boxes.
state box takes a clock cycle Decision is made based on the
to complete. value of one or more input signals. Therefore, the output signals in
the conditional output box are
The output signals in the box Decision box must follow and be
asserted in the same clock cycle
take the specified values associated with a state box.
as those in the state box to whic
during this clock cycle. Thus, the decision is made in the it is attached.
The signal (x=1) is assigned same clock cycle as the other
The output signals can change
during the next clock cycle actions of the state.
during that state as a result of
and holds its value until Hence, the input signals must be changes on the inputs.
otherwise set elsewhere. available and valid at the start of
The conditional output signals a
the clock cycle.
sometimes referred as Mealy
outputs since they depend on th
input signals as well.

Prof. Dr. Müştak E. Yalçın (İTÜ) EHB326E (V: 0.1) September, 2018 5 / 23
Timing

Prof. Dr. Müştak E. Yalçın (İTÜ) EHB326E (V: 0.1) September, 2018 6 / 23
FSM to ASM

Prof. Dr. Müştak E. Yalçın (İTÜ) EHB326E (V: 0.1) September, 2018 7 / 23
FSM & ASM

ASM Representation of a Mealy Machine (Input-based):

Prof. Dr. Müştak E. Yalçın (İTÜ) EHB326E (V: 0.1) September, 2018 8 / 23
FSM & ASM
ASM Representation of a Moore Machine (State-based):

Prof. Dr. Müştak E. Yalçın (İTÜ) EHB326E (V: 0.1) September, 2018 9 / 23
ASMs to FSMDs

Prof. Dr. Müştak E. Yalçın (İTÜ) EHB326E (V: 0.1) September, 2018 10 / 23
ASMs to FSMDs

Prof. Dr. Müştak E. Yalçın (İTÜ) EHB326E (V: 0.1) September, 2018 11 / 23
Example : ASM to Application-specific processor

Source: D. Gajski, Principles of Digital Design

Prof. Dr. Müştak E. Yalçın (İTÜ) EHB326E (V: 0.1) September, 2018 12 / 23
Design Technology

The system specification:

The designer describes the desired functionality in some language, often a
natural language like English, but preferably an executable language !

Designers must spend much time and effort simply understanding and
describing the desired behaviour of a system, and some studies have found
that most system bugs come from mistakes made describing the desired
behaviour rather than from mistakes in implementing that behaviour.

D. Gajski, F. Vahid, S. Narayan and J. Gong, ”Specification an Design of embedded systems,” page 10 - 13.

Prof. Dr. Müştak E. Yalçın (İTÜ) EHB326E (V: 0.1) September, 2018 13 / 23
Program to FSMD

The system specification

" compute a greatest common divisor of two inputs"
0: int x, y;
1: while (1) {
2: while (!go i);
Black-box view 3: x = x i;
4: y = y i;
5: while (x != y) {
6: if (x < y)
7: y = y - x;
else
8: x = x - y;
}
9: d o = x;
}

Prof. Dr. Müştak E. Yalçın (İTÜ) EHB326E (V: 0.1) September, 2018 14 / 23
Templates for Program statement to FSMD
Assignment statement Loop statement Branch statement
a = b while (cond) { if (c1)
next statement loop-body- c1 stmts
statements else if c2
} c2 stmts
next statement else
other stmts
next statement

Prof. Dr. Müştak E. Yalçın (İTÜ) EHB326E (V: 0.1) September, 2018 15 / 23
Algorithm→ Templates → FSMD

0: int x, y;
1: while (1) {
2: while (!go i);
3: x = x i;
4: y = y i;
5: while (x !=
y) {
6: if (x < y)
7: y = y - x;
else
8: x = x - y;
}
9: d o = x;
}

Step1 Behavioral Specification !

Prof. Dr. Müştak E. Yalçın (İTÜ) EHB326E (V: 0.1) September, 2018 16 / 23
Register Transfer Level (RTL) specification (Step2 )
Define I/O and Create a register for any declared variable

Prof. Dr. Müştak E. Yalçın (İTÜ) EHB326E (V: 0.1) September, 2018 17 / 23
Register Transfer Level (RTL) specification (Step2 )
Create a functional unit for each arithmetic operation

Prof. Dr. Müştak E. Yalçın (İTÜ) EHB326E (V: 0.1) September, 2018 18 / 23
Register Transfer Level (RTL) specification (Step2 )
Connect the ports, registers and functional units

Prof. Dr. Müştak E. Yalçın (İTÜ) EHB326E (V: 0.1) September, 2018 19 / 23
Step3
Create unique identifier

Prof. Dr. Müştak E. Yalçın (İTÜ) EHB326E (V: 0.1) September, 2018 20 / 23
Step4
Creating the controller’s FSM: Replace complex actions/conditions with
datapath configurations

Prof. Dr. Müştak E. Yalçın (İTÜ) EHB326E (V: 0.1) September, 2018 21 / 23
Creating the controller’s FSM:

How to design combinational logic in the controller ? Figure 2.12, page: 43

Optimizing single-purpose Processor ! (Read Chp. 2.6)
Prof. Dr. Müştak E. Yalçın (İTÜ) EHB326E (V: 0.1) September, 2018 22 / 23
Asynchronous serial transmitter unit, Github

Github:uart tx.v

Asynchronous serial receiver unit, Github

Source: Juan González-Gómez, GitHub

Prof. Dr. Müştak E. Yalçın (İTÜ) EHB326E (V: 0.1) September, 2018 23 / 23