Chapter -2

Hardware and Software Design Issues

A processor is a digital circuit designed to perform computation task. A processor consists of
data path capable of storing and manipulating data and a controller is capable of moving data
through data path. A general-purpose processor is designed such that it can carry out a wide
variety of computation task, which are described by a set of instructions.

In contrast, a single purpose processor is designed specifically to carry out a part task. While
some tasks are so common that we can purchase standard single-purpose processor to
implement those tasks, other is best implemented using custom single processor to implement
those tasks.

It is possible that certain subsystems in hardware (microcontroller), IO memory accesses, real-

time clock, system clock, pulse width modulation, timer and serial communication are also
implemented by the software. A serial communication real-time clock and timers featuring
microcontroller may cost more than the microprocessor with external memory and a software
implementation. Hardware implementations provide advantage of processing speed.

Two approaches for the embedded two approaches for the embedded system design are follows
as below.
 When the software development cycle ends then the cycle begins for the process of
integrating the software into the hardware at the time when a system is designed.
 Both cycles concurrently proceed when co-designing a time critical sophisticated
system.

Software Design Methodology:

In general, the design of a system with software based needs a design entry as programming
language like C, C++ etc. The design flow is shown in Fig... In this methodology the constraints
are with respect to area but not speed. The system design information can be specified by using
user requirements to the system designer. The user requirements are verified according to the
target board (like processor), area, speed and other nonfunctional constraints. If the user
requirements satisfy existing elements then the design will move forward, otherwise user has
to refine the requirements. General programming languages like C, C++ etc. can be used as the
design entry and compilation will be done to check the functionality is with respect to
specifications or not. Finally, hex file or bit file is generated according to the target device.

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The advantage of this design process is easy to design and implement with less area but timing
issues and speed cannot be improved. The timing issues and speed can be considered by using
the hardware-based design methodology.

Hardware Design Methodology:

The systems with hardware components considering timing can be designed by using a
programmable device like PLA, PAL, PGA, FPGA or a non-programmable device like ASIC.
The systems behavior can be expressed by using a Hardware Description Language like Verilog
HDL, VHDL etc. instead of a programming language. These HDL languages describe the
timing behavior of the hardware elements. The design flow for an FPGA is shown in figure
below:

Combinational and Sequential Logic:

1. Combinational Logic Circuit
Combinational logic refers to circuits whose output is a function of the present value of the
inputs only. As soon as inputs are changed, the information about the previous inputs is lost,
that is, combinational logic circuits have no memory.

2. Sequential Logic Circuit

Sequential logic circuits are those whose outputs are also dependent upon past inputs, and hence
outputs. In other words, the output of a sequential circuit may depend upon its previous outputs
and so in effect has some form of "memory". The mathematical model of a sequential circuit is

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usually referred to as a sequential machine. The general block diagram of a sequential switching
circuit is shown below:

Sequential circuits are basically combinational circuits with the additional properties of storage
(to remember past inputs) and feedback.

Transistor:
A transistor is a basic electrical component in digital system. It acts as a simple ON/OFF switch.
Transistor are abstracted to construct the logic gates in higher level. One type of transistor is
complementary metal oxide (CMOS) which is more popular in combinational circuit design
and corresponding technology is called CMOS technology. CMOS transistor are two types:
1. nMOS Transistor
2. pMOS Transistor

We can apply low or high levels to the gate of the CMOS transistor. We refer logical levels i.e.
logic 0 is 0V and logic 1 is 5V.

nMOS Transistor:
- When logic 1 is applied to gate, the transistor conducts and current flows from source to drain.
- When logic 0 is applied to gate, the transistor doesn’t conduct and high resistance is developed
about 10 MΩ along source to drain.

pMOS Transistor:
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When logic 0 is applied to gate, the transistor conducts and current flows from source to drain.
When logic 1 is applied to gate, the transistor doesn’t conduct and high resistance is developed
about 10 MΩ along source to drain

Implementations of Logic gates using CMOS

1. Invertor (NOT)
 When the input “x” is logic 0, the upper transistor conducts and lower transistor does
not conduct. Thus logic 1 is appears as output “F”.
 Similarly, when the input “x” is logic 1, the upper transistor does not conduct and lower
transistor conducts. Thus logic 0 is appears as output “F”.

2. NAND Gate

 When one of the input “A” or “B” is logic 0 then at least one of the upper transistors
and lower conducts. Thus, logic 1 is appears as output “F”.
 When both input “A” or “B” is logic 0 then neither of the upper transistor conducts but
both lower conducts. Thus, logic 0 is appears as output “F”.

3. NOR Gate

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  When both input “A” or “B” is logic 0 then both of the upper transistor conducts but
both lower does not conducts. Thus logic 1 is appears as output “Y”.
 When both input “A” or “B” is logic 1 then both of the upper transistor does conducts
but both lower does conducts. Thus logic 0 is appears as output “Y”.
 When one of the input “A” or “B” is logic 0 then at least one of the upper transistor
and lower conducts. Thus logic 0 is appears as output “Y”.

Logic Gates:
The Digital Logic Gate is the basic building block from which all digital electronic circuits and
microprocessor-based systems are constructed from. Basic digital logic gates perform logical
operations of AND, OR and NOT on binary numbers.

Digital logic gates may have more than one input, (X, Y, Z, etc.) but generally only have one
digital output, (F). Individual logic gates can be connected together to form combinational or
sequential circuits, or larger logic gate functions.

Basic Combinational Logic Design:

Combinational logic refers to circuits whose output is a function of the present value of the
inputs only. Combinational logic circuits have no memory. The design procedure includes
following steps:
a. Determine the no of input and output of system from the problem
specifications.
b. Derive truth table for each output from their relationship with number of
inputs.
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 c. Simplify the Boolean expression using K-maps & obtain logic equations.
d. Draw logic diagram (sharing common gates).
e. Simulate circuit for design verification.
f. Optimize the circuit for area and/or performance using different optimization
metric.
g. Re -simulate & verify optimized design.

For example: a combinational circuit that have three input say A, B and C and will give
a single output X as logic 1 if the binary number consists more 1’s than 0’s.

Design a combinational circuit for the problem: “y is 1 if a is 1, or b and c are 1, z is 1 if b

or c is 1, but not both, or if all are 1”.

Design a combinational circuit for output y and z where y is 1 when a is 1 or b and c are
1 and z is 1 if b or c is 1 but not all i.e. a and b and c are 1.

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Truth Table:

Construct K map and find Bolean Expression for each output.

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Draw the logic circuit to implement the expressions

Design a 2 bit comparator circuit that have one single output “less than” using the
approach of combinational design technique
Truth Table

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 Boolean expressions

Circuit Diagram

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RT-level Combinational Component:
All digital circuit can be designed as the procedure stated as above but it is difficult and complex
so higher abstract level of combinational logic devices are used in resister transfer level design.
Some of the component are:

1. Multiplexer:

A digital multiplexer is a combinational circuit that selects binary information from one of
many input lines and directs it to a single output line.

A multiplexer sometimes called as a selector, always only one its data input Im passed through
the o/p. Thus multiplexer acts much like a railroad switch, allowing multiple input tracks to a
single track as output.
- If there are “m” data inputs then it consists log2 (m) selection inputs lines “S”. We call this an
m-by-1 MUX.
- The binary inputs to “S” determines which input line is connected to O/P.
 0000…….0000 means the input I0 passed through
 0000…….0001 means the input I1 passed through
 0000…….0010 means the input I2 passed through
 And so on…………..
2. Decoder
Discrete quantities of information are represented in digital systems with binary codes. A binary
code of n bits is capable of representing up to 2n distinct elements of the coded information.
Decoder is a combinational circuit that converts binary information from n input lines to a
maximum of 2n unique output lines.

A decoder converts the binary input combinations “I” into a one-hot output. One-hot means
that exactly one output line can be 1 at a given time.
Thus, there are n-outputs, then there must be log2 (n) then it is called as log2 (n) by n decoder

3. Adder:

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An n-bit adder adds two n-bit data say A and B at a time and generates carry and sum as an
output. A half adder adds bits without carry whereas the full adder ( 3 bit adder) adds bits with
previous carry.

4. Comparator:

An n-bit comparator compares n –bit data say A and B and generates the output as A<B or A>B
or A=B.

5. Arithmetic-Logic Unit (ALU)

An n-bit ALU can perform arithmetic and logical calculations on n-bit data inputs A and B.
The selection input “S” determines the operation that is going to perform.

Sequential Logic Components:

Their output values are computed using both the present and past input values. In other words,
their outputs depend on the sequence of input values that have occurred over a period of time.
This dependence on the past input values requires the presence of memory elements. The values
stored in memory elements define the state of a sequential component. Since memory is finite,
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therefore, the sequence size must always be finite, which means that the sequential logic can
contain only a finite number of states. So sequential circuits are sometimes called finite-state
machines. Sequential circuits can be a asynchronous or synchronous.
Asynchronous sequential circuits change their state and output values whenever a change in
input values occurs. Synchronous sequential circuits change their states and output values at
fixed points of time, which are specified by the rising or falling edge of a free-running clock
signal. Clock period is the time between successive transitions in the same direction, i.e.,
between two rising or two falling edges. Clock frequency = 1/clock period Clock width is the
time during which the value of the clock signal is equal to 1. Duty cycle is the ratio of clock
width and clock period. Active high if the state changes occur at the clock's rising edge or
during the clock width. Active low if the state changes occur at the clock's falling edge. Latches
and flip flops are the basic storage elements that can store one bit of information. The basic
components with their properties are shown below.

The characteristic table is a shorter version of the truth table that gives for every set of input
value and the state of the flip-flop before the rising edge, the corresponding state of the flip-
flop after the rising edge of the clock. It is used during the analysis of sequential circuits.

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The characteristic equation is just the functional expressions derived from the characteristic
(truth) table. It formally describes the functional behavior of a latch or flip-flop. They specify
the flip-flop’s next state as a function of its current state and inputs.

The excitation table gives the value of the flip-flop inputs that are necessary to change the flip-
flop’s present state to the desired next state after the rising edge of the clock signal. It is obtained
from the characteristic table by transposing input and output columns. It is used during the
synthesis of sequential circuits.
RT-level Sequential Component:
1. Register
A register stores the n-bits from its input “I” with those n bits appearing at output line “Q”.
A register usually has at least two control input, clock and load. For a raising edge triggered
register, input is usually drawn as a small triangle as shown in fig.
Another common control unit is clear, which resets all bits to value “0” regardless the value of
“I”.
All input bits are loaded in parallel so it is called as parallel load register.
2. Shift Register:

 A shift registers stores n bit but they cannot be stored in parallel. Instead they must be
shifted into the register i.e. one bit at a single clock.
 The register has at least a data input “I” that holds a single bit at a time and control
input shift that is used to insert a data.
 When clock is raising mode the shift equals 1 such that the data bits in “I” is inserted
into “n” bit position of register while nth bit is inserted into (n-1)th bits and (n-1) bit into
(n-2) and so on.
 The first bit is usually shifted to the output end “Q”.

3. Counter:

 A counter is a register that can be also increment, meaning add the binary value 1, to
its stored binary value. A counter has a control input clear that resets all bits of register
to vale “0” and count input that increments the value of stored number by 1 in each
raising edge of clock.
 A counter has also a load input to load the n –bit data in parallel.
 Commonly a counter operates in both mode as down and up. The up counter increments
the value stored in register by 1 and down counter decrements the contents of register
by value 1 up to define level. Mode M counter counts from 0 to M-1 or M-1 to 0. For
this it requires another control input as Count UP/DOWN.
 These control input may be
o Synchronous
o Asynchronous
 A synchronous input value only have effect during in a clock edge.
 An asynchronous value effects the circuit independent of clock.

Design Procedure to Sequential Circuit Design:

The design of a clocked sequential circuit starts from a set of specifications (state table) and
ends in a logic diagram or a list of Boolean functions from which the logic diagram can be
obtained. The procedure can be summarized by a list of consecutive recommended steps:

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 1. State the word description of the circuit behavior. It may be a state diagram, a timing
diagram, or other pertinent information.
2. From the given information about the circuit, obtain the state table.
3. Apply state-reduction methods if the sequential circuit can be characterized by input-
output relationships independent of the number of states.
4. Assign binary values to each state if the state table obtained in step 2 or 3 contains letter
symbols.
5. Determine the number of flip-flops needed and assign a letter symbol to each.
6. Choose the type of flip-flop to be used.
7. From the state table, derive the circuit excitation and output tables.
8. Using the map or any other simplification method, derive the circuit output functions
and the flip-flop input functions.
9. Draw the logic diagram.

Design Examples:
Construct a clock divider. Slow down your pre-existing clock so that you output a 1 for
every four clock cycles.

State Diagram

State table and truth table

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Boolean Expression

Combinational Circuit

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Design the 3- bit counter that counts the sequence as 1,2,3,4,5,6,7,1,2,3,…etc. . This
counter has output “odd” whose value is 1 when it counts odd. Design the circuit by using
sequential circuit design technique.
State diagram:

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Truth Table

Boolean Expression

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Logic Circuit

Four lights are connected to decoder. Built a circuit that will blink the lights in the order 0, 2,
3, 1, 0, 2……….. Start from state diagram draw the finial circuit.

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Design a soda controller machine given that a soda costs 75 cents and your machine
accepts quarters only. Draw the black box view, come up with state diagram, and draw
the finial circuit.

Sequence Recognizer (Moore)

A sequence recognizer is a special kind of sequential circuit that looks for a special bit pattern
in some input. The recognizer circuit has only one input, X
- One bit of input is supplied on every clock cycle
- This is an easy way to permit arbitrarily long input sequences

There is one output, Z, which is 1 when the desired pattern is found. Our example will detect
the bit pattern ―1001‖:
Inputs: 1 1 1 101 1 0 1 10 1 101 1 0…
Outputs: 0 00 001 00 0 00 1 001 0 0…
A sequential circuit is required because the circuit has to ―remember‖ the inputs from previous
clock cycles, in order to determine whether or not a match was found. The corresponding state
diagram is:

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1.Design a sequence detector to detect a sequence ----1010---- using D flip-flops and logic
gates.

State diagram

The state table for above state diagram is as follows:

State assignments: Let S0S0 = 00, S1S1 = 01, S2S2 = 10, S3S3 = 11
The above state table becomes:

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Four states will require two flip flops. Consider two D flip flops. Their excitation table is
shown below.
Excitation table:

K-maps to determine inputs to D Flip flop

Circuit diagram for the sequence detector

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2. Design a sequence detector that produces a true output whenever it detects the
sequence 010 at its input.
(Assignment)

Custom Single-Purpose Processor Basic Model:

 The data path stores and manipulates the system data. Examples of data in embedded
system includes binary numbers representing external conditions like temperature or
speed, the character to be displayed on the screen or digitized photographic image to
be stored and compressed.
 The data path consists register unit, functional unit, and connection unit like wires and
multiplexer.

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  The data path can be configured to read the data from register, fed that data into the
functional unit configured to carry the operations like add, subtract, shift etc. and stores
the result back to the designated register.
 A controller caries out the configuration of data path. It sets the data path control signals
like load input to register, select inputs for selecting the register, operation selection for
functional unit and connection unit to obtain the desired configuration at particular
instant of time.
 It monitors the external control input as well as data path control outputs known as
status signal, coming from the functional units and it sets the external control output as
well.
 The combinational or sequential logic can be applied to design controller and data path.

Statements:
Statements are used to implement the logical operation, data flow and control flow during the
custom single processor design. Some of the useful statements are:
1. Assignment statements
2. Loop statements
3. Branch statements

Assignment Statements:
Assignment statements are used to initialize the fixed data into a variable or transfer of data
from one variable to another. For example a =5, b = 10, d= a etc. It is used to create a single
state and available for next statement.

Loop Statements:
The control statement are represented by the loop statements. For loop statement:
We create condition statement C and a join state J, both have no action.
- We add an arc with the loop’s condition state to in first statement in loop body.
- We create the second arc with the complement of the loop’s condition from the
condition state to next statement after the loop body.

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Branch Statements:
Branch statements are used to alter the execution order of statements with or without
condition. For branch statements:
We create the condition statement C with a join statements J both with no action.
We create the arc from the first branch statement from the condition statement.
We add another arc with the complement
of first branch condition ANDed with second branch condition from the first statement of first
branching condition. We repeat this for all branching conditions.
Finally we connect the arc leaving the last statement of each branch to join state and we add
an arc from this state to next statement state.

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Steps to Design Single Custom Processor
Steps:
1. Draw a black box that shows the abstract view of the implementation logic.
2. Derive the algorithms to implement the functionality of system.
3. Derive the state diagram to implement the operational logic in terms of control flow,
dataflow and applicable logic using different statements.
4. Design the data path, functional unit as well as controller to implement the complex logic
specified in step 2.

For example: design of custom single processor to find the GCD (HCF) of given two
numbers
Suppose Xi and Yi be the two input numbers, go be the control input and do is the GCD of Xi
and Yi such that the black box, functionality and state diagram be designed as below be
represented as:

The data path can be designed as below:

• Create a register for any declared variable
• Create a functional unit for each arithmetic operation
• Connect the ports, registers and functional units
Based on reads and writes
Use multiplexors for multiple sources
• Create unique identifier for each datapath component control input and output

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The controller of the above functionality is:
• Same structure as FSMD and convert it to FSM.
• Replace complex actions/conditions with data path configurations

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Controller state table for the GCD

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Optimization of Single Processor Design
The finite state machine uses the number of states so thaht they can be reduced without
halting the operation. The machine can be optimized by optimizing different parameter as
below:
- Original program
- FSMD
- Data path
- FSM for controller
1. Optimization of Original Program:

The program can be optimize by optimizing the no of computation, size of variable, time and
space complexity, operation used like multiplication and division may have the higher cost etc.
for example:

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Here subtract operation is replaced by modulo operation, the program be optimized in terms of
number of computation as well as space and time complexity.

2. Optimization of FSMD:
FSMD can be optimized by using different concepts as merge state, separate state and
scheduling. Those states they have constant value or independent with change then they can be
merged and so called merged state. The state with complex logic can be replaces by no of sub
operation with simpler logic that reduce the hardware complexity and so called as separate state.
By optimization of scheduling time, we can optimize the FSMD. For example:

Eliminate the state -1 that consists constant value.

 Merge the state 2 and 2-J since there is no loop operation in between them.
 Merge the state 3 and 4 since they are independent to each other.
 Merge the state 5 and 6 since transition from state 6 can be done from 5.
 Eliminate state 6-J and 5-J since it can be done from state 7 and 8.
 Eliminate the state 1-J since it can be done through state 9.

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3. Optimizing Data Path:
To optimize the data path, a sheared functional unit can be used such that there is a optimized
datapath and able perform the verity of operation. For this purpose we can use the sheared ALU
circuit that supports verity of state equation as well as state operations. For example: for
operation X-Y and Y-X, instead of using two sub tractor we can generate the result.

4. Optimizing FSM for Controller:

The FSM of controller can be optimize by reducing the states and using efficient state encoding.
The n bit encoded binary bits can define 2n different states and n bits can generate the n!
Combinations. The states can be merged into a single state such that it provides the optimize
FSM.

Software Design Issues: General Purpose Processor

The general purpose processor sometimes called as central processing unit (CPU) or a
microprocessor. It consists of a datapath and a control unit, tightly coupled with memory as
shown above fig. the general purpose basic architecture consists of:
- Datapath
- Control unit
- Memory

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Data path:
The data path consists the circuitry to transfer the data from one place to another and storing
the temporary data. The datapath contains the ALU capable of transferring the data from
different operation like additions, subtraction, bitwise OR, AND etc. ALU also generates the
status signals often stored in status register. These status bit conditions are known as flags. The
flags may be zero, sign carry overflow etc. It also contains register and stores the data
temporarily during ALU operation. The temporary data includes:
- Data read from memory but not yet send to ALU.
- Result from ALU operation that is used for next operation or going to write on
memory.
The capacity of processor measured by bandwidth of datapath i.e. data carrying capacity. The
n-bit size processor consists:
- N bit registers set
- N bit internal and external system bus
- N bit ALU

The processor size may be 4, 8, 16, 32 or 64 bit.

Control Unit
It consists a circuitry that generates the control signal to read the instruction stored in
memory, its execution and transferring the data from datapath, storing the result on memory
and IO operation. A register called as program counter (PC) that is use to sequence the
program i.e. it points the address of next instruction that is going to fetch and execute.
Another register called as instruction register (IR) is used to hold the instruction read from
memory. The register called as Address Register (AR) is used to store the memory address
during memory read/write operation. The control unit has a controller, consisting of a status
register plus next state and control logic. It controls the data flow on datapath and such flow
includes:
- Inputting the two particular register for ALU operation.
- Storing the ALU results in particular register.
- Moving the data between memory and register.

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An m bit sized address memory consists the address space of 2m and controller goes through
the following operation to execute an instructions.
- Fetching the instruction from memory.
- Decode the instruction.
- Fetch the operand from memory
- Perform the operation on memory.
- Store the result.

Memory:
Registers are used as the short term storage whereas memory is used as the mid-term
and long –term storage. Memory be classified as:
- Program Memory
- Data memory

The program memory is used to store the sequence of instruction called as program which is
use to achieve a given functionality whereas data memory use to store the data information
and represents the values of input, output, and transformed by program. We can store the data
and program together or separately. The memory architecture follow the following two
model:
- Princeton Architecture
The Princeton architecture shares the common memory space to store the data and
program and requires one to one connection with hardware.
- Harvard Architecture
The Harvard architecture uses the separate memory space to store program as well as data and
requires different connection. The microcontroller 8051/52 follow this model

Instruction Execution:
The instruction be executed in microprocessor by taking following steps:
i. Fetch Instruction (FI): It is a task that reads the instruction from memory
pointed by PC and loaded into the instruction register.
ii. Decode Instruction (DI): In this phase, an instruction be decoded to separate
the operand reference as well as operation code to represent the particular
operation as ADD, MOV, AND, SUB etc.
iii. Fetch Operand (FO): In this stage, the operand be read from the memory
represented by the effective address (EA). EA calculation is needed for
indirect address.
iv. Execute Instruction (EI): In this phase, the instruction be executed in
accordance with its opcode an operand and generates the result.
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 v. Store Result (SR): The result is stored on the particular destination that may
be register or memory.

Pipeline for Instruction Execution: The pipeline is a common process to increase the
instruction throughput of a microprocessor..
The instruction pipeline can be carried to execute the instruction in five independent segments
as specified above as FI, DI, FO, EI and SR. The instruction pipeline structure be constructed
as:

Programmer View:
A programmer writes the program instruction carryout the desired functionality on GPP. For
this purpose, programmer doesn’t need to know about the detailed structure of the processor
where as he/she need to know how instruction be executed. There are three levels of
programming:
1. Assembly Level
2. Structure level
3. Machine level

Assembly Level: An assembly language is a low-level programming language for

microprocessors and other programmable devices. It is not just a single language, but rather a
group of languages. An assembly language implements a symbolic representation of the
machine code needed to program a given CPU architecture. Assembly language is also known
as assembly code. The term is often also used synonymously with 2GL. The assembler is
needed to convert the assembly code into machine code.
Structure Level: Structured programming is a logical programming method that is
considered a precursor to object-oriented programming (OOP). Structured programming
facilitates program understanding and modification and has a top-down design approach,

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where a system is divided into compositional subsystems. These languages are machine
independent and need a compiler to convert them into machine code.
Machine Level: Sometimes referred to as machine code or object code, machine language is
a collection of binary digits or bits that the computer reads and interprets. Machine language
is the only language a computer is capable of understanding.

Operating System:
An Operating System (OS) is an interface between a computer user and computer hardware.
An operating system is a software which performs all the basic tasks like file management,
memory management, process management, handling input and output, and controlling
peripheral devices such as disk drives and printers. An operating system is a program that acts
as an interface between the user and the computer hardware and controls the execution of all
kinds of programs.

The system call provides an interface to the operating system services. Application developers
often do not have direct access to the system calls, but can access them through an application
programming interface (API). The functions that are included in the API invoke the actual
system calls. By using the API, certain benefits can be gained:
 Portability: as long a system supports an API, any program using that API can
compile and run.

 Ease of Use: using the API can be significantly easier than using the actual system
call.

Development Environment:
The development environment is comprise of the general software tools they are used to
design, testing, validation and verification of embedded system software. The software be
developed in general processor called as development processor then it sis burned to the
target embedded processor.
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Embedded Systems Programming requires a more complex software build process:
- Target hardware platform consists of target hardware (processor, memory, I/O) and
Runtime environment (Operating System/Kernel).
- Target hardware platform contains only what is needed for final deployment.
- Target hardware platform does not contain development tools (editor, compiler,
debugger).

Target hardware platform is different from development platform

- Development platform, called the Host Computer, is typically a general purpose
computer.
- Host computer runs compiler, assembler, linker, locator to create a binary image that
will run on the Target embedded system.

An Integrated Development Environment (IDE)

An Integrated Development Environment (IDE) is software that assists programmers in
developing software. IDEs normally consist of a source code editor, a compiler, a linker/locater
and usually a debugger.

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Sometimes, an IDE is devoted to one specific programming language or one (family of) specific
processor or hardware but more often the IDEs support multiple languages, processors, etc.
Some commonly used IDEs for embedded systems are the GNU compiler collection (gcc),
Eclipse, Delphi etc.

Editor
A source code editor is a text editor program designed specifically for editing source code to
control embedded systems. It may be a standalone application or it may be built into an
integrated development environment (e.g. IDE). Source code editors may have features
specifically designed to simplify and speed up input of source code, such as syntax highlighting
and auto complete functionality. These features ease the development of code.

Compiler
A compiler is a computer program that translates the source code into computer
language (object code). Commonly the output has a form suitable for processing by
other programs (e.g., a linker), but it may be a human readable text file. A compiler
translates source code from a high level language to a lower level language (e.g.,
assembly language or machine language). The most common reason for wanting to
translate source code is to create a program that can be executed on a computer or on
an embedded system. The compiler is called a cross compiler if the source code is compiled
to run on a platform other than the one on which the cross compiler is run. For embedded
systems the compiler always runs on another platform, so a cross compiler is needed.

Linker
A linker or link editor is a program that takes one or more objects generated by compilers and
assembles them into a single executable program or a library that can later be linked to in itself.
All of the object files resulting from compiling must be combined in a special way before the
program locator will produce an output file that contains a binary image that can be loaded into
the target ROM. A commonly used linker/locater for embedded systems isld (GNU).

Debugger
A debugger is a computer program that is used to test and debug other programs. It is a piece
of software running on the PC, which has to be tightly integrated with the emulator that you
use to validate your code. A Debugger allows you to download your code to the emulator's
memory and then control all of the functions of the emulator from a PC.

Process for Developing Embedded Software

1. Develop software for a General Purpose Computer:

2. Develop software for an embedded system

memory addresses to code and data (on Host)

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Compiling Embedded Systems:
Compiler translates program written in human-readable language into machine language:
- Source Code --> Object file
- Object file is binary file that contains set of machine-language instructions (opcodes)
and data resulting from language translation process

The process of converting the source code into object file is called compiling. Machine-
language instructions are specific to a particular processor and platforms are different for
development. The complier that runs on a computer platform and produces code for that same
computer platform called as Native-compiler. The compiler that runs on one computer
platform and produces code for another computer platform is called Cross-compiler.

Assembling/Interpreters for Embedded Systems:

In some cases, a compiler is not used. In this case assembler and interpreter is used.
Assembler performs one-to-one translation from human-readable assembly language
mnemonics to equivalent machine-language opcodes and this process is called assembling.
Interpreter constantly runs and interprets source code as a set of directives

- can be ~1000x slower than an equivalent compiled

language ª
-- easier to learn
Handyboard runs a C interpreter called Interactive C

Linking Embedded Systems:

The Linker combines object files (from compiler) and resolves variable and function references
and corresponding process is called linking.
- Source code may be contained in >1 file, which must be combined
- Resolve variables which may be referenced in one file and defined in another file
- Resolve calls to library functions, like sqrt
- May include operating system
Linker creates a relocatable version of the program.

Locating Embedded Systems:

- A Locator is the tool that performs the conversion from relocatable program to executable
binary image and corresponding procedure is called locating.
- The Locator assigns physical memory addresses to code and data sections within the
relocatable program
- The Locator produces a binary memory image that can be loaded into the target ROM
- In contrast, On General Purpose Computers, the operating system assigns the addresses at
load time

Executing Embedded System Program:

Once a program has been successfully compiled, linked, and located, it must be moved to the
target platform. Executable binary image is transferred and loaded into a memory device on
target board.

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Debugging Tools:
When it comes to debugging your code and testing your application there are several different
tools you can utilize that differ greatly in terms of development time spend and debugging
features available. In this section we take a look at simulators, and emulators.

Simulators try to model the behavior of the complete microcontroller in software. Some
simulators go even a step further and include the whole system (simulation of peripherals
outside of the microcontroller). No matter how fast you’re PC, there is no simulator on the
market that can actually simulate a microcontroller's behavior in real-time. Simulating
external events can become a time-consuming exercise, as you have to manually create
"stimulus" files that tell the simulator what external waveforms to expect on which
microcontroller pin. A simulator can also not talk to your target system, so functions that rely
on external components are difficult to verify. For that reason simulators are best suited to test
algorithms that run completely within the microcontroller.

An emulator is a piece of hardware that ideally behaves exactly like the real microcontroller
chip with all its integrated functionality. It is the most powerful debugging tool of all. A
microcontroller's functions are emulated in real-time.

Embedded Product Development Lifecycle:

Concept
- Description of the original idea in a formal technical form (verbal requirements)
- Investigation of the existing prototypes and/or models that match the idea
- Comparative analysis of existing implementations
- Proposal of implementation and materials options

Design
Functional Requirements
- Development of hardware functional specification
- Development of software and firmware functional requirements
- Analysis of the third-party requirements documentation

Architecture Design
- Development of the system architecture concept

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 - Design of the mechanics parts/molding of the system
- Development of hardware design documentation (including FPGA design)
- Development of the detailed software design specification
- Analysis of the third-party design documents

Hardware Modeling
- Schematics design
- PCB Layout Design
- Re-engineering and repairing
- Samples & Prototypes Assembly

Prototyping
- Product prototyping (including all types of mechanics, hardware, software and the
whole system prototyping)
- Mechanical parts manufacturing (including molding/press forms manufacturing) –
Hardware development
- Software and firmware coding
- System integration (software with hardware and mechanics)

Application Specific Processor (ASPs)

General purpose processors are designed to execute multiple applications and perform
multiple tasks. General purpose processors can be quite expensive especially for small
devices that are designed to perform special tasks. Also general purpose processors might
lack high performance that a certain task required. Therefore, application specific processors
emerged as a solution for high performance and cost effective processors. Application
specific processors have become a part of our life’s and can be found almost in every device
we use on a daily basis. Devices such as TVs, cell phones, and GPSs they all have a form of
application specific processors. An application specific processor combines high
performance, low cost, and low power consumption.

Application specific processors can be classified into three major categories:

- Digital Signal Processor (DSP): Programmable microprocessor for
extensive real-time mathematical computations.
- Application Specific Instruction Set Processors (ASIP): Programmable
microprocessor where hardware and instruction set are designed together for
one special application.
- Application Specific Integrated Circuit (ASIC): Algorithm completely
implemented in hardware.

Application Specific Systems

Some of the typical approaches of building an application specific system or an embedded
system are to use one or more of the following implementation methods: GPP, ASIC or ASIP.
4. GPP:

Functionality of the system is exclusively build on the software level. Although the biggest
advantage of such system is the flexibility but it is not optimal in term of performance, power
consumption, cost, physical space and heat dissipation.
5. ASIC:

Compared to GPP, ASIC based systems offer better performance and power consumption but
at the cost of flexibility and extensibility. Although it is difficult to use the ASIC for tasks
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other than what they were designed for, but it is possible to use GPP to perform the more
general less demanding tasks in addition to ASIC in the same system.
6. ASIP:
In this approach, an ASIP is basically a compromise between the two extremes; The
Application specific integrated circuit processors ASIC being designed to do mostly a very
specific job with high performance but with minimal room for modifications and the general
purpose processors which costs a lot more than ASIP but with extreme flexibility at what they
do. Due to this flexibility and low price, ASIP are great to be used in embedded and system-
on-a-chip solutions.

Table below shows the comparison between the three approaches in term of performance and
flexibility and other design considerations.

Application-Specific Instruction Set Processors

An ASIP is typically a programmable architecture that is designed in a specific way to
perform certain tasks more efficiently. This extra efficiency is not exclusively associated with
faster performance. Other factors like reduced production costs, simplified manufacturing
process and less power consumption can all be considered efficiency qualities for ASIP. The
term “Application” in ASIP is not necessarily related to software applications, it actually
describe the class of tasks the ASIP platform was designed to efficiently accomplish. As the
name suggests, the Instruction set seems to be the core characteristic of any ASIP based
platform; but this is entirely not true. Considering a whole platform, other very important
attributes like interfaces and micro-architecture do contribute a lot to the overall system
performance.

Interfaces outline how the system and the architecture communicate with each other. Having
only an extremely parallelized instruction-set ASIP in a data extensive processing platform
doesn’t mean necessarily a more efficiently performing system. For example, if the load/store
unit cannot handle data processing as quick, there will be a performance bottle-nick due to
system interfaces. Similarly for the micro-architecture, the pipeline of the ASIP must be
designed in a specific way that optimizes the performance of the whole system.

A traditional RISC stages (Fetch, Decode, Execute, memory & write-back) might not be the
optimal pipeline for the application. Specifically designing any of these aspects of ASIP will
be always associated with trade-offs. Having an extremely parallelized instruction-set will
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propose issues with the size of the instruction-set and it will affect the program memory,
interfaces and fetch & decode stages of the pipeline.

There are many advantages of using a ASIPs as compared to GPP. The following are the
major ones:

- Speed: The hardware of ASIPs is spacially tailored to execute the applications

specific instruction. For example an image processor may have an instruction
differentiating the input values or may have the instruction for recognizing a bit pattern
in communication interface circuit. The hadware is designed to implement the
instruction so provides the faster processing.
- Reprogram ability: ASIPs can be reprogrammed. The scope of program executed
by an ASIPs may be limited to particular application, but still feature of
reproggrammability gives the flexibility, though limited, for upgrades and
modifications. This saves the time and cost.
- NRE: ASIPs are not designed for a specific single task, they are designed for class of
task. Unlike single purpose processor, they can be reprogrammed when application
requirement changes. Thus the cost of engineering work for producing an ASIC can be
distributed which lowers the overall cost. For same task ASIPs are cheaper than single
purpose processor.

- Power Consumption: compared to GPP, an ASIPs may consume less power. An

ASIPs designed to execute specific task; it would not contain unnecessary hardware
components required by GPP. It implies lower the hardware lower the cost.
The importance of ASIPs cannot be undermined when there is an increasing use of
microprocessor controlled system. The availability of hardware unit including the
processor in HDL allows one to implement the processor in ASIP form.

Selecting a Processor:
The selection basis is the requirement, what the processor needs to do. A processor may be
selected on the basis of following parameters.

1. Speed:
How fast a processor can compute has always been a point of high interest for designers and
developers. There is always demand for fast processors. But good practice is to use a
processor required by application. A data logging application that records temperature in
every 5 minutes might not require a faster processor but a X-ray machine in the emergency
ward should have faster one. MIPS (Millions instruction set second) is also used to measure
Speed.

2. Instruction Set:
The instruction set defines what a processor can do. Based on task to be performed, an
additional set of instruction or totally different instruction set may be required. In robotic
system the processor for driving a motor and analyzing an environment are required to
perform different task, instruction set may be different for them.

3. Bit/ Word Length:

It is a size of data the processor can handled, the length of register around processor. If
processor needs to process floating point data, the word length that works for integer type
data is no sufficient. A narrower option may works but takes more time.

4. Power Consumption:
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Power consumption may not a deciding factor for fixed system but when it comes to a
portable handheld device, it becomes a crucial point. Both the standby and peak power
consumption of processor are to be considered. For example, the low power consumed by
mobile phone in standby or sleep and active mode should low.

5. Prior Experience:
While working in a project, a designer would chose a processor with which he has experience.
The availability of development and libraries for the SW for a processor contributes to the
performance.

6. Size:
The actual physical size of the processor may impact the design when the trend is going for
slim smart devices. Everything, including processor is required to be small.

7. Cost:
The price of the processor is the ultimate selection factor. The available project budget may
not accommodate expensive processor then designer selects the low cost processor.
Other factors may be type/ version, no of register etc., may also be used as selection criteria.

General Purpose Processor Design:

The general purpose processor design follows the states as like in singe processor design as:

1. Create a FSMD to describe a behavior of processor. I.e. design instruction set.

2. Built the data path to carry the data flow between different functional units.
3. Rewrite the FSMD to FSM
4. Design the FSM controller.
1. Instruction Set Design:
 defnes the various operations
 determines the number of registers and memory size required.
 a number of operation and kind of operation must be considered.
 a number of operands,, type of operators, and location of operands must be selected.
 size and format of instruction must be selected.

2. Creating FSMD:
It represents state diagram of given instruction set functionality.
The execution of instruction requires following steps:
1. Fetch Instruction (FI): It is a task that reads the instruction from memory pointed
by PC and loaded into the instruction register.
2. Decode Instruction (DI): In this phase, an instruction be decoded to separate the
operand reference as well as operation code to represent the particular operation as
ADD, AND, SUB etc.
3. Fetch Operand (FO): In this stage, the operand be read from the memory
represented by the effective address (EA). EA calculation is needed for indirect
address.
4. Execute Instruction (EI): In this phase, the instruction be executed in accordance
with its opcode an operand and generates the result.

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 5. Store Result (SR): The result is stored on the particular destination that may be
register or memory.

3. Build Datapath
The design of data follows from the instruction set. Each expression shown in FSMD are
carried out by different functional unit. The datapath must contain the functional units
required by instruction. The operation of functional unit is define by the control unit.
These control signal are generated from the controller. A MUX is used to select the
functional units, memory and register used in data path. The data path must be able to transfer
the information about address, data and control.
The main tasks performed in datapath may be :
- for each declared variable, we need to initiate a storage device.
- initiate functional unit to carry out FSMD operation.

4. Development of FSM/Controller
The controller is a finite state machine that goes from one to another state and its design
involves sequential design processor. The state diagram be different but procedure is almost
same.
- rewrite the FSMD states without instruction or operations.
- equivalent binary operations on control signal must be written in each state rather
than the operation.
- each operation with binary operation.

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