UNIT-5

Microcomputer System Basics

Table of contents:

• Commercial microprocessors list (single bit to 128 bits)

• Microcomputer system ALU, Register Unit, Control Unit)
• Various Registers in CPU
• System Bus (Address bus, data bus, control bus)
• Memory types and Memory organisation
• Microcomputer Input/Output (I/O) methods
• Data transfer scheme
• Classification of digital system buses (Link buses, Expansion slot buses, I/O buses)
• Fetch and Execute cycles
• Addressing modes
• Instruction set
• Subroutine.
Commercial microprocessors list (single bit to 128 bits)

• There was a curious single-bit microprocessor introduced in 1977, the MC14500B from Motorola, CMOS technology
encapsulated in a 16-pin DIP (Dual-In-Line (DIL) Package, cf. § 3.3 of Darche (2004)).
• It was clocked at about 1 MHz.
• It was actually an Industrial Control Unit (ICU) called by this same company PLC for Programmable Logic Controller.
• Its instruction set included 16 instructions.
• There was no address bus.
• A memory was addressed sequentially using an external binary counter.
• Intel, moreover, seems to have associated for an intelligent Input–Output (I/O) controller an 8-bit microprocessor
responsible for executing the control program in ROM (ReadOnly Memory) integrated and a single bit (Petritz 1977)
whose instructions were stored in a programmable logic circuit of PLA type (Programmable Logic Array).
Single bit microprocessor:
This type of architecture should not be confused with that of a central unit which works internally at the bit level (serial

calculation) but presents a larger format externally .

4-bit family:
• The 4-bit family was the first generation. Table 4.1 presents the main characteristics of the first components of this
generation. LSI (Large-Scale Integration) manufacturing technology is essentially PMOS, which involves at least two
supply voltages.
• It shows the internal architecture of the 4004. It has a single internal data bus.
• It consists of an ACC (accumulator) register, 16 working registers (MPX registers) and a stack consisting of three 12-bit
registers which contain instruction addresses.
• The MF7114 from the Canadian company Microsystems International Limited (MIL) was designed and produced from this
first MPU (Stachniak 2010) and named “the Intel 4005”.
• It was part, with RAM (Random Access Memory) MF7115 and ROM MF1601, of a set of three components referenced
MP-1.
• Three peculiarities for the time were its addressing capacity of 256 KiB, the fact that the eight data registers and the eight
12-bit address registers resided in primary memory and, finally, that the I/O ports were also implemented in main memory.
• It should be noted that the 4040, an improved version of the 4004, included its entire set of instructions (notion of
backward compatibility, cf. § V4-3.3.3) to which were added 14 other instructions, in particular of a logical type.
• The interest of the PPS-4 lies in an internal four-phase clock and a data search in 8-bit format and a few I/O lines as for a
microcontroller.
• Its particular case included four rows of 10, 11, 11 and 10 pins respectively.
8-bit family
• Its successor, the 8080, is very close from an architectural point of view
• It adds 30 new instructions to the 48 that it shares with its predecessor.
• They vary in size.
• Its cycle time is typically 2 µs, an improvement factor of the order of 6.
• With it, the call stack disappears in favor of a stack pointer which manages the latter in RAM, instead “modern” for all
MPUs.
• The work registers also disappear. It inaugurates the buses of addresses and separate data externally.
• The program/data and I/O address spaces (cf. § 2.1.1.1) are separate.
• This intermediate generation is characterized by improvements such as a generalization of the single supply voltage thanks
to the introduction of NMOS and CMOS technologies, an integrated clock circuit or a simplification of the bus control
signals.
• The addressing capacity is de facto “standardized” to the value of 64 KiB
12-bit family
• There are not only families that process integers in format n which is a power of 2.
• The circuits referenced IM6100 and IM6120 from the company Intersil and manufactured in CMOS technology (Thomas
1976) are two examples.
• Its instruction set was compatible (cf. § V4-3.3.2) with the PDP-8 from DEC (DEC).
• The TLCS12 from Toshiba in NMOS technology is a second example (Ogdin 1975; Mori et al. 1977).

16-bit family
The 16-bit generation marks a turning point because technology makes it possible to implement high-level concepts such as
the (primary) memory protection offered, for example, by virtual memory (mechanism detailed in the second work on
microprocessors) and the supervisor execution mode, these protections being necessary for modern operating systems
The technology of the 9440 Microflame™ is bipolar.
It offers, with its 50 instructions and its eight addressing modes, 2,192 possible operation codes compatible with NOVA1200.
32 bit family:

• The first is called RISC (Reduced Instruction Set Computer).

• The second is Instruction-Level Parallelism (ILP).
• The RISC approach consists mainly and, as the name suggests, of reducing the number of instructions to the bare minimum
and optimizing their execution.
• It comes in opposition to the CISC (Complex Instruction Set Computer) approach.
• The parallelism in the instructions comes from research that began during the late 1960s–early 1970s (Jouppi 1989).
• It brings together techniques for designing families of processors and compilers to break with sequential execution.
• It was first implemented in supercomputers and mainframe computers.
• Then, these techniques appeared in microprocessors from the 1980s to accelerate the execution of instructions, more
particularly those relating to the transfer between CPU and main memory (and vice versa) and to arithmetic calculations for
whole and floating numbers.
• Increasing performance means executing more than one instruction per processor cycle
Microcomputer system ALU, Register Unit, Control Unit)
• Microcomputer systems are small and inexpensive computers that are widely used in various applications. The 8085
microprocessor is an example of a Microcomputer System. A microprocessor system contains two types of memory that are
EPROM and R/WM, Input and Output devices, and the buses that are used to link all the periphera
The Microprocessor Unit (MPU)
• The MPU is the brain of the microcomputer system. It contains the arithmetic and logic unit (ALU) and the control unit
(CU) that work together to execute instructions. The 8085 microcomputer system has 16 address lines ranging from A0 to
A15 that are used to address memory. The lower-order address bus A0-A7 is used to identify the input and output devices.
• ls (memory and I/Os) to the MPU.
Memory
• There are two types of memory in the microcomputer system: Erasable Programmable Read-Only Memory (EPROM) and
Random-Access Read-Write Memory (R/WM). EPROM is a type of memory that can be programmed once and can be
erased by exposing it to ultraviolet light. R/WM is a type of memory that can be both read and written to. The MPU
communicates with memory through memory read and memory write control signals.
Input and Output (I/O) Devices
• The microcomputer system contains input and output (I/O) devices that allow the system to interact with the external
environment. The microcomputer system has 8 data lines, D0-D7, which are bidirectional and common to all devices. The
microcomputer system generates four control signals: memory read, memory write, I/O read, and I/O write. These signals
are connected to different peripheral devices.
Interfacing Devices:

• The MPU communicates with only one peripheral device at a time by enabling that peripheral through its control
signal.
• For example, to send data to the output device, the MPU places the device address (or output port number) on the
address bus, data on the data bus, and enables the output device by using its control signal I/O Write. After that, the
output device displays the result.
• The other peripheral devices that are not enabled remain in a high impedance state called Tri-state.
• The bus drivers increase the current driving capacity of the buses, the decoder decodes the address to identify the
output port, and the latch holds data output for display
• These devices are called Interfacing devices. Interfacing devices are semiconductor chips that are necessary to
connect peripherals to the bus system.
• In summary, the microcomputer system is a small and inexpensive computer that contains an MPU, memory, input
and output devices, and buses that connect all the peripherals.
• The microcomputer system communicates with peripherals through control signals, which are connected to different
peripheral devices.
• Interfacing devices are necessary to connect peripherals to the bus system.
The block diagram of a microcomputer system is shown below:
Advantages:
• Flexibility
• Cost-effective
• Compact size
• Ease of use
Disadvantages:
• Limited processing power
• Limited memory capacity
• Limited I/O options
• Limited expansion options
Various Registers in CPU

• In Computer Architecture, the Registers are very fast computer memory which are used to execute programs and
operations efficiently.
• This does by giving access to commonly used values, i.e., the values which are in the point of operation/execution at
that time.
• So, for this purpose, there are several different classes of CPU registers which works in coordination with the
computer memory to run operations efficiently.
• The sole purpose of having register is fast retrieval of data for processing by CPU.
• Though accessing instructions from RAM is comparatively faster with hard drive, it still isn’t enough for CPU.
• For even better processing, there are memories in CPU which can get data from RAM which are about to be
executed beforehand.
• After registers we have cache memory, which are faster but less faster than registers.
• Accumulator:
This is the most frequently used register used to store data taken from memory. It is in different numbers in different
microprocessors.

• Memory Address Registers (MAR):

It holds the address of the location to be accessed from memory. MAR and MDR (Memory Data Register) together
facilitate the communication of the CPU and the main memory.

• Memory Data Registers (MDR):

It contains data to be written into or to be read out from the addressed location.

• General Purpose Registers:

These are numbered as R0, R1, R2….Rn-1, and used to store temporary data during any ongoing operation. Its content can
be accessed by assembly programming. Modern CPU architectures tends to use more GPR so that register-to-register
addressing can be used more, which is comparatively faster than other addressing modes.

• Program Counter (PC):

Program Counter (PC) is used to keep the track of execution of the program. It contains the memory address of the next
instruction to be fetched. PC points to the address of the next instruction to be fetched from the main memory when the
previous instruction has been successfully completed. Program Counter (PC) also functions to count the number of
instructions. The incrementation of PC depends on the type of architecture being used. If we are using 32-bit architecture,
the PC gets incremented by 4 every time to fetch the next instruction.
• Instruction Register (IR):
The IR holds the instruction which is just about to be executed. The instruction from PC is fetched and stored in IR. As
soon as the instruction in placed in IR, the CPU starts executing the instruction and the PC points to the next instruction to
be executed.

• Condition code register ( CCR ) :

Condition code registers contain different flags that indicate the status of any operation.for instance lets suppose an
operation caused creation of a negative result or zero, then these flags are set high accordingly.and the flags are
1. Carry C: Set to 1 if an add operation produces a carry or a subtract operation produces a borrow; otherwise cleared to 0.
2. Overflow V: Useful only during operations on signed integers.
3. Zero Z: Set to 1 if the result is 0, otherwise cleared to 0.
4. Negate N: Meaningful only in signed number operations. Set to 1 if a negative result is produced.
5. Extend X: Functions as a carry for multiple precision arithmetic operations.
• These are generally decided by ALU.
• So, these are the different registers which are operating for a specific purpose
System Bus (Address bus, data bus, control bus):

Buses of computer system

1. Address bus
2. Data bus
3. Control bus

• The buses connect the CPU (microprocessor) to each of the memory and I/O devices.
• The CPU is involved in sending or receiving information to or from memory location, input or output device, and a
secondary memory device (FDD or HDD).
• When the CPU sends data to a device or memory, it is called WRITE operation and when the CPU receives data it is called
READ operation.
• The functions of buses are described now.
Address bus:

• The address bus is unidirectional, information flows over it only in one direction, from the CPU to the memory or I/O
devices. The CPU generates addresses on the lines of the address bus. Each of the addresses corresponds to one memory
location or one I/O device.
• When the CPU wants to communicate with (READ or WRITE), a certain memory location or I/O device, it places the
appropriate address on its address output.
• This address is then decoded to select the desired memory location or I/O device. This decoding process usually requires
address decoder circuits.
Data bus:

• The data bus is bidirectional and data can flow to the CPU through it. The data bus can be either input or output depending
on whether the CPU performs a READ or a WRITE operation.
• The data bus is bidirectional and data can flow to the CPU through it. The data bus can be either input or output depending
on whether the CPU performs a READ or a WRITE operation.

Control Bus

• The control bus consists of a set of signals that are used to synchronize the activities of separate microcomputer elements.
Some of these control signals are sent by the CPU to the other components to tell them the type of operation in progress.
• The I/O devices can send control signals to the CPU. Read/Write, Rest, and interrupt are examples of control signals used
in a microcomputer.
Memory types and Memory organisation:

• In the Computer System Design, Memory Hierarchy is an enhancement to organize the memory such that it can minimize
the access time. The Memory Hierarchy was developed based on a program behavior known as locality of references.The
figure below clearly demonstrates the different levels of memory hierarchy
Design is divided into 2 main types:
1. External Memory or Secondary Memory – Comprising of Magnetic Disk, Optical Disk, Magnetic Tape i.e. peripheral
storage devices which are accessible by the processor via I/O Module.
2. Internal Memory or Primary Memory – Comprising of Main Memory, Cache Memory & CPU registers. This is directly
accessible by the processor.
There are typically four levels of memory in a memory hierarchy:
• Registers: Registers are small, high-speed memory units located in the CPU. They are used to store the most frequently
used data and instructions. Registers have the fastest access time and the smallest storage capacity, typically ranging from
16 to 64 bits.
• Cache Memory: Cache memory is a small, fast memory unit located close to the CPU. It stores frequently used data and
instructions that have been recently accessed from the main memory. Cache memory is designed to minimize the time it
takes to access data by providing the CPU with quick access to frequently used data.
• Main Memory: Main memory, also known as RAM (Random Access Memory), is the primary memory of a computer
system. It has a larger storage capacity than cache memory, but it is slower. Main memory is used to store data and
instructions that are currently in use by the CPU.
• Types of Main memory:
• Static RAM: It stores the binary information in flip flops and information remains valid until power is supplied.
• It has faster access time and is used in implementing cache memory.
• Dynamic RAM: It stores the binary information as a charge on the capacitor.
• It requires refreshing circuitry to maintain the charge on the capacitors after few milliseconds.
• It contains more memory cells per unit area as compared to SRAM.
• Secondary Storage: Secondary storage, such as hard disk drives (HDD) and solid-state drives (SSD), is a non-volatile
memory unit that has a larger storage capacity than main memory.
• It is used to store data and instructions that are not currently in use by the CPU.
• Secondary storage has the slowest access time and is typically the least expensive type of memory in the memory
hierarchy.
We can infer the following characteristics of Memory Hierarchy Design from above figure:
1. Capacity: It is the global volume of information the memory can store. As we move from top to bottom in the Hierarchy,
the capacity increases.
2. Access Time: It is the time interval between the read/write request and the availability of the data.
3. As we move from top to bottom in the Hierarchy, the access time increases.
4. Performance: Earlier when the computer system was designed without Memory Hierarchy design, the speed gap increases
between the CPU registers and Main Memory due to large difference in access time.
5. This results in lower performance of the system and thus, enhancement was required.
6. This enhancement was made in the form of Memory Hierarchy Design because of which the performance of the system
increases.
7. One of the most significant ways to increase system performance is minimizing how far down the memory hierarchy one
has to go to manipulate data.
8. Cost per bit: As we move from bottom to top in the Hierarchy, the cost per bit increases i.e. Internal Memory is costlier
than External Memory.
According to the memory Hierarchy, the system supported memory standards are defined below:
Microcomputer Input/Output (I/O), methods:
• There are three basic methods by which data can be read from or written to a peripheral device and RAM (Random Access
Memory). These input/output methods and communications of microcomputers are:
1. Programmed I/O
2. Interrupt I/O and
3. Direct memory access
Programmed Input / Output (I/O)
• In this technique, the microprocessor is in direct control of all transfers and other I/O operations. This is accomplished with
specific input or output instructions.
• When an input operation is desired, the microprocessor simply issues an input command and awaits the arrival of the
data on the bus. From the bus, the data are moved to memory.
• Similarly, if an output operation is desired, the microprocessor transmits data to the bus and issues and command to the
output device through the appropriate interface.
• Once the data transfer is initiated, the microprocessor mist waits for its completion and the bus to be freed before
beginning a new transfer. This method is commonly used for personal computers because it is effective and easily
implemented.
• Interrupt Input / Output (I/O)

• This is a device that initiated the transfer. An interrupt transfer involves the I/O device sending a request to the processor
through interrupt input (INT, IRQ, etc.) to inform the CPU that the I/O device is ready for data transfer.
• In response, the CPU interrupts the execution of its current program and jumps to a new program called interrupt service
routine which contains instructions to transfer data to or from the interrupting device.

• Direct Memory Address

• This method is fastest is the fastest of the methods. It requires a multi-bus architecture and allows the microprocessor to be
bypassed completely.
• A special direct memory access controller is connected between RAM and an input or output device.
• This method is the most expensive of all and therefore is not used except with very high-speed input/output devices and
only when absolutely necessary.
Data transfer scheme:
• In data transfer schemes, it can provide an efficient means of transmitting data between the processing unit and the I/O
devices.
• In a computer, the data transfer happens between any of these combinations CPU and memory, CPU and I/O devices, and
memory and I/O devices.
• A computer is interfaced with many devices of different speeds.
• Therefore, I/O devices may not be ready to transfer data as soon as the microprocessor issues the instruction for this
purpose.
• Many data transfer schemes have been developed to solve this problem.
Programmed Data Transfer Schemes
• In a programmed data transfer scheme, data transfer takes place between the CPU and I/O device under the control of a
program that resides in the memory.
• In this scheme, the program is executed by the CPU.
• This scheme is used when a limited extent of information is to be transferred.
• The three important types of programmed data transfer schemes are −
• Synchronous Data Transfer Scheme − This type of programmed data transfer scheme is used when the
processor and the I/O devices match in speed. Some suitable instructions such as IN and OUT are used for ‘to and from’
data transfer of I/O devices.
• Asynchronous Data Transfer Scheme − This type of programmed data transfer scheme is used when the speeds
of I/O devices and the microprocessor do not match and also when the timing characteristics of the I/O devices are not
predictable.
• Interrupt Driven Data Transfer Scheme − In this programmed data transfer scheme, the processor enables the
I/O devices and then continues to execute its original program instead of wasting time checking the status of the I/O
devices. When the I/O devices are ready to send and receive data, then the processor is informed through a specific control
line called the ‘Interrupt line’.
• DMA Data Transfer Scheme
• In DMA data transfer, data is directly transferred from the memory to the I/O device or vice versa without going through
the microprocessor.
• This scheme is used when there is a requirement to send bulk data. Transferring bulk data using a microprocessor consumes
more time.
• Therefore, the microprocessor performs the data transfer between an I/O device and memory using this DMA technique.
• For a DMA transfer, I/O devices must also contain electronic circuitry to generate control signals. But most I/O devices are
not equipped with such facilities. Hence, to solve this problem, manufacturers have developed a single-chip programmable
DMA controller to interface I/O devices with the microprocessor for DMA transfer.
Classification of digital system buses (Link buses, Expansion slot
buses, I/O buses):

• The electrically conducting path along which data is transmitted inside any digital electronic device.
• A Computer bus consists of a set of parallel conductors, which may be conventional wires, copper tracks on a PRINTED
CIRCUIT BOARD, or microscopic aluminum trails on the surface of a silicon chip.
• Each wire carries just one bit, so the number of wires determines the most significant data WORD the bus can transmit: a
bus with eight wires can carry only 8-bit data words and hence defines the device as an 8-bit device.
• The bus is a communication channel.
• The characteristic of the bus is shared transmission media.
• The limitation of a bus is only one transmission at a time.
• A bus used to communicate between the major components of a computer is called a System bus.
Computer:
System bus contains 3 categories of lines used to provide the communication between the CPU, memory and IO named as:
1. Address lines
2. Data lines (DL)
3. Control lines (CL)

1. Address Lines:
•Used to carry the address to memory and IO.
•Unidirectional.
•Based on the width of an address bus we can determine the capacity of a main memory
• Data Lines:
• Used to carry the binary data between the CPU, memory and IO.
• Bidirectional.
• Based on the width of a data bus we can determine the word length of a CPU.
• Based on the word length we can determine the performance of a CPU.
Control Lines:

• Used to carry the control signals and timing signals

• Control signals indicate the type of operation.
• Timing Signals are used to synchronize the memory and IO operations with a CPU clock.
• Typical Control Lines may include Memory Read/Write, IO Read/Write, Bus Request/Grant, etc.

Fetch and execute cycle:

Fetch:
In the fetch cycle, the CPU retrieves the instruction from memory. The instruction is typically stored at the address specified
by the program counter (PC). The PC is then incremented to point to the next instruction in memory.
Execute: In the execute cycle, the CPU performs the operation specified by the instruction.
This may involve reading or writing data from or to memory, performing arithmetic or logic operations on data, or
manipulating the control flow of the program.
• At the beginning of the fetch cycle, the address of the next instruction to be executed is in the Program Counter(PC).
• Step 1: The address in the program counter is moved to the memory address register(MAR), as this is the only register
which is connected to address lines of the system bus.
• Step 2: The address in MAR is placed on the address bus, now the control unit issues a READ command on the control
bus, and the result appears on the data bus and is then copied into the memory buffer register(MBR). Program counter is
incremented by one, to get ready for the next instruction. (These two action can be performed simultaneously to save time)
• Step 3: The content of the MBR is moved to the instruction register(IR).
The Execute Cycle:
• The other three cycles(Fetch, Indirect and Interrupt) are simple and predictable.
• Each of them requires simple, small and fixed sequence of micro-operation.
• In each case same micro-operation are repeated each time around.
• Execute Cycle is different from them. Like, for a machine with N different opcodes there are N different sequence of
micro-operations that can occur.
• We begin with the IR containing the ADD instruction.

• Step 1: The address portion of IR is loaded into the MAR.

• Step 2: The address field of the IR is updated from the MBR, so the reference memory location is read.

• Step 3: Now, the contents of R and MBR are added by the ALU.
 Adressing modes:

• The term addressing modes refers to the way in which the operand of an instruction is specified. The addressing mode
specifies a rule for interpreting or modifying the address field of the instruction before the operand is actually executed.
• Addressing modes for 8086 instructions are divided into two categories:
• 1) Addressing modes for data
• 2) Addressing modes for branch
• The 8086 memory addressing modes provide flexible access to memory, allowing you to easily access variables, arrays,
records, pointers, and other complex data types. The key to good assembly language programming is the proper use of
memory addressing modes.
• An assembly language program instruction consists of two parts
• Addressing modes used by 8086 microprocessor are discussed below:
• Implied mode: In implied addressing the operand is specified in the instruction itself. In this mode the data is 8 bits or
16 bits long and data is the part of instruction.Zero address instruction are designed with implied addressing mode.
• Immediate addressing mode (symbol #):In this mode data is present in address field of instruction .Designed
like one address instruction format.
Note:Limitation in the immediate mode is that the range of constants are restricted by size of address field.
• Register mode: In register addressing the operand is placed in one of 8 bit or 16 bit general purpose registers. The data is
in the register that is specified by the instruction.
Here one register reference is required to access the data.
Instruction set:
• The instruction set, also called ISA (instruction set architecture), is part of a computer that pertains to programming,
which is more or less machine language.
• The instruction set provides commands to the processor, to tell it what it needs to do.
• The instruction set consists of addressing modes, instructions, native data types, registers, memory architecture, interrupt,
and exception handling, and external I/O.
Examples of instruction set:
• ADD - Add two numbers together.
• COMPARE - Compare numbers.
• IN - Input information from a device, e.g., keyboard.
• JUMP - Jump to designated RAM address.
• JUMP IF - Conditional statement that jumps to a designated RAM address.
• LOAD - Load information from RAM to the CPU.
• OUT - Output information to device, e.g., monitor.
• STORE - Store information to RAM.
Various types of instruction sets:

• Complex instruction set computer. CISC processors have an additional microcode or microprogramming layer where
instructions act as small programs.
• Programmable instructions are stored in fast memory and can be updated. More instructions are included in CISC
instruction sets than in other types of instruction sets.
• A single instruction can initiate multiple actions by the computer, such as a single add command launching multiple
memory access load and store instructions.
• Reduced instruction set computer. RISC architecture has hard-wired control. It does not require microcode, but has a
greater base instruction set.
• RISC also uses a smaller and more compact instruction set with a fixed instruction format. RISC processors are designed to
process faster and more efficiently.
• Enhancement instruction sets. These instruction types are more familiar because they are often used in marketing CPUs.
Examples of this go back to the 166-megahertz Intel Pentium with MultiMedia Extensions (MMX) technologies.
• It was introduced in 1996 and marketed with enhanced Intel CPU multimedia performance. MMX refers to the extended
instruction set.
Subroutine:
• In computers, a subroutine is a sequence of program instructions that perform a specific task, packaged as a unit.This unit
can then be used in programs wherever that particular task have to be performed.
• A subroutine is often coded so that it can be started (called) several times and from several places during one execution of
the program, including from other subroutines, and then branch back (return) to the next instruction after the call, once the
subroutine’s task is done.
• It is implemented by using Call and Return instructions.
• The different types of subroutine instructions are

Unconditional Call instruction –

• CALL address is the format for unconditional call instruction.

• After execution of this instruction program control is transferred to a sub-routine whose starting address is specified in the
instruction.
• Value of PC (Program Counter) is transferred to the memory stack and value of SP (Stack Pointer) is decremented by 2.
Conditional Call instruction –
Conditional Return instruction –
• Advantages of Subroutine –
1. Decomposing a complex programming task into simpler steps.
2. Reducing duplicate code within a program.
3. Enabling reuse of code across multiple programs.
4. Improving tractability or makes debugging of a program easy.