Xcelium Parallel Simulator

Breaking through functional verification bottlenecks provides highest

productivity for your most complex IP and largest SoC projects

The Cadence® Xcelium™ Parallel Simulator is the third generation of digital simulation. At its core
is the first production-proven multi-core engine. Unified with that engine are the industry’s fastest
single-core, randomization, and mixed-signal engines to simulate all use cases, and supported by
second-generation simulators. Enabling these use cases are the most comprehensive set of language,
methodology, power, coverage, and functional-safety technologies. The Xcelium simulator runs on
your existing compute resources with leading runtime and capacity, making it the simulator of choice
throughout the verification flow.

Introduction The Xcelium Parallel Simulator multi-core support in the future. The
launches the third generation of Xcelium simulator automatically parti-
As system-on-chip (SoC) designs have
simulation. It provides multi-core tions the accelerate-able portions
grown in size, simulation technologies
speed-up for RTL, zero-delay gate- across multiple cores on your existing
have had to evolve dramatically to
level, and zero-delay design for server farm resources and allows you
keep pace. The first generation of
test (DFT) use cases, and single- to continue using your familiar verifi-
commercial simulation technology
core support for all other use cases cation environment, methodologies,
emerged in the late 1980s and was
currently running on second-gener- and debug without change while
marked by interpreted-code simulators
ation simulations, including the accelerating runtimes by 3X-10X on
such as Verilog-XL and RapidSim. Since
Universal Verification Methodology’s average. The Xcelium simulator is the
such simulators compiled to a form of
(UVM) testbench, low-power, mixed- simulator of choice throughout the
p-code and then interpreted that code,
signal gate simulation with Standard verification flow.
they ran rather slowly, but were suited
Delay Format (SDF) timing and more.
to the smaller designs of the time.
Many of these use cases will have
Next came compiled-code simulators
in the mid-1990s, providing the speed
and capacity for designs that quickly Three Generations of Simulation Xcelium ™

Ushering in a new ear of parallel simulation Parallel Simulator

grew larger with the emergence of
synthesis. Compiled-code simulators Use Performance
Cases and scalability
convert source code into machine code via multi-core

before running the simulation. These Complied Simulators

second-generation technologies were Example: Incisive

more complex to build, taking about Use Performance and scalability

Cases via compilers
three years to implement simulation
Interpreted Simulators
for the existing languages and use Example: Verilog-XL
models at that time. Since then, they
1990 1995 2000 2005 2010 2015 2020
have served the industry quite well,
implementing a wide range of new
standards including e, SystemC®,
SystemVerilog, CPF, and UPF. But now, Figure 1: The Xcelium simulator launches the third
designs are growing even larger and generation of simulation, unique multi-core
parallelism breaks SoC-level bottlenecks.
more complex.
 Xcelium Parallel Simulator

Key Benefits event-chains are mapped over available • Compatible with your existing
cores to run independently in parallel environments, verification method-
• Largest capacity and fastest runtime for
and scheduled to communicate with the ologies, and interactive debug
SoC-level tests
single-core engine. processes: Move between single-core
• Fast IP-level tests driven by e, and multi-core engines without code
SystemVerilog/UVM, SystemC, and This approach defines a third-generation
changes or environment restrictions
other languages engine opening the door for verification
engineers to more actively stimulate their The Xcelium simulator provides parallelism
• Seamless single-core to multi-core designs. Active stimulus creates more with multi-core speed-up, benefiting
integration events in each simulation run that is event-dense simulation runs of all types.
• Auto-partitioning of accelerate- needed to model the actual functionality
able design and non-accelerate-able in modern designs. Since third-generation Additional Parallelism
partitions simulators are able to distribute the extra
The Xcelium simulator also takes
• Multi-core parallelism regardless of activity to parallel cores, it provides both
advantage of parallelism for additional
design topology, structure, or hierarchy a speed and verification quality advantage
verification processes. These tasks can be
over second-generation simulators. In this
• Fully supports low power, performed in parallel on different cores or
way, the Xcelium simulator provides 3X to
X-propagation, and mixed signal even different machines across a network,
10X performance gains for SoC designs.
and results can be assembled post-
• Unified coverage database integrates
Performance benefits of the Xcelium process without noticeably degrading
simulation, formal, acceleration,
simulator’s multi-core parallelism include: performance.
software, fault, and use case coverage
• Simulation acceleration on average The Xcelium simulator’s tasks that
• Enables unified debug for all use cases
3X – register transfer level (RTL), 5X – can run in parallel include monolithic
including interactive and batch debug
gate-level simulation (GLS), and 10X elaboration, code generation, and two
- GLS-DFT: Expand your simulation modes of multi-snapshot incremental
capacity, and reduce hour-long RTL elaboration (MSIE), providing better
Design and Testbench
runs to minutes and multi-week DFT user control and superior performance.
runs to days Single-run auto-MSIE allows command-
xrun
• Automatic partitioning: Enables line primary and incremental partitions
multi-core, parallel build, and to be defined to gain up to 10X build
Behavioral Design multi-core speed-up for the largest SoC improvement. Multi-run MSIE allows
Elaborator Elaborator users to more directly control elaboration
designs with no learning curve
Scheduler partitioning for much greater storage and
Behavioral Direct
Multi-Core Design • Multi-core parallelism at the fine-grain
Engine Kernel runtime savings. More importantly, MSIE
Simulation design level: Multi-core speed-up
allows tighter control over re-use and
unaffected by design type, structure,
environment consistency. This ensures
Perspec
hierarchy, or process node
verification teams located across regions
Software-Driven Test
• Runtime mapping onto the industry’s and time zones are all working from the
available standard multi-core servers: same consistent primary base as they
Figure 2: The Xcelium simulator ‘s partitioning
of accelerate-able design and
Use existing X-86 servers optimize and debug their changing incre-
non-accelerate-able partitions mental DUT partitions. Each incremental
iteration needs far less memory and
High-Performance Simulation shorter runtime.

The definition of the third-generation

simulator is the combination of significant Fine-Grained Design Parallelism
speed-up and simulation automation. Complex Dependency Graph
The Xcelium simulator delivers both.
It analyzes the entire design with its
testbench, partitioning the accelerate-
able code to the multi-core engine and
non-accelerate-able code to the single- Xcelium
Algorithm
core engine. At this time, it identifies the
complex dependency maps at a fine-
grained design level. This resulting set Memory
of many millions of truly independent Xcelium Multi-Core Virtual Machine

Figure 3: The Xcelium simulator’s complex dependency graph

technology enables multi-core parallelism

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 Xcelium Parallel Simulator

Additional parallelism in the Xcelium Xcelium simulator’s native linting for power-states can be checked to compare
simulator includes: e, SystemVerilog, and RTL with testing isolation, state retention, and state loss
• Compile and elaboration partitioning features and with the Cadence Indago™ actual behavior against the expectation
–– Monolithic elaboration code Debug Analyzer, you can more fully for post synthesis and post place-and-
generation – up to 1.5X improvement develop, test, and debug to create the route implementations. Verification of
–– MSIE automated – up to 10X build most effective testbenches possible. shutoff and restore behavior can be
time and storage improvements accomplished at the design level, for the
–– MSIE multi-run – up to 20X or more, Inseparable Low-Power and logical netlist, and through to physical
creating re-useable, deployable, and Reset Verification implementation.
stable primary partitions The simulation burden has exploded with Integration with Cadence Conformal® Low
• Save and restore and dynamic restart smaller geometries requiring many tens Power and with the Cadence JasperGold®
to hundreds of power domains operating Low-Power Verification (LPV) App enables
• Debug dumping for 2X runtime and
at various different voltage levels and power intent equivalency checking, and
peak memory reduction
controlled by embedded software. Xcelium simulation allows final verification
• The Cadence Integrated Metrics Center Consistency between simulation, formal, at the SoC level to ensure the scan and
(IMC)’s individual-test coverage merge and emulation views is essential for your other physical structures inserted have not
and ranking to multiple cores with 3X verification team. altered your power intent.
on four cores observed
The Xcelium simulator’s low-power Power-up reset, initialization, and
• The Cadence vManager™ Metric-Driven simulation brings comprehensive IEEE corruption recovery are critical to
Signoff Platform’s multiple-regression 1801 (UPF) and CPF support. Cadence low-power behavior. The Xcelium simula-
coverage merge and ranking, linear pioneered using native engines to allow tor’s X-propagation support verifies
with number of cores with 4X on four all low-power information to be analyzed reset and initialization and allows you to
cores observed once during elaboration, instead of during dynamically choose the appropriate level
each simulation run, for lower overhead of pessimism or optimism for each section
Testbench Performance, and cleaner integration, meaning every on a design/level/block/instance basis
Coverage, and Debug simulation can be power aware. The same using the X-propagation tools during
Meeting your verification goals depends power intent can be carried through from simulation of VHDL and SystemVerilog.
on your testbench and verification architectural abstraction through design The Xcelium simulator’s native CPF
methodology. Regression coverage implementation and all CPF/UPF objects and UPF support work together with
metrics, interactive debug, long, deep including CPF power-modes and UPF X-propagation to verify that retention and
corner case bugs, functional safety faults,
low-power modes with initialization, and
digital interfaces with analog and mixed-
signal boundaries are essential challenges
for SoC verification.
Cadence led the development of UVM
by providing methodology and code
from OVM and building on eRM. UVM,
including the IEEE 1800.2 standard,
is supported in the Xcelium simulator
for SystemVerilog, e, and SystemC. In
addition, the Xcelium simulator supports
the emerging Accellera standard for
multi-language UVM.
But how do you recognize whether
the testbench is exercising the design
as intended? The Xcelium simulator’s
testbench coverage capability provides
metric-based reporting of testbench
activity, ensuring you know of untested
parts of your design by identifying
portions of the testbench that have not
been appropriately active. Likewise,
when a simulation fails, is it a design Figure 4: Xcelium simulator provides the Cadence IMC for concurrent dynamic analysis
or testbench issue? Combining the views. Shown here: Context-aware activity for finite state machine analysis.

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 Xcelium Parallel Simulator

isolation corruption follows power intent bugs faster. The Specman/e-based options for timing, access, and initial-
and will recover correctly from low-power Inteligen engine inspired the Xcelium ization of registers to streamline your
modes. simulator’s new Xceligen randomization gate-level timing simulation.
engine. The Xcelligen engine manages
The Xcelium simulator provides the IMC Parallelism for multi-core waveform
multiple new solvers, automatically
to measure coverage on low-power dumping, multi-snapshot incremental
choosing the most appropriate solver for
objects, power-modes, and power-states. elaboration, and save and restart reduces
the task. The Xcelium simulator’s random-
The Cadence SimVision™ Debug platform setup time and preserves stable base
ization performance is up to 5X faster
delivers waveform, schematic, and power partitions for iterative tasks, taking
than in previous simulations.
supply network browser features to your simulation back to the point of
visualize and debug all aspects of power Analyzing metrics is a critical part of any interest and allowing new scenarios to
intent. Reset and initialization verification functional verification flow. The IMC run forward. The Xcelium simulator is
using X-propagation helps fully ensure provides a single, integrated portal for integrated with the Cadence Palladium®
each power domain of the design cleanly viewing and analyzing the vast array of platforms, allowing the design to be run
recovers from power-down corruption metrics and coverage data generated at highest performance in emulation and
schemes. within the verification platform. The IMC run for debug in software simulation.
enables context-aware activity centers,
Analog Mixed-Signal and dynamic user interactivity, deep-dive SoC Verification
Digital Mixed-Signal Simulation coverage analysis, and high-performance
Ever-growing SoC verification prompted
merging and ranking to help you refine
The Xcelium simulator is integrated development of high-level verification
your regression runs. Intuitive and easy to
with the Cadence Spectre ® Circuit languages like e and SystemVerilog, along
use, the IMC greatly improves verification
Simulation Platform for analog mixed- with companion methodologies such as
productivity at every stage of the flow.
signal simulation. Users of this flow the UVM. But language and methodology
typically capture a design and testbench The results from all this advanced take you only so far.
in the Cadence Virtuoso® Analog Design technology are pulled together and either
Bugs in full-chip are few but those bugs
Environment and netlist it to run with executed or collected by the vManager
are big misses that can escape IP and
the Xcelium simulator and a Spectre platform. The vManager platform, and
subsystem regressions. Additionally, final
engine. The Xcelium simulator provides the IMC embedded within it, provides a
SoC verification requires interconnect
the xrun unified front end to compile powerful, customizable, project-level view
validation, performance profiling, and
and elaborate the netlist for simulation. of verification that is specifically tailored
physical netlist validation to ensure all IP
In this use model, the analog engines are and optimized to the Xcelium simulator,
integration and physical structures
simulating at transistor level, Verilog-AMS, bringing visibility and efficiency needed
instantiated for low power control and
or VHDL-AMS, and may include WREAL for effective verification planning and to
for scan and test have not altered your
modeling within the AMS languages for manage and accelerate coverage closure
design intent.
both power-managed and non-power- for small to multiple geography and
managed tests. distributed verification teams. In spite of great advancements in
formal, VIP, and emulation technologies,
The Xcelium simulator can also simulate functional simulation is still required for
Gate-Level Simulation
high-speed digital mixed-signal models. final SoC-level verification. The Xcelium
These models are typically written with Gate-level simulation requirements have
simulator unites tools to mix gate-level
SystemVerilog real number modeling exploded with finer process nodes,
simulation for testing interface perfor-
(RNM), Specman Elite, or VHDL. These dramatically multiplying additional cell
mance, mixed-signal and software
models provide high accuracy and support timing checks to represent more than
domains, hundreds of low-power
randomization and functional coverage, a billion gates. The Xcelium simulator’s
domains, and their initialization and
enabling digital mixed-signal simulations zero-delay and unit-delay gate-level
reset behavior. The interconnect validator
to run at digital speeds. As with multi- simulation speeds through functional
application helps quickly verify interconnect
core engines, this support allows SoC simulations to resolve race and loop
connectivity across all your IP boundaries
feature testing that can’t be done by conditions, and verify functionality. This
and the Cadence Interconnect Workbench
traditional mixed-signal approaches for reduces SDF timing gate-level simulation
accelerates performance analysis and
both power-managed and non-power- to those essential checks unavailable in
verification of on-chip interconnects
managed tests. other engines.
throughout your SoC by identifying
For gate-level simulation with back- bottlenecks under critical traffic conditions.
Coverage and Randomization annotated timing, the Xcelium simulator
Performance Multi-snapshot incremental elaboration
is optimized to run your simulations
creates stable and reuse-able primary
Randomization performance is critical faster and with less memory, using many
partitions to allow your team to focus
to achieving functional coverage in the on the portion of the design under test.
shortest number of cycles, finding more Save and restart with dynamic restart

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 Xcelium Parallel Simulator

takes your simulation back to the point of ation through emulation for software You also have the freedom to build your
interest and allows new scenarios to run application testing. The Cadence Perspec™ custom VIP testbench using any of these
forward. System Verifier automates the creation verification languages: SystemVerilog,
of software-driven real-world use-cases e, Verilog, VHDL, or C/C++. Cadence
The Xcelium simulator also provides
to address this challenge. The Perspec Simulation VIP supports UVM as well as
the capacity and performance needed
System Verifier’s development is helping other methodologies.
for your largest SoCs. The ability to
advance the Accellera portable stimulus
use Xcelium simulation and Palladium The unique and flexible architecture of
working group standard.
emulation in a flow enables high speed Cadence VIP makes all this possible. It
for reset, asynchronous, and low-power It’s becoming more common for specifica- includes a multi-language testbench
simulation with 4-state accuracy and then tions for standard interface protocols to interface with full access to the source
higher-speed 2-state accuracy for longer be hundreds of pages long. Deciphering code making it easy to integrate VIP
tests focused on system simulation, these specs and accurately modeling the with your testbench. Optimized cores for
including tests in the context of software. protocols is a big development effort simulation and simulation-acceleration
requiring deep technical knowledge. allow you to choose the verification
The Xcelium simulator is one of the best-
By using production-proven Cadence approach that best meets your objectives.
in-class engines within the Cadence
Verification IP (VIP), you can verify your
Verification Suite. Effective use of the
different engines is enabled via Cadence
SoC designs faster, more thoroughly, and Unified Plan to Closure with
verification fabric technologies supporting
with less effort. Cadence is the industry MDV
VIP leader with products supporting more
portable stimulus, a unified plan to You can use the integrated multi-window
than 40 communication protocols and 60
closure with Metric-Driven Verification GUI with the vManager platform to drive
memory interfaces.
(MDV), verification IP, and debug across the verification process right from the
the engines. planning stage. Following the guidelines
of the MDV methodology, verification
teams can automatically capture the
Verification Fabric VIP vManager ™
Indago ™
Perspec ™

verification objectives from the written

Uniform multi-engine verification VERIFICATION IP METRICS DEBUG SOFTWARE-DRIVEN TEST
verification plan, create a vPlan executable
JasperGold ®
Xcelium ™
Palladium Z1 ®
Protium S1™ specification, and automatically compare
FORMAL and STATIC SIMULATION EMULATION FPGA PROTOTYPE and communicate progress against the
NEW NEW vPlan.
Total throughput Both the Xcelium simulator and Palladium
platforms produce coverage data at the
Metric-driven signoff
end of execution by writing out coverage
Application optimized results into a unified coverage database
(UNICOV), consistent with the MDV
methodology and integrated with the
vManager platform for easy adoption. The
Figure 5: Cadence Verification Suite
vManager platform provides a powerful,
customizable, project-level view for verifi-
Multi-domain debug capabilities are cation that is specifically tailored and
required for SoC verification, including
core debug (RTL, gate-level, and
testbench), low power, mixed-signal, Plan
Web Portal,
embedded software, software-driven Regression
Dashboards,
use-case, and protocol debug. The Execution
Reports, Email
innovative SimVision and Indago debug
platforms provide differentiated solutions
for all of these debug requirements across External Data Runner / DRM
Integration Integration
the engines.
SystemVerilog and the UVM’s bottom-up
approach using constrained-random
coverage-driven testing is not sufficient Project Failure Analysis /
Tracking Confirmation
for large SoC-level verification. Real-world Multi-Engine
use cases that work are necessary for Coverage Analysis
both vertical (IP to SoC) and horizontal
cross-platform re-use, supporting the
Figure 6: The vManager platform’s advanced verification methodology control cycle
entire workflow from architectural evalu-

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 Xcelium Parallel Simulator

SoC Verification (Hardware and Software)

Formal Simulation Acceleration Emulation

RTL Verification (Hardware Only)

Figure 7: The Xcelium simulator and vManager platform take metric-driven

verification further with multi-engine MDV methodology

optimized for the Xcelium simulator. The simple and easy adaptation to traditional • Complies with IEEE 1364 Verilog, IEEE
vManager platform takes MDV beyond simulation-oriented flows, with push- 1800 SystemVerilog (including SVA),
the industry-leading IMC, to execute button automation for verification tasks IEEE 1801 UPF, IEEE 1076 VHDL, IEEE
tests across the server farm, collect test such as connectivity checking, register 1647 Specman/e, IEEE 1666 SystemC,
results, combine coverage results, and checking, and X-propagation. Coverage IEEE 1735 IP Protection,
create a verification plan, and it will do so unreachability is another fully automated • Executes full support for four-state
with the Xcelium simulator, JasperGold application deeply embedded into the logic (0, 1, X, Z) in all modes
Formal Property Verification (FPV) App, vManager platform and the Xcelium
• Supports mixed signal, low power,
and Palladium platform. The vManager simulator, making coverage closure
X-propagation, and debug across other
platform is also used to execute and faster. For teams looking for more, the
verification technologies and flows
collect results from the Xcelium Functional JasperGold FPV App with coverage allows
Safety Simulator, and with the Perspec advanced bug-hunting techniques that • Supports UVM, eRM, and OVM
System Verifier. The vManager platform nicely complement the Xcelium simulator, testbench methodologies
is a fully customizable planning and with easily combined data results to show • Supports PLI/VPI-compliant interface
management tool, which easily connects productivity levels by engine.
• Provides full debug visibility in
to your customer’s enterprise applications,
interactive and post-process use cases
and includes a commercial SQL database Features and Benefits
for tracking verification progress over • Supports standard debug tools
• Speeds up RTL, gate-level, and
time. including direct dump of waveforms
gate-level DFT functional simulations
With the vManager platform and Xcelium for higher productivity Cadence simulation has always provided
simulator, Cadence takes the MDV the most integrated unified verification
• Provides over one billion logic gate
methodology beyond traditional RTL with the widest support for standard
capacity for full SoC-level simulation
simulation-only testing. The multi-engine languages, methodologies, and flows.
• Automated multi-core partitioning With the Xcelium simulator and its third-
MDV methodology allows users to take
supports existing environment and generation multi-core parallel simulation
the best tool for the job and combine
tools for quick ramp-up your verification schedule is no longer
results transparently. The Perspec System
Verifier’s random stimulus generation runs • Runs on standard multi-core servers in at the mercy of simulation bottlenecks.
on the Xcelium simulator and Palladium existing server farms Cadence support is unexcelled as a
platform, and is used for top-down • Scales to available cores for higher partner to keep your unique verification
software-driven testing to ensure all performance project on schedule.
use cases are covered, while simultane-
• Accelerates design code on multiple
ously reading back which parts of the
cores alongside the testbench without
RTL were covered by those software
altering your environment
tests. The JasperGold FPV App is a

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 Xcelium Parallel Simulator

Specifications Cadence Services and Support

• Comprehensive language support • Functional coverage analysis • Cadence application engineers can
–– Verilog (IEEE 1364) –– Supports Verilog, SystemVerilog, answer your technical questions by
–– SystemVerilog (IEEE 1800) including VHDL, e, SystemC, SCV, PSL, SVA, telephone, email, or Internet—they can
SVA and OVL also provide technical assistance and
–– e (IEEE 1647) • Cadence SoC Functional custom training
–– VHDL (IEEE 1076) Verification Kit • Cadence-certified instructors teach
–– SystemC (IEEE 1666) more than 70 courses and bring
–– PSL (IEEE 1850) • Verification IP
–– Supports the full portfolio of their real-world experience into the
–– UPF (IEEE 1801) classroom
–– Silicon Integration Initiative (Si2) Cadence Universal Verification
Components (UVCs): PCI Express® • More than 25 Internet Learning
Common Power Format (CPF)
(PCIe®), AHB, AXI, USB, and Series (iLS) online courses allow you
–– 1735-2014 – IEEE recommended
Ethernet, PCI, SATA, and OCP the exibility of training at your own
practice for encryption of IP
–– Supports all simulation-based computer via the Internet
• Code coverage UVCs, transaction-based VIP, • Cadence Online Support gives you 24x7
–– Supports Verilog, SystemVerilog, assertion-based VIP, and Cadence online access to a knowledgebase of
VHDL, and mixed-language designs SpeedBridge® interface rate adapters the latest solutions, technical documen-
–– Automatic finite state machine used in emulation tation, software downloads, and more
extraction –– UVCs are designed to use all
–– Coverage attributes supported • For more information, please visit
elements of Cadence Incisive ®
include blocks, paths, expressions, www.cadence.com/support for support
Enterprise Simulator, featuring
variables, gates, FSM (states, and www.cadence.com/training for
a comprehensive Compliance
sequences), and toggle training
Management System that leverages
–– Coverage waiver (refinement) reuse vPlans to exhaustively verify protocol
–– Rank order coverage contributions compliance
–– Bit-wise expression scoring

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