XR22800

Hi-Speed USB to 10/100 Ethernet Bridge

FEATURES
General Description  USB 2.0 Compliant Interface
The XR22800 is a Hi-Speed USB 2.0 compound device with an embed-  10/100 Ethernet MAC and PHY
ded hub and 3 downstream USB functions: 10/100 Ethernet MAC and
 I2C Multi-master
PHY, multi-master capable I2C controller, and an Enhanced Dedicated
GPIO Entity (EDGE) controller.  Enhanced Dedicated GPIO Entity (EDGE)
 Single +5.0V Power Supply Input
The upstream USB interface has an integrated USB 2.0 PHY and device
controller that is compliant with both Hi-Speed (480Mbps) and Full-Speed  Regulated +3.3V Output Power
(12Mbps) USB 2.0. The vendor ID, product ID, power mode, remote  Single 25MHz Crystal
wakeup support and maximum power consumption are amongst the val-  ±15kV HBM ESD Protection on USB data
ues that can be programmed using the on-chip One-Time Programmable pins
(OTP) memory.  ±8kV HBM ESD Protection on all other pins
The 10/100 Ethernet MAC and PHY is compliant with IEEE 802.3 and  USB CDC-ECM and HID compliant
supports auto-negotiation, auto-MDIX, checksum offload, auto-polarity  Custom Software Drivers
correction in 10Base-T and remote wakeup capabilities.

The multi-master capable I2C controller and EDGE controller (8 GPIOs) APPLICATIONS
can be accessed via the USB HID interface. The EDGE pins or I2C inter-  USB to Ethernet Dongles
face can be used for controlling and monitoring other peripherals. Up to 2  POS Terminals
EDGE pins can be configured as a PWM generator.  Test Instrumentation
 Networking
 Factory Automation and Process Controls
 Industrial Applications

Ordering Information – Back Page

Block Diagram

10/100 Ethernet
25 MHz Ethernet
Ethernet
XO Phy
MAC

USB USB
Upstream I 2C
2.0 I2 C
USB Phy Multimaster
Hub
EDGE
EDGE
OTP Controller
Memory

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Extended Features

• USB 2.0 Compliant Interface • I2C Multi-master

• Integrated USB 2.0 PHY • Up to 400 kbps transfers
• Supports 480 Mbps USB Hi-Speed and 12 Mbps USB • Multi-master capable
Full-Speed data rate
• Enhanced Dedicated GPIO Entity (EDGE)
• Supports USB suspend, resume and remote wakeup
operations • Parallel GPIO access
• Compatible with USB CDC-ECM • Two PWM generators

• 10/100 Ethernet MAC and PHY • Custom software drivers

• Compliant with IEEE 802.3 • Windows XP, Vista, 7, 8, 8.1 and 10
• Integrated 10/100 Ethernet MAC and PHY • Windows CE 6.0
• 10BASE-T and 100BASE-TX support • Linux
• Full-duplex and half-duplex support • Mac OS X
• Full-duplex and half-duplex flow control
• Preamble generation and removal
• Automatic 32-bit CRC generation and checking
• Automatic payload padding and pad removal
• Diagnostic loop-back modes
• TCP/UDP/IP/ICMP checksum offload support
• Flexible Address filtering modes
• Wakeup packet support
• Support for 2 status LEDs

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Absolute Maximum Ratings Operating Conditions

Stresses beyond the limits listed below may cause perma- Operating Temperature Range...............................-40°C to +85°C
nent damage to the device. Exposure to any Absolute Max- VCC Supply Voltage...............................................+4.4V to +5.25V
imum Rating condition for extended periods may affect
device reliability and lifetime.
VCC Supply Voltage.............................................................+5.75V

Input Voltage
(all pins except SCL, SDA, USBD+, USBD–)..............-0.3 to +4.0V
Input Voltage (USBD+ and USBD–).......................-0.3V to +5.75V
Input Voltage (SCL and SDA)...................................-0.3V to +6.0V
Junction Temperature............................................................125°C

Electrical Characteristics
Unless otherwise noted: TA = -40°C to +85°C, VCC = 4.4V to 5.25V

Symbol Parameter Conditions Min Typ Max Units

Power Consumption

ICC Operating Current No load on GPIO pins or 3V3_OUT 185 250 mA

ISUSP Suspend Mode Current No load on GPIO pins or 3V3_OUT 3 4.5 mA

VBUS_SENSE, LOW_PWR# and EDGE Pins

VIL Input Low Voltage -0.3 0.8 V

VIH Input High Voltage 2.0 3.6 V

VOL Output Low Voltage IOL = 4mA 0.3 V

VOH Output High Voltage IOL = -4mA 2.2 V

IIL Input Low Leakage Current ±10 μA

IIH Input High Leakage Current ±10 μA

CIN Input Pin Capacitance 5 pF

USB I/O Pins

VOL Output Low Voltage Full-speed USB. External 15kΩ to GND 0 0.3 V
on USBD+ and USBD- pins

VOH Output High Voltage Full-speed USB. External 15kΩ to GND 2.8 3.6 V
on USBD+ and USBD- pins

VOL Output Low Voltage Hi-speed USB. External 45 Ω to GND on -300 300 mV
USBD+ and USBD- pins

VOH Output High Voltage Hi-speed USB. External 45 Ω to GND on 360 440 mV
USBD+ and USBD- pins

VDrvZ Driver Output Impedance 45 Ω

IOSC Output Short Circuit Current 1.5V on USBD+ and USBD- pins 52 mA

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Symbol Parameter Conditions Min Typ Max Units

Ethernet I/O Pins - 100Base-TX transmit mode

VPPH Peak Differential Output Voltage High 950 1050 mV

VPPL Peak Differential Output Voltage Low Measured at line side of transformer, line -950 -1050 mV
replaced by differential resistance of 100
VSAS Signal Amplitude Symmetry ohms. 98 102 %

TRF Signal Rise and Fall Time 3 5 ns

DCD Duty Cycle Distortion 0 0.5 ns

VOS Overshoot and Undershoot 0 5 %

- Transmit Jitter Measured differentially 0 1.4 ns

Ethernet I/O Pins - 10Base-T transmit mode

VPPH Peak Differential Output Voltage High Measured at line side of transformer, line 2.2 2.8 V
replaced by differential resistance of 100
ohms.

3.3V Regulated Power Output

VOUT Output Voltage Max load current 50 mA 3.0 3.3 3.6 V

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Pin Configuration

LOW_PWR#
GND
SDA

SCL

E3

E2

E4

E5
32

31

30

29

28

27

26

25
VBUS_SENSE 1 24 E7

REXT 2
MaxLinear 23 E6
XR22800
CAP1 3 22 GND

GND 4 21 GND

USBD- 5 20 CAP2

USBD+ 6 19 ETH_LINK

VCC 7 18 E1
CNTR_PAD
ETH_SPD 8 17 E0
10

11

12

13

14

15

16
9

XTALIN

GND

ETH_TX-

ETH_RX-
ETH_TX+

ETH_RX+
XTALOUT

3V3_OUT

Top View
Pin Assignments

Pin No. Pin Name Type Description

1 VBUS_SENSE I VBUS Sense input. In self-powered mode, the VBUS from the USB connector needs to be
connected to this pin through a voltage divider circuit (VBUS = 5V, VBUS_SENSE = 3.3V
input) using large resistance values to minimize power. It should also be decoupled by a 0.1uF
capacitor. This feature may be enabled via the OTP whenever the hub function is configured
for self-powered mode. The VBUS_SENSE input is used to disable the pull-up resistor on the
USBD+ signal when VBUS is not present. In bus-powered mode, this pin is ignored.

2 REXT I Connect externally using short trace to 226 ohm 1% resistor to ground

3 CAP1 I Connect externally to CAP2 and 3V3_OUT using short trace

4 GND PWR Power supply common, ground

5 USBD– I/O USB port differential data negative.

6 USBD+ I/O USB port differential data positive.

7 VCC PWR 5.0V power supply input

8 ETH_SPD O Ethernet 10/100 Mbps Speed Indicator. Asserted high for 100 Mbps.

9 XTALOUT O Crystal or buffered clock output.

10 XTALIN I 25 MHz +/- 50 ppm Crystal or external clock input.

11 3V3_OUT PWR 3.3 V output power. Connect externally to CAP1 and CAP2 using short trace and decouple
with minimum of 4.7uF capacitor

12 GND PWR Power supply common, ground

13 ETH_TX– O Ethernet transmit data out negative

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Pin No. Pin Name Type Description

14 ETH_TX+ O Ethernet transmit data out positive

15 ETH_RX+ I Ethernet receive data in positive

16 ETH_RX– I Ethernet receive data in negative

17 E0 I/O Enhanced general purpose IO. Defaults to input with internal pull-up resistor.

18 E1 I/O Enhanced general purpose IO. Defaults to input with internal pull-up resistor.

19 ETH_LINK O Ethernet 10/100 Activity Indicator. Toggles with activity.

20 CAP2 I Connect externally to CAP1 and 3V3_OUT using short trace

21 GND PWR Power supply common, ground

22 GND PWR Power supply common, ground

23 E6 I/O Enhanced general purpose IO. Defaults to input with internal pull-up resistor.

24 E7 I/O Enhanced general purpose IO. Defaults to input with internal pull-up resistor.

25 E5 I/O Enhanced general purpose IO. Defaults to input with internal pull-up resistor.

26 E4 I/O Enhanced general purpose IO. Defaults to input with internal pull-up resistor.

27 LOW_PWR# O The LOW_PWR# pin will be asserted whenever it is not safe to draw the amount of current
requested from VBUS in the Device Maximum Power field of the Configuration Descriptor. The
LOW_PWR# pin is asserted when the XR22800 is in suspend mode or when it is not yet con-
figured. The LOW_PWR# pin will be de-asserted whenever it is safe to draw the amount of
current requested in the Device Maximum Power field. Note that the XR22800 device is a high
power device. The default polarity of the LOW_PWR# output pin is active low and is program-
mable via the OTP.

28 GND PWR Power supply common, ground

29 E2 I/O Enhanced general purpose IO. Defaults to input with internal pull-up resistor.

30 E3 I/O Enhanced general purpose IO. Defaults to input with internal pull-up resistor.

31 SCL I/O OD I2C Master controller serial clock (open-drain) External pull-up resistor required on this pin.

32 SDA I/O OD I2C Master controller data (open-drain). External pull-up resistor required on this pin.

CNTR_PAD PWR Must be connected to ground.

Type: I = Input, O = Output, I/O = Input/Output, PWR = Power, OD = Open-Drain

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Functional Block Diagram

5.0V VCC
GND
GND ETH_LINK
GND 10/100 ETH_SPD
Ethernet ETH_TX+
Ethernet
Phy ETH_TX-
Controller ETH_RX+
USBD+ ETH_RX-
USBD-
USB 2.0 USB 2.0
VBUS_SENSE Phy Hub
I2C SDA
LOW_PWR# Multimaster SCL

E7
XTALIN 25 MHz E6
XTALOUT Xtal EDGE
E5
E4
Controller E3
E2
USB E1
OTP
Descriptors E0

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Functional Description

USB Interface
The XR22800 is a USB compound device with an embedded hub and 3 downstream USB functions. The downstream func-
tions of the XR22800 are 10/100 Ethernet, an I2C function, and an Enhanced Dedicated GPIO Entity (EDGE) function. The
upstream USB interface of the XR22800 is compliant with both USB 2.0 full and hi-speed specifications. All functions down-
stream of the hub are hi-speed functions.
The XR22800 will have a single vendor ID and vendor string. Each function in the XR22800 will have an individual product
string and serial string. The default serial number strings will be based upon the uniquely assigned Ethernet MAC address
for each XR22800 device. The serial strings for multiple functions within the same device will differ only by a single charac-
ter which will be assigned a value between 0 and 7. All string and ID values can be overridden via OTP.
The XR22800 can be placed into a low power or suspended state by the USB host. By default the XR22800 hub is config-
ured for bus powered mode with a maximum power of 250 mA. All other functions in the XR22800 are configured for self-
powered mode. In bus powered mode, the Ethernet Phy must be powered down during suspended state to meet USB sus-
pend power requirements. The Ethernet Phy may remain enabled to support Ethernet remote wakeup during suspend if the
device is self-powered and the usb OTP is modified to report the hub function as self-powered in the USB descriptors. See
Ethernet Remote Wakeup section on page 10.
Each function of the XR22800 supports one configuration and utilizes the following USB endpoints:

• USB hub
• Control endpoint
• Interrupt-in endpoint

• Ethernet function
• Control endpoint
• Interrupt-in endpoint
• Bulk-in and bulk-out endpoints

• I2C function
• Control endpoint
• Interrupt-in and interrupt-out endpoints

• EDGE Controller function

• Control endpoint
• Interrupt-in and interrupt-out endpoints

USB Vendor ID
Exar’s USB vendor ID is 0x04E2. This is the default vendor ID that is used for the XR22800. Companies may obtain their
own vendor ID, by becoming members of USB.org. The XR22800 OTP can then be modified to report this vendor ID in the
USB descriptors.

USB Product ID
Each function in the XR22800 has an individual USB product ID. The default product IDs for each of the functions are
shown in Table 1. These values can be modified by programming the OTP. Companies using their own vendor ID may also
select their own product IDs. Additionally, upon request MaxLinear will provide a selection of different product IDs for use
with Exar’s vendor ID for companies that do not wish to become members of USB.org, but wish to use their own product ID.

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Table 1: Default XR22800 Product IDs

XR22800 Function Default Product ID

Hub 0x0800

Ethernet 10/100 0x1300

I2C 0x1100

EDGE 0x1200

USB Suspend
All USB peripheral devices must support the USB suspend mode. Per USB standard, the XR22800 device will begin to
enter the suspend state if it does not detect any activity, (including Start of Frame or SOF packets) on its USB data lines for
3 ms. The peripheral device must then reduce power consumption from VBUS power within the next 7 ms to the allowed
limit of 2.5 mA per function for the suspended state. Because the XR22800 is a compound device with 4 functions, the sus-
pend state power limit is 10 mA for the device. Note that in this context, the "device" is all circuitry (including the XR22800)
that draws power from the host VBUS.
USB Strings
USB specifies three character string descriptors that are provided to the USB host during enumeration in string descriptors:
the manufacturer, product and serial strings. In a compound device such as the XR22800, each function provides these
strings to the USB host. The default manufacturer string for the XR22800 device is "Exar Corp.". The default product strings
for the hub, Ethernet function, I2C function and EDGE function are shown in Table . The serial number string is a unique
alpha-numeric ASCII string programmed into the device at the factory.

Default XR22800 Product Strings

XR22800 Function Default Product String

Hub Exar’s XR22800 Hub

Ethernet 10/100 Exar USB Ethernet

I2C Exar USB I2C

EDGE Exar USB EDGE

The OTP may be used to override these strings. However, to ensure unique serial numbers for each device, it is recom-
mended that the factory pre-programmed serial number string be used and not be overwritten via OTP.

USB Device Drivers

Each of the functions in the XR22800 require a USB device driver for operation. Both the I2C and EDGE functions conform
to the HID device class and as such, utilize the embedded HID driver that is native to each Operating System. The embed-
ded hub also uses the native hub driver. The Ethernet function conforms to the CDC device class and as such can utilize an
embedded CDC-ECM driver. However, at the time of this writing, none of the Microsoft OS provide support for CDC-ECM
embedded drivers. Both Linux and Mac OS-X platforms do support CDC-ECM drivers.
The CDC-ECM driver is a class specific driver which provides functionality for USB Ethernet devices. It operates without
any ability to access device specific register sets. In some cases, this can limit the functionality and / or throughput capabil-
ity of the XR22800. MaxLinear provides a custom Ethernet device driver which has been optimized for the best possible
data through-put in Windows platforms. Refer to 10/100 Ethernet section on page 10 for more details.

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10/100 Ethernet
The Ethernet port is a 10/100 Ethernet MAC and Phy compliant with IEEE 802.3. The Ethernet port supports speed /
duplex auto-negotiation, auto-MDIX, 10 Mbps data auto-polarity, full and half duplex data rates at 10 and 100 Mbps, gener-
ates and validates the 32-bit FCS, and performs unicast and multicast filtering. The XR22800 also performs TCP, UDP and
ICMP checksum offload over IPV4 and IPV6 as well as header checksum offload in IPV4. On chip RAM provides all
required packet buffering.
In Windows OS, using the MaxLinear custom Ethernet driver, the properties dialog, advanced properties can be used to set
the pause frame flow control, speed and duplex, auto-negotiation, checksum offload, and Ethernet remote wakeup settings.
By default, the Ethernet MAC will honor incoming pause frames sent by a peer Ethernet device, but will not generate pause
frames. Auto-MDIX is always enabled.

Ethernet Remote Wakeup

If the XR22800 hub is configured as a self-powered device and has Ethernet remote wakeup enabled, the XR22800 will
request the USB host to resume in response to a magic packet or a link state change on the Ethernet port. When the USB
host is suspended, the Ethernet Phy remains active and the XR22800 is able to both meet USB suspend mode power
requirements as well as respond to magic packet and link state changes.

The magic packet is an Ethernet packet with specific content, i.e. 6 bytes of 0xFF, followed by 16 repetitions of the target
MAC address (MAC address of the XR22800 device). This content can occur anywhere in the incoming packet payload.
The link state change will wake the USB host if the link is down when the USB host is suspended and then the link goes up,
or if the link is up when the USB host is suspended and then the link goes down.

EDGE - Enhanced Dedicated GPIO Entity

The XR22800 has 8 EDGE IO pins The EDGE controller allows for GPIO signals to be individually set or cleared or to be
grouped, such that the all pins in the group can be simultaneously accessed for reads or writes. Note that on write
accesses, output pins will change in 4-bit subgroups on core clock (60 MHz) boundaries. For example, if an 8 bit data group
is defined and the data value is written from 0x00 to 0xFF, 4 bits would change from ’0’ to ’1’ followed by the next 4 bits one
clock cycle (~ 17 ns) later.
EDGE IOs can be configured as inputs or outputs. Outputs can be configured as push-pull or open drain and can be tri-
stated. Inputs can be configured to generate interrupts to the USB host on either negative or postive edge transitions.
Another feature of the EDGE controller is that up to 2 GPIO pins within the EDGE can be assigned to pulse width modu-
lated (PWM) outputs. Each of the PWM outputs can be used to generate an output clock or pulse of varying duty cycle.
Both low and high cycles can be configured in steps of 267 ns up to 1.092 ms. The output can be controlled to generate a
single "one-shot" pulse or to free run. Refer to the EDGE_PWM0_CTRL and EDGE_PWM1_CTRL registers on page 22
and page 24 for control of PWM outputs.

I2C

The XR22800 implements an I2C multi-master using the control endpoint of the full-speed USB function to transfer data to
and from the I2C interface. The I2C master supports both standard (100 kbps) and fast (400 kbps) modes and supports mul-
tiple master configurations to allow other devices to access slave devices on the I2C. The I2C function is an HID function
and uses the native HID driver. It supports both 7 and 10 bit addressing modes.

Regulated 3.3V Power Output

The XR22800 internal voltage regulator provides 3.3 VDC output power which can be utilized by other circuitry. Refer to
Electrical Characteristics” on page 3 for maximum power capability. For bus powered devices, significant utilization of the
3V3 output power may require increasing the maximum power request above the 250 mA default value from the USB host
by programming the OTP.

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OTP
The OTP is an on-chip non-volatile memory, that is one-time programmable via the USB interface. Bit locations within the
memory may be programmed at various times allowing for customization of the XR22800. Some bits are pre-programmed
at the factory and caution must be taken not to program any locations except user defined addresses. Contact the factory
for information and assistance in programming the XR22800 OTP.

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USB Control Commands

The following table shows all of the USB Control Commands that are supported by the XR22800. Commands include stan-
dard USB commands and USB vendor specific MaxLinear commands.

Value Index Length

Request
Name Request Description
Type
LSB MSB LSB MSB LSB MSB

USB Standard Requests

DEV GET_STATUS 0x80 0x0 0x0 0x0 0x0 0x0 0x2 0x0 Device: remote wake-up +
self-powered

IF GET_STATUS 0x81 0x0 0x0 0x0 0x0 0x0 0x2 0x0 Interface: zero

EP GET_STATUS 0x82 0x0 0x0 0x0 0x0, 0x0 0x2 0x0 Endpoint: halted
0x4,
0x84

DEV CLEAR_FEATURE 0x00 0x1 0x1 0x0 0x0 0x0 0x0 0x0 Device remote wake-up

EP CLEAR_FEATURE 0x02 0x1 0x0 0x0 0x0, 0x0 0x0 0x0 Endpoint halt
0x4,
0x84

DEV SET_FEATURE 0x00 0x3 0x1 0x0 0x0 0x0 0x0 0x0 Device remote wake-up

EP SET_FEATURE 0x02 0x3 0x0 0x0 0x0, 0x0 0x0 0x0 Endpoint halt
0x4,
0x84

SET_ADDRESS 0x00 0x5 addr 0x0 0x0 0x0 0x0 0x0 addr = 1 to 127

GET_DESCRIPTOR 0x80 0x6 0x0 0x1 0x0 0x0 len len Device descriptor
MSB MSB

GET_DESCRIPTOR 0x80 0x6 0x0 0x2 LangID LangID len len Configuration descriptor
MSB MSB

GET_DESCRIPTOR 0x80 0x6 0x0 0x3 0x0 0x0 len len String descriptor
MSB MSB

GET_CONFIGURATION 0x80 0x8 0x0 0x0 0x0 0x0 0x1 0x0

SET_CONFIGURATION 0x00 0x9 n 0x0 0x0 0x0 0x0 0x0 n = 0, 1

USB Class Specific Requests

CDC_ECM_IF_ 0x21 0x40 Num- Num- 0x0 0x0 N*6 N*6

SET_ETH_MCAST_FIL- ber ber LSB MSB
TERS (N) of (N) of
filters filters
LSB MSB

CDC_ECM_IF_ 0x21 0x43 *Bit- *Bit- 0x0 0x0 0x0 0x0 See Bitmap definition in
SET_ETH_PACKET_- map map note 1 below
FILTERS LSB MSB

CDC_ECM_IF_ 0xA1 0x44 Selec 0x0 0x0 0x0 0x4 0x0 See Selector definition in
GET_ETH_STATISTIC tor note 2 below

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Value Index Length

Request
Name Request Description
Type
LSB MSB LSB MSB LSB MSB

USB Vendor Specific Requests

XR_GET_CHIP_ID 0xC0 0xFF 0x0 0x0 0x0 0x0 0x6 0x0 Get Exar VID (2 bytes),
PID (2 bytes) and bcdDe-
vice (2 bytes)

Note 1: SET_ETH_PACKET_FILTERS Bitmap definition:

D15..D5: reserved
D4: MULTICAST If 1, packets with multicast addresses set by SetEthernetMulticastFilter are forwarded to the host. 0 = Disabled.
D3: BROADCAST If 1, broadcast packets are forwarded to the host. 0 = Disabled.
D2: DIRECTED If 1, unicast packets with a matching address are forwarded to the host. 0 = Disabled.
D1: ALL_MULTICAST If 1, all multicast packets are forwarded to the host. 0 = Disabled.
D0: PROMISCUOUS If 1, all packets are forwarded to the host, regardless of address. 0 = Disbled.
Note 2: SET_ETH_PACKET_FILTERS Selector definition:
0x01 = XMIT_OK
0x02 = RCV_OK
0x03 = XMIT_ERROR
0x04 = RCV_ERROR
0x05 = RCV_NO_BUFFER
0x0d = DIRECTED_FRAME_RCV
0x0f = MULTICAST_FRAME_RCV
0x11 = BROADCAST_FRAME_RCV
0x12 = RCV_CRC_ERROR
0x13 = XMIT_QUEUE_LENGTH
0x14 = RCV_ERR_ALIGNMENT
0x19 = RCV_OVERRUN

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HID Reports
The I2C and EDGE functions in the XR22800 are HID functions. I2C data may be read or written to / from the slave device
using the interrupt in and interrupt out endpoints via HID input and output reports. Additionally, XR22800 device register
access using the control endpoint for both I2C and EDGE functions is performed via HID feature reports. Reading uses indi-
rect addressing such that for register reads, the register address must first be written and the register value may then be
read. Both types of reports are described below.

Input and Output Reports

Input and output reports using the interrupt in and interrupt out endpoints follow the following format.

I2C_SLAVE_OUT
Transfer Type: Interrupt Out
Transfer Size: 37 bytes
The I2C_SLAVE_OUT report writes and / or reads up to 32 bytes of data on the I2C interface. Note that all interrupt out
transfers will be automatically followed by an interrupt in transfer. For write only transfers, the interrupt in packet will contain
the status of the interrupt out transfer. For read only or write and read transfers, the interrupt in packet will contain the read
data, as well as the status of the interrupt out transfer. The format of the interrupt out packet is given below.

Field Offset Size Value Description

Report ID 0 1 0x00 Write, read, or write and read I2C data

Flags 1 1 Bitmap Transfer options

D0: Prefix transfer with a start bit.
D1: Append a stop bit to the transfer.
D2: ACK last read to extend a read transfer (e.g. if more than 32 bytes
need to be read).
The default is to NAK the last read in the transfer. This bit has no effect
if RdSize is 0.
D3: Reserved
D7..D4: Sequence number. This can help the host to correlate an IN
response with a prior OUT command. This field is optional.

WrSize 2 1 Number Number of data bytes to write. Valid values are 0 to 32. The 7-bit slave
address should not be included in this total.

RdSize 3 1 Number Number of bytes to read. Valid values are 0 to 32.

SlaveAddr 4 1 Number The 7-bit slave address* to send. The XR22800 will automatically set
the I2 C read/write bit, so bit D0 of this field is ignored.

Data 5 32 Data Data to be written to the slave. HID uses a fixed report size for each
specific report ID so this field will always be 32 bytes long. However,
only the number of bytes specified in WrSize will be written. Other bytes
will be ignored.

* Note: To support 10-bit addressing the standard 7-bit address must be set to 1111 0xxB where xx are the most significant bits of the 10-
bit address. All 4 of these 7-bit addresses are reserved and will not be used by any slaves with 7-bit only addresses. The least significant
bit of the address byte still specifies the direction. For writes, the first data byte which was previously unformatted is now reserved for the
least significant 8 bits of the 10-bit address. Additional data bytes remain unformatted. For reads, the write-then-read combined transfer
format is always used. During the write portion of the combined transfer the master must send at least one data byte which contains the
least significant 8 bits of the 10-bit address. After all of the write data is sent the master then sends a restart bit. This is followed with an
address byte which has the same 7-bit address 1111 0xxB as in the write portion. However, the direction bit is now 1 for reading. The slave
then sends the read data as usual. The least significant 8 bits of the 10-bit address are not sent again after the restart bit.

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I2C_SLAVE_IN
Transfer Type: Interrupt In
Transfer Size: 36 bytes
Interrupt in packet status only, or status and read data from the I2C interface.

Field Offset Size Value Description

Flags 0 1 Bitmap Status of the requested transfer.

D0: Request Error. If 1, the OUT request had an error (e.g. invalid size)
and was not executed.
D1: A byte sent to a slave received an I2C NAK response. The transfer
was aborted.
D2: Arbitration was lost. The transfer was aborted.
D3: Timeout. Bus free condition was not observed within 256 ms or an
individual byte transfer extended longer than 10ms.
D7..D4: Sequence number. This number matches the value provided in
the corresponding OUT command packet.

WrSize 1 1 Number Number of bytes written, 0 to 32.

RdSize 2 1 Number Number of bytes read, 0 to 32.

Reserved 3 1 Number This field is reserved.

Data 4 32 Data The read data that was received from the slave. HID uses a fixed report
size for each specific report ID, so this field will always be 32 bytes long.
However, only the number of bytes specified in RdSize are valid. Other
bytes should be ignored.

Feature Reports
Access to XR22800 registers via HID feature reports along with the register descriptions are given in the following sections.
WRITE_HID_REGISTER
Transfer Type: Control
Transfer Size: 5 bytes
The WRITE_HID_REGISTER report writes 2 bytes of data to the specified register address.

Field Offset Size Value Description

Report ID 0 1 0x3C Write HID register

Write Address LSB 1 1 Write address

Write Address MSB 2 1

Write Data LSB 3 1 Write data

Write Data MSB 4 1

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SET_HID_READ_ADDRESS
Transfer Type: Control
Transfer Size: 3 bytes
The SET_HID_READ_ADDRESS report sets the address for the READ_HID_REGISTER report.

Field Offset Size Value Description

Report ID 0 1 0x4B Set address for HID register read

Read Address LSB 1 1 Read address

Read Address MSB 2 1

READ_HID_REGISTER
Transfer Type: Control
Transfer Size: 3 bytes
The READ_HID_REGISTER report reads register data from the address set by the SET_HID_READ_ADDRESS report.

Field Offset Size Value Description

Report ID 0 1 0x5A Read HID register

Read Data LSB 1 1 Read data

Read Data MSB 2 1

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HID Register Map

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Address Register Name
(15) (14) (13) (12) (11) (10) (9) (8)

I2C Registers

I2C_SCL_LOW MSB [15:8] VALUE (MSB)

0x341
I2C_SCL_LOW LSB [7:0] VALUE (LSB)

I2C_SCL_HIGH MSB [15:8] VALUE (MSB)

0x342
I2C_SCL_HIGH LSB [7:0] VALUE (LSB)

EDGE Registers

0x3C1 EDGE_DIR E7 E6 E5 E4 E3 E2 E1 E0

0x3C2 EDGE_SET E7 E6 E5 E4 E3 E2 E1 E0

0x3C3 EDGE_CLEAR E7 E6 E5 E4 E3 E2 E1 E0

0x3C4 EDGE_STATE E7 E6 E5 E4 E3 E2 E1 E0

0x3C5 EDGE_TRI_STATE E7 E6 E5 E4 E3 E2 E1 E0

0x3C6 EDGE_OPEN_DRAIN E7 E6 E5 E4 E3 E2 E1 E0

0x3C7 EDGE_PULL_UP E7 E6 E5 E4 E3 E2 E1 E0

0x3C8 EDGE_PULL_DOWN E7 E6 E5 E4 E3 E2 E1 E0

0x3C9 EDGE_INTR_MASK E7 E6 E5 E4 E3 E2 E1 E0

EDGE_INTR_POS_
0x3CA E7 E6 E5 E4 E3 E2 E1 E0
EDGE

EDGE_PWM0_CTRL MSB
0 0 0 0 0 0 0 CMD[2]
[15:8]
0x3D8
EDGE_PWM0_CTRL LSB
CMD[1:0] EN 0 0 PIN
[7:0]

EDGE_PWM0_HIGH MSB
0 0 0 0 VALUE[11:8]
[15:8]
0x3D9
EDGE_PWM0_HIGH LSB
VALUE [7:0]
[7:0]

EDGE_PWM0_LOW MSB
0 0 0 0 VALUE[11:8]
[15:8]
0x3DA
EDGE_PWM0_LOW LSB
VALUE [7:0]
[7:0]

EDGE_PWM1_CTRL MSB
0 0 0 0 0 0 0 CMD[2]
[15:8]
0x3DB
EDGE_PWM1_CTRL
CMD[1:0] EN 0 0 PIN
LSB [7:0]

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Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Address Register Name
(15) (14) (13) (12) (11) (10) (9) (8)

EDGE_PWM1_HIGH MSB
0 0 0 0 VALUE[11:8]
[15:8]
0x3DC
EDGE_PWM1_HIGH LSB
VALUE [7:0]
[7:0]

EDGE_PWM1_LOW MSB
0 0 0 0 VALUE[11:8]
[15:8]
0x3DD
EDGE_PWM1_LOW LSB
VALUE [7:0]
[7:0]

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HID Register Descriptions

Note that all register reset default values are ’0’ unless otherwise specified. All registers are 16 bits.
I2C_SCL_LOW (0x341) - Read/Write

Bit Default Description

15:0 0x0144 Value

Specifies the number of periods that SCL will be asserted low by the XR22800 I2C master. Note that in clock
stretching, the I2C slave may extend the SCL low period to delay the next transaction. For 100 kbps transfer
rate this value must be at least 252 (0x00FC) and the sum of high and low periods must be at least 600
(0x0258). For 400kbps transfer rate this value must be at least 78 (0x004E) and the sum of the high and low
periods must be at least 150 (0x0096). Measured in 60 MHz core clock periods, i.e. approximately 16.7 ns.

I2C_SCL_HIGH (0x342) - Read/Write

Bit Default Description

15:0 0x0114 Value

Specifies the number of periods that SCL will be asserted high by the XR22800 I2C master. Note that another
multi-master may assert SCL low before the XR22800 high period is completed. For 100 kbps transfer rate this
value must be at least 240 (0x00F0) and the sum of the high and low periods must be at least 600 (0x0258).
For 400 kbps transfer rate this value must be at least 36 (0x0024) and the sum of the high and low periods must
be at least 150 (0x0096). Measured in 60 MHz core clock periods, i.e. approximately 16.7 ns

EDGE_DIR (0x3C1) - Read/Write

Note that when setting direction of an EDGE IO to output, the EDGE_PULL_UP for that IO pin should also be disabled and
when setting an EDGE IO pin to input, the EDGE_PULL_UP for that IO pin should also be enabled.

Bit Default Description

15:8 0x00 Reserved

These bits are reserved and should be written as ‘0’.

7:0 0x00 E[7:0]

0: IO pin assigned to EDGE function is configured as an input
1: IO pin assigned to EDGE function is configured as an output.

EDGE_SET (0x3C2) - Write Only

Bit Default Description

15:8 0x00 Reserved

These bits are reserved and should be written as ‘0’.

7:0 0x00 E[7:0]

0: No effect
1: Set IO pin assigned to EDGE function and configured as an output to a logic ‘1’

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EDGE_CLEAR (0x3C3) - Write Only

Bit Default Description

15:8 0x00 Reserved

These bits are reserved and should be written as ‘0’.

7:0 0x00 E[7:0]

0: No effect
1: Clear IO pin assigned to EDGE function and configured as an output to a logic ‘0’

EDGE_STATE (0x3C4) - Read/Write

Bit Default Description

15:8 0xFF Reserved

These bits are reserved and should be written as ‘1’.

7:0 0x00 E[7:0]

Writing in this register sets or clears the EDGE IO pin(s) configured as an output. Writing to an EDGE pin con-
figured as an input has no effect. Reading this register returns the state of each IO pin configured as an EDGE
pin irrespective of whether it is configured as an input or output. Note that output transitions across multiple IO
pins may be slightly staggered. Refer to page 10.

0: Write clears the corresponding bit to a ‘0’. Read returns the current state.
1: Write sets the corresponding bit to a ‘1’. Read returns the current state.

EDGE_TRI_STATE (0x3C5) - Read/Write

Bit Default Description

15:8 0x00 Reserved

These bits are reserved and should be written as ‘0’.

7:0 0x00 E[7:0]

0: IO pin assigned to EDGE function and configured as an output is actively driven
1: IO pin assigned to EDGE function and configured as an output is tri-stated

EDGE_OPEN_DRAIN (0x3C6) - Read/Write

Bit Default Description

15:8 0x00 Reserved

These bits are reserved and should be written as ‘0’.

7:0 0x00 E[7:0]

Note that XR22800 open drain outputs have a weak internal pull-up.

0: IO pin assigned to EDGE function and configured as an output is a push-pull output

1: IO pin assigned to EDGE function and configured as an output is an open drain output

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EDGE_PULL_UP (0x3C7) - Read/Write

Bit Default Description

15:8 0xFF Reserved

These bits are reserved and should be written as ‘1’.

7:0 0xFF E[7:0]

0: Disable internal pull-up resistor on IO pin assigned to EDGE function and configured as an input
1: Enable internal pull-up resistor on IO pin assigned to EDGE function and configured as an input

EDGE_PULL_DOWN (0x3C8) - Read/Write

Bit Default Description

15:8 0x00 Reserved

These bits are reserved and should be written as ‘0’.

7:0 0x00 E[7:0]

0: Disable internal pull-down resistor on IO pin assigned to EDGE function and configured as an input
1: Enable internal pull-down resistor on IO pin assigned to EDGE function and configured as an input

EDGE_INTR_MASK (0x3C9) - Read/Write

Bit Default Description

15:8 0x00 Reserved

These bits are reserved and should be written as ‘0’.

7:0 0x00 E[7:0]

Writing a ’1’ in this register enables an input pin for the corresponding bit position EDGE IO pin(s) configured as
an input to generate an interrupt if either EDGE_INTR_POS_EDGE and / or EDGE _INTR_NEG_EDGE regis-
ters has also been enabled. An EDGE pin configured as an output has no effect.

0: IO pin will not generate an interrupt

1: IO pin assigned to EDGE function and configured as an input will generate an interrupt

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EDGE_INTR_POS_EDGE (0x3CA) - Read/Write

Bit Default Description

15:8 0xFF Reserved

These bits are reserved and should be written as ‘1’.

7:0 0xFF E[7:0]

Writing a ’1’ in this register enables an interrupt to be generated on the rising edge of the corresponding bit posi-
tion EDGE IO pin(s) configured as an input if the EDGE_INTR_MASK register is enabled for that pin. If the
EDGE_INTR_NEG_EDGE register is also enabled, interrupts will be generated on both edges. Writing to an
EDGE pin configured as an output has no effect.

0: IO pin will not generate an interrupt on rising edge

1: IO pin assigned to EDGE function and configured as an input will generate an interrupt on rising edge if cor-
responding EDGE_INTR_MASK bit is set

EDGE_INTR_NEG_EDGE (0x3CB) - Read/Write

Bit Default Description

15:8 0xFF Reserved

These bits are reserved and should be written as ‘1’.

7:0 0xFF E[7:0]

Writing a ’1’ in this register enables an interrupt to be generated on the falling edge of the corresponding bit
position EDGE IO pin(s) configured as an input if the EDGE_INTR_MASK register is enabled for that pin. If the
EDGE_INTR_POS_EDGE register is also enabled, interrupts will be generated on both edges. Writing to an
EDGE pin configured as an output has no effect.

0: IO pin will not generate an interrupt on falling edge

1: IO pin assigned to EDGE function and configured as an input will generate an interrupt on falling edge if cor-
responding EDGE_INTR_MASK bit is set

EDGE_PWM0_CTRL (0x3D8) - Read/Write

Bit Default Description

15:9 0x00 Reserved

These bits are reserved and should be written as ‘0’.

8:6 0x0 Cmd

000: Idle. output pin remains at same state
001: Undefined, do not use
010: Undefined, do not use
011: Undefined, do not use
100: Assert logic ‘0’
101: One-shot -If previous state was assert ’0’, one-shot pulse will be high, If previous state was assert ’1’, one-
shot pulse will be low
110: Free run output
111: Assert logic ‘0’

5 0 Enable
0: PWM0 output is not enabled
1: PWM0 output is enabled on pin specified in Pin field using mode specified in Cmd field

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Bit Default Description

4:3 0x0 Reserved

These bits are reserved and should be written as ‘0’.

2:0 0x0 Pin

Specifies which pin (E7 - E0) will be assigned to PWM0 output.

EDGE_PWM0_HIGH (0x3D9) - Read/Write

Bit Default Description

15:12 0x0 Reserved

These bits are reserved and should be written as ‘0’.

11:0 0x001 Value

This register specifies the high period for PWM0 in increments of 266.667ns. High period must be in the range
of 1 to 4095 (266.667 ns to 1.092 ms)

EDGE_PWM0_LOW (0x3DA) - Read/Write

Bit Default Description

15:12 0x0 Reserved

These bits are reserved and should be written as ‘0’.

11:0 001 Value

This register specifies the low period for PWM0 in increments of 266.667ns. Low period must be in the range of
1 to 4095 (266.667 ns to 1.092 ms)

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EDGE_PWM1_CTRL (0x3DB) - Read/Write

Bit Default Description

15:9 0x00 Reserved

These bits are reserved and should be written as ‘0’.

8:6 0x0 Cmd

000: Idle. output pin remains at same state
001: Undefined, do not use
010: Undefined, do not use
011: Undefined, do not use
100: Assert logic ‘0’
101: One-shot -If previous state was assert ’0’, one-shot pulse will be high, If previous state was assert ’1’, one-
shot pulse will be low
110: Free run output
111: Assert logic ‘0’

5 0 Enable
0: PWM1 output is not enabled
1: PWM1 output is enabled on pin specified in Pin field using mode specified in Cmd field

4:3 0x0 Reserved

These bits are reserved and should be written as ‘0’.

2:0 0x0 Pin

Specifies which pin (E7 - E0) will be assigned to PWM1 output.

EDGE_PWM1_HIGH (0x3DC) - Read/Write

Bit Default Description

15:12 0x0 Reserved

These bits are reserved and should be written as ‘0’.

11:0 0x001 Value

This register specifies the high period for PWM1 in increments of 266.667ns. High period must be in the range
of 1 to 4095 (266.667 ns to 1.092 ms)

EDGE_PWM1_LOW (0x3DD) - Read/Write

Bit Default Description

15:12 0x0 Reserved

These bits are reserved and should be written as ‘0’.

11:0 0x001 Value

This register specifies the low period for PWM1 in increments of 266.667ns. Low period must be in the range of
1 to 4095 (266.667 ns to 1.092 ms)

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Mechanical Dimensions
32-Pin QFN

Top View Bottom View

Side View

Drawing No: POD-00000037

Revision: B

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 XR22800

Drawing No: POD-00000037

Revision: B

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 XR22800

Ordering Information(1)

Part Number Operating Temperature Range Lead-Free Package Packaging Method

XR22800IL32-F Tray
-40°C to +85°C Yes(2) 32-pin QFN
XR22800IL32TR-F Reel

XR22800IL32-0A-EB XR22800 Evaluation Board

NOTE:

1. Refer to www.maxlinear.com/XR22800 for most up-to-date Ordering Information.

2. Visit www.maxlinear.com for additional information on Environmental Rating.

Revision History

Revision Date Description

1A July 2014 Initial Release

1B April 2015 Clarified pin definitions for VBUS_SENSE, ETH_SPD and ETH_LINK pins. Added USB CDC-ECM class spe-
cific requests to USB commands table. Added descriptions of feature and input and output reports for HID
functions. Added HID register access feature reports. [ECN 1518‐01 Apr 28 2015]

1C April 2016 Updated package diagrams. [ECN 1616‐05 Apr 15 2016]

1D December 2017 Update to MaxLinear logo. Update format and ordering information table. Renamed center pad and added to
Pin Assignments. Added defaults to E0-E7 pins. Updated custom software drivers on page 2. Changed stan-
dard driver to class specific driver in USB Device Drivers section.

1E March 2019 Updated I2C_SLAVE_IN register table. Updated Ordering Information.

1F September 2019 Re-colored headers on page 10, 14 and 15 for consistency.

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