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Multi Matrix Processor For Cyberspace Analysis

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Multi Matrix Processor For Cyberspace Analysis

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Multimatrix Processor for Cyberspace Analysis

Conference Paper · February 2012

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4 authors, including:

Vladimir Hahanov Svetlana Chumachenko


Kharkiv National University of Radio Electronics Kharkiv National University of Radio Electronics
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University of Baghdad
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243

Multimatrix Processor for Cyberspace Analysis


Vladimir Hahanov, Svetlana Chumachenko, Baghdad Ammar Avni Abbas, M. Maksimov

Abstract – The structural model of high-speed multimatrix implemented built-in instruction that allows realizing a
processor designed for fast and accurate search of information primitive control system for parallel computing processes
objects in cyberspace is described is proposed. It enables to (SIMD – Single Instruction Multiple Data), which is
increase considerably (x10) the speed of diagnosing single and/or
multiple faults. sequential in nature, and therefore there is no need to create a
Keywords – testing, verification, HDL-model, Infrastructure super complex compilers, focused on parallelization of
IP. computational processes. Here, each matrix processor
executes a single operation, built-in storage elements of the
1. INTRODUCTION matrix. But there are situations, when the matrix level (M-
Purpose of this article is creation of the individual and level) of data definition is redundant to perform operations on
virtual computer in cyberspace for intelligence transactions of Boolean (B-level) or registration (R-level) variables. For such
data and services, focused on each person [1]. The problems case, it is necessary to have the hierarchy of data levels. The
are: 1) Defining the functional infrastructure for virtual PCC. typical MMP blocks are: memory for data (DM) and programs
2) Creating a structured database for storing information and (PM), control unit (CU), interface (I-face) and Infrastructure
services. 3) Developing a PCC template as a set of related IP (I-IP), as well as multimatrix processor module, which
services and tools focused to the needs of the user. 4)
includes 4 memory blocks with built-in operations (A – and, B
Developing a system for protection of personal cyberspace,
– xor, C – or, D – slc – shift left crowding) and buffer
data and services, including authentication, keys, digital
signature, cryptography. 5) Creating intelligent tools for memory M.
searching, pattern recognition and decision making as a set of The applications of vector-logic or matrix technology for
filters, focused to a specific user. 6) Developing PCC analyzing the processes or phenomena: 1) text recognition in
prototype and its testing for different kinds of users. the entry registration cards; 2) personal identification by
photographs, close to the standard images for visa documents;
II. ENGINE FOR CYBERSPACE ANALYSIS
3) search of analogs in the Internet by the given patterns; 4)
For high-speed navigation in cyberspace (searching objects sorting images in the database according to the classes and
and evaluating their interaction) it is needed a simple and fast attributes; 5) fingerprinting and creation of classified
multimatrix processor (MMP), where each operation (and, or, intelligence library; 6) recognition and classification of software
xor, slc) processes in parallel and very fast only one binary
viruses; 7) identification of targets and moving objects (aircraft,
operation on the matrices (two-dimensional data arrays). The
ships, cars); 8) control robotic systems; 9) pattern recognition for
number of instruction-oriented primitive matrices creates a
smell, taste, sound, heat and radio frequency; 10) recognition of
system – heterogeneous multimatrix processor of binary
operations with the buffer M, Fig. 1. Multimatrix processor linguistic structures and primitives, and their estimation when
module involves 4 comparing with benchmarks.
memory blocks with III. CONCLUSION
built-in instructions (A –
and, B – xor, C – slc – The architecture of multimatrix processor, focused to
shift left crowding, D – improve the performance of decision-making in the library
or) and buffer memory space, is proposed. It is characterized by using parallel logic
M. The module is vector operations and, or, xor, slc, which makes it possible to
focused on the parallel improve significantly (x10) the performance of functionality
execution in this case synthesis. The model for synthesizing functionality of a digital
Fig 1. Multimatrix processor one of four instructions system in the form of multitree and method of traversal the
of binary operations (ISA – Instruction Set tree nodes, implemented in the engine to search a solution of
Architecture) by using given depth, which greatly increases the performance of
matrices of binary data of the same dimension
software and hardware design, are presented.
M = M {and, or, xor, slc}{A, B, C, D} and saves the result in
the buffer M. MMP feature that is not the matrix cell has the REFERENCES
command system of the four instructions, and each instruction [1] M.F. Bondaryenko, O.A. Guz, V.I. Hahanov, Yu.P.
has its own cell matrix as the data for parallel processing,
Shabanov-Kushnaryenko, “Infrastructure for brain-like
which significantly simplifies the control structure and the
computing,” Kharkov: Novoye Slovo, 160 p., 2010.
whole device. The MMP complexity is moved on the data
structure, where the matrix memory has a single hardware-

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