Behavioral Modeling

Structured Procedures
• There are two structured procedure statements in Verilog: always and initial.
• Each always and initial statement represents a separate activity flow in Verilog. Each activity
flow starts at simulation time 0.

Initial Statement
All statements inside an initial statement constitute an initial block.
An initial block starts at time 0, executes exactly once during a simulation, and then does not
execute again

module stimulus;
reg x,y, a,b, m;
initial
m = 1'b0; //single statement; does not need to be grouped
initial
begin
#5 a = 1'b1; //multiple statements; need to be grouped
#25 b = 1'b0;
end
initial
begin
#10 x = 1'b0;
#25 y = 1'b1;
end

initial
#50 $finish;

Endmodule

• The execution sequence of the statements inside the initial blocks will be as follows

• time statement executed

• 0 m = 1'b0;
• 5 a = 1'b1;
• 10 x = 1'b0;
• 30 b = 1'b0;
• 35 y = 1'b1;
• 50 $finish;
 Combined Variable Declaration and Initialization

• Variables can be initialized when they are declared

Example : Initial Value Assignment

//The clock variable is defined first

reg clock;
//The value of clock is set to 0
initial
clock = 0;

//Instead of the above method, clock variable

//can be initialized at the time of declaration
//This is allowed only for variables declared
//at module level.
reg clock = 0;
Example - Combined Port/Data Declaration and Variable Initializatio

module adder (sum, co, a, b, ci);

output reg [7:0] sum = 0; //Initialize 8 bit output sum
output reg co = 0; //Initialize 1 bit output co
input [7:0] a, b;
Input ci;
--
--
endmodule

Example - Combined ANSI C Port Declaration and Variable Initialization

module adder (output reg [7:0] sum = 0, output reg co

= 0, input [7:0] a, b,Input ci);
--
--
endmodule
 always Statement
• All behavioral statements inside an always statement constitute an always block.
• The always statement starts at time 0 and executes the statements in the always
block continuously in a looping fashion
Example -always Statement

module clock_gen (output reg clock);

//Initialize clock at time zero
initial
clock = 1'b0;
//Toggle clock every half-cycle (time period = 20)
always
#10 clock = ~clock;
initial
#1000 $finish;

endmodule
 Procedural Assignments
• Procedural assignments update values of reg, integer, real, or time variables.
• The value placed on a variable will remain unchanged until another procedural
assignment updates the variable with a different value

Variable_lvalue = [delay or event_control] expression

• The left-hand side of a procedural assignment <lvalue> can be one of the

following:

• A reg, integer, real, or time register variable or a memory element

• A bit select of these variables (e.g., addr[0])
• A part select of these variables (e.g., addr[31:16])
• A concatenation of any of the above

• The right-hand side can be any expression that evaluates to a value

• There are two types of procedural assignment statements: blocking and
nonblocking.
 Blocking Assignments

• Blocking assignment statements are executed in the order they are specified in a
sequential block
• The = operator is used to specify blocking assignments.
• Example -Blocking Statements
reg x, y, z;
reg [15:0] reg_a, reg_b;
integer count;
//All behavioral statements must be inside an initial or always block
initial
begin
x = 0; y = 1; z = 1; //Scalar assignments
count = 0; //Assignment to integer variables
reg_a = 16'b0; reg_b = reg_a; //initialize vectors
#15 reg_a[2] = 1'b1; //Bit select assignment with delay
#10 reg_b[15:13] = {x, y, z} //Assign result of
concatenation to part select of a vecto
count = count + 1; //Assignment to an integer
(increment)
end
 Nonblocking Assignments

• Nonblocking assignments allow scheduling of assignments without blocking execution of the statements
that follow in a sequential block.
• A <= operator is used to specify nonblocking assignments
• Example - Nonblocking Assignments

reg x, y, z;
reg [15:0] reg_a, reg_b; integer count;
//All behavioral statements must be inside an initial or always block

initial
begin
x = 0; y = 1; z = 1; //Scalar assignments
count = 0; //Assignment to integer variables
reg_a = 16'b0; reg_b = reg_a; //Initialize vectors
reg_a[2] <= #15 1'b1; //Bit select assignment with delay
reg_b[15:13] <= #10 {x, y, z}; //Assign result of concatenation
//to part select of a vector

count <= count + 1; //Assignment to an integer (increment)

end
 Application of nonblocking assignments

always @(posedge clock)

begin
reg1 <= #1 in1;
reg2 <= @(negedge clock) in2 ^ in3;
reg3 <= #1 reg1; //The old value of reg1
end

Example - Nonblocking Statements to Eliminate Race Conditions

//Illustration 1: Two concurrent always blocks with

// blocking statements
always @(posedge clock)
a = b;
always @(posedge clock)
b = a;
//Illustration 2: Two concurrent always blocks with
// nonblocking statements
always @(posedge clock)
a.<= b;
always @(posedge clock)
b.<= a;
Example 7-9 Implementing Nonblocking Assignments using Blocking ssignments

//Emulate the behavior of nonblocking assignments by

//using temporary variables and blocking assignments

always @(posedge clock)

Begin

// Read operation store values of right-hand-side //expressions

in temporary variables
temp_a = a;
temp_b = b;

// Write operation Assign values of temporary variables //to

left-hand-side variables

a = temp_b;
b = temp_a;
end
 Timing Controls

• Timing controls provide a way to specify the simulation time at which procedural
statements will execute.
• There are three methods of timing control:
1.delay-based timing control,
2.event-based timing control,
3.Level-sensitive timing control.
1.Delay-Based Timing Control
• Delay-based timing control in an expression specifies the time duration between
when the statement is encountered and when it is executed
• Delay-based timing control can be specified by a number, identifier, or a
mintypmax_expression.
• There are three types of delay control for procedural assignments:
i)regular delay control,
ii)intra-assignment delay control, and
iii)zero delay control.
 Regular delay control

• Regular delay control is used when a non-zero delay is specified to the left of a
procedural assignment
Example:
//define parameters
parameter latency = 20;
parameter delta = 2;
reg x, y, z, p, q;
initial
Begin
x = 0; // no delay control
#10 y = 1; // delay control with a number. Delay execution of
// y = 1 by 10 units
#latency z = 0; // Delay control with identifier. Delay of 20
Units
#(latency + delta) p = 1; // Delay control with expression
#y x = x + 1; // Delay control with identifier. Take value of
y.
#(4:5:6) q = 0; // Minimum, typical and maximum delay values.
//Discussed in gate-level modeling chapter.
end
 Intra-assignment delay control

• Instead of specifying delay control to the left of the assignment, it is possible to

assign a delay to the right of the assignment operator
Example
//define register variables
reg x, y, z;

//intra assignment delays

initial
begin
x = 0; z = 0;
y = #5 x + z; //Take value of x and z at the time=0,
// evaluate x + z and then wait 5 time units
// to assign value to y.
end
 Zero delay control

• Procedural statements in different always-initial blocks may be evaluated at the

same simulation time. T
• he order of execution of these statements in different always-initial blocks is
nondeterministic.
• Zero delay control is a method to ensure that a statement is executed last, after all
other statements in that simulation time are executed
Example
initial
begin
x = 0;
y = 0;
end

initial
begin
#0 x = 1; //zero delay control
#0 y = 1;
end
 2.Event-Based Timing Control

• An event is the change in the value on a register or a net.

• Events can be utilized to trigger execution of a statement or a block of statements.
• There are four types of event-based timing control:
i)regular event control,
ii)named event control,
iii)event OR control,
iv)level- sensitive timing control.
 Regular event control

• The @ symbol is used to specify an event control.

• Statements can be executed on changes in signal value or at a positive or
negative transition of the signal value
• Example
@(clock) q = d; //q = d is executed whenever signal clock
changes value
@(posedge clock) q = d; //q = d is executed whenever signal
// clock does a positive transition (
// 0 to 1,x or z, x to 1, z to 1 )
@(negedge clock) q = d; //q = d is executed whenever signal
// clock does a negative transition (
// 1 to 0,x or z, x to 0, z to 0)
q = @(posedge clock) d; //d is evaluated immediately and
// assigned to q at the positive edge of clock
 Named event control
• Verilog provides the capability to declare an event and then trigger and recognize
the occurrence of that event .
• A named event is declared by the keyword event.
• An event is triggered by the symbol ->. The triggering of the event is recognized
by the symbol @.
• Example
//This is an example of a data buffer storing data after
// the last packet of data has arrived.

event received_data; //Define an event

always @(posedge clock)//check at each positiveclock edge

begin
if(last_data_packet) //If this is the last data packet
->received_data; //trigger the event received_data
end

always @(received_data)
data_buf = {data_pkt[0], data_pkt[1], data_pkt[2],data_pkt[3]};
 Event OR Control

• Sometimes a transition on any one of multiple signals or events can trigger the
execution of a statement or a block of statements. This is expressed as an OR of
events or signals
Example 7-15 Event OR Control (Sensitivity List)

//A level-sensitive latch with asynchronous

reset
//Wait for reset or clock or d to change
always @( reset or clock or d)
begin
if (reset) //if reset signal is high, set q to 0.
q = 1'b0;
else if(clock) //if clock is high, latch input
q = d;
end
 Level-Sensitive Timing Control

• The symbol @ provided edge-sensitive control.

• Verilog also allows level- sensitive timing control, that is, the ability to wait for a
certain condition to be true before a statement or a block of statements is executed.
• The keyword wait is used for level- sensitive constructs.
always
wait (count_enable) #20 count = count + 1;
 Conditional Statements
//Type 1 conditional statement. No else statement.

if (<expression>) true_statement ;

//Type 2 conditional statement. One else statement

//Either true_statement or false_statement is
evaluated

if (<expression>) true_statement ;
else false_statement ;

//Type 3 conditional statement. Nested if-else-if.

//Choice of multiple statements. Only one is
executed.

if (<expression1>) true_statement1 ;
else if (<expression2>) true_statement2 ;
else if (<expression>) true_statement 3;

else default_statement ;
 Conditional Statement Examples
//Type 1 statements
if(!lock) buffer = data;
if(enable) out = in;

//Type 2 statements
if (number_queued < MAX_Q_DEPTH)
begin
data_queue = data;
number_queued = number_queued + 1;
end
else
$display("Queue Full. Try again");
//Type 3 statements
//Execute statements based on ALU control
signal.
if (alu_control == 0) y = x + z
else if(alu_control == 1) y = x - z;
else if(alu_control == 2) y = x * z;
else
$display("Invalid ALU control signal");
 Multiway Branching
1 case Statement
case (expression)
alternative1: statement1;
alternative2: statement2;
alternative3: statement3;
...
...
default: default_statement;
endcase

//Ex:-Execute statements based on the ALU

control signal
reg [1:0] alu_control;
...
...
case (alu_control)
2'd0 : y = x + z;
2'd1 : y = x - z;
2'd2 : y = x * z;
default : $display("Invalid ALU control signal");
endcase
 Example : 4-to-1 Multiplexer with Case Statement

module mux4_to_1 (out, i0, i1, i2, i3, s1, s0);

// Port declarations from the I/O diagram

output out;
input i0, i1, i2, i3;
input s1, s0;
reg out;

always @(s1 or s0 or i0 or i1 or i2 or i3)

case ({s1, s0}) //Switch based on concatenation of
control signals
2'd0 : out = i0;
2'd1 : out = i1;
2'd2 : out = i2;
2'd3 : out = i3;
default: $display("Invalid control signals");
endcase

endmodule
2.casex, casez Keywords

reg [3:0] encoding;

integer state;

casex (encoding) //logic value x represents a don't

care bit.
4'b1xxx : next_state = 3;
4'bx1xx : next_state = 2;
4'bxx1x : next_state = 1;
4'bxxx1 : next_state = 0;
default : next_state = 0;

endcase
 Loops

• There are four types of looping statements in Verilog: while, for, repeat, and forever.
• All looping statements can appear only inside an initial or always block.
1.While Loop
Example 1:

//Illustration 1: Increment count from 0 to 127. Exit at count 128.

//Display the count variable.

integer count;
initial
begin
count = 0;
while (count < 128) //Execute loop till count is 127.
//exit at count 128
begin
$display("Count = %d", count);
count = count + 1;
end
end
2. For Loop
• The keyword for is used to specify this loop. The for loop contains three parts:

• An initial condition
• A check to see if the terminating condition is true
• A procedural assignment to change value of the control variable

Example

integer count;

initial
for ( count=0; count < 128; count = count + 1)
$display("Count = %d", count);
Example:

//Initialize array elements

'define MAX_STATES 32
integer state [0: 'MAX_STATES-1]; //Integer array state
with elements 0:31
integer i;

initial
begin
for(i = 0; i < 32; i = i + 2) //initialize all even
locations with 0
state[i] = 0;
for(i = 1; i < 32; i = i + 2) //initialize all odd
locations with 1
state[i] = 1;
end
3.Repeat Loop

Example :

//increment and display count from 0 to 127

integer count;
initial
begin
count = 0;
repeat(128)
begin
$display("Count = %d", count);
count = count + 1;
end
end
4.Forever loop
Example :

//Example 1: Clock generation

//Use forever loop instead of always block
reg clock;
initial
begin
clock = 1'b0;
forever #10 clock = ~clock; //Clock with period of 20 units
end

//Example 2: Synchronize two register values at every positive

// edge of clock
reg clock;
reg x, y;
initial
forever @(posedge clock) x = y;
 Sequential and Parallel Blocks
• There are two types of blocks: sequential blocks and parallel blocks.
1.Sequential blocks
• The keywords begin and end are used to group statements into sequential blocks.
Example :

// Sequential block without delay

reg x, y;
reg [1:0] z, w;

initial
begin
x = 1'b0;
y = 1'b1;
z = {x, y};
w = {y, x};
end
2.Parallel blocks

• Parallel blocks, specified by keywords fork and join

//Example 1: Parallel blocks with delay.

reg x, y;
reg [1:0] z, w;

initial
fork
x = 1'b0; //completes at simulation time 0
#5 y = 1'b1; //completes at simulation time 5
#10 z = {x, y}; //completes at simulation time10
#20 w = {y, x}; //completes at simulation time
20
join
 Special Features of Blocks

• three special features available with block statements: nested blocks, named blocks, and
disabling of named blocks.
i)Nested blocks
• Blocks can be nested. Sequential and parallel blocks can be mixed
Example :

//Nested blocks
initial
begin
x = 1'b0;
fork
#5 y = 1'b1;
#10 z = {x, y};
join
#20 w = {y, x};

end
ii)Named blocks
• Blocks can be given names.

Example :
//Named blocks
module top;

initial
begin: block1 //sequential block named block1
integer i; //integer i is static and local to block1
// can be accessed by hierarchical name, top.block1.i
...
...
end

initial
fork: block2 //parallel block named block2
reg i; // register i is static and local to block2
// can be accessed by hierarchical name, top.block2.i
...
...
join
iii)Disabling named blocks
The keyword disable provides a way to terminate the execution of a named block
Example :
// Find the first bit with a value 1 in flag (vector variable)
reg [15:0] flag;
integer i; //integer to keep count
initial
begin
flag = 16'b 0010_0000_0000_0000;
i = 0;
begin: block1 //The main block inside while is named block1

while(i < 16)

begin
if (flag[i])
begin
$display("Encountered a TRUE bit at element number %d", i);
disable block1; //disable block1 because you found true bit.
end
i = i + 1;
end
end
end
 Examples: 4-to-1 Multiplexer

module mux4_to_1 (out, i0, i1, i2, i3, s1, s0);

output out;
input i0, i1, i2, i3;
input s1, s0;
reg out;
always @(s1 or s0 or i0 or i1 or i2 or i3)
begin
case ({s1, s0})
2'b00: out = i0;
2'b01: out = i1;
2'b10: out = i2;
2'b11: out = i3;
default: out = 1'bx;
endcase
end
endmodule
 Examples :4-bit Counter
//4-bit Binary counter
module counter(Q , clock, clear);
// I/O ports
output [3:0] Q;
input clock, clear;
//output defined as register
reg [3:0] Q;
always @( posedge clear or negedge clock)
begin
if (clear)
Q <= 4'd0;
else
Q <= Q + 1;

end
endmodule
 Example: 4 bit magnitude Comparator
module magnitudeComparator(AEQB, AGTB, ALTB, A, B);
output reg AEQB, AGTB, ALTB;
input [3:0] A, B;

always @(A,B)
begin
if( A === B )
begin
AEQB = 1;
AGTB = 0;
ALTB = 0;
end
else if ( A > B )
begin
AEQB = 0;
AGTB = 1;
ALTB = 0;
end
else
begin
AEQB = 0;
AGTB = 0;
ALTB = 1;
end
end
endmodule
 Example: Universal Shift Register
module universalShiftRegister(DATAOUT, clock, reset, MODE, DATAIN);
output reg [3:0] DATAOUT;
input clock, reset;
input [1:0] MODE;
input [3:0] DATAIN;

always @(posedge clock)

begin
if(reset)
DATAOUT <= 0;
else
begin
case(MODE)
2'b00 : DATAOUT <= DATAOUT; // locked mode, do nothing
2'b01 : DATAOUT <= {DATAIN[0], DATAOUT[3:1]}; //DATAOUT >> 1; // RFSR
2'b10 : DATAOUT <= {DATAOUT[2:0], DATAIN[0]}; //DATAOUT << 1; // LFSR
2'b11 : DATAOUT <= DATAIN; // parallel in parallel out
endcase
end
end

endmodule
 Example:up_down_counter
module up_down_counter ( out , up_down , clk , data , reset);
output [7:0] out;
input [7:0] data;
input up_down, clk, reset;
reg [7:0] out;

always @(posedge clk)

if (reset)
out <= 8'b0 ;
else if (up_down)
out <= out + 1;
else
out <= out - 1;
endmodule
THANK YOU