APPROVED BY AICTE NEW DELHI, AFFILIATED TO VTU BELGAUM

DEPARTMENT OF ELECTRONICS & COMMUNICATION

ENGINEERING

DSD USING VERILOG LABORATORY

SUBJECT LAB MANUAL – BEC302
III-SEMESTER
2024-2025

Prepared by: Reviewed by: Approved by:

Dr. A. Deepa Dr.Anantha Padmanabhan Dr.Arunvikas Singh

Assistant Professor Head of the Department Principal
Dept. of ECE Dept. of ECE GCEM
GCEM GCEM

81/1, 182/1, Hoodi Village, Sonnenahalli, K.R. Puram, Bengaluru, Karnataka-

560048.
 LIST OF EXPERIMENTS & SCHEDULE

Course Code: BEC302

Course Title: DIGITAL SYSTEM DESIGN LAB USING
VERILOG

S. No Experiments Page. No

1 Design of Logic gates 1

2 To simplify the given Boolean expressions 2

and realize using Verilog program
To realize Adder/Subtractor(Full/half)circuits
3 using Verilog data flow description. 3

4 To realize 4-bit ALU using Verilog program. 4

5 To realize the following Code converters 5

using Verilog Behavioral description a)Gray
to binary and vice versa b)Binary to excess3
and vice versa

6 To realize using Verilog Behavioral 6

description:8:1mux, 8:3encoder, Priority
encoder

7 To realize using Verilog Behavioral 7

description:1:8Demux, 3:8 decoder,2 –bit
Comparator
To realize using Verilog Behavioral
8 description: Flip-flops: a)JK type b)SR type 8
c)T type and d)D type

9 To realize Counters-up/down (BCD and 9

binary)using Verilog Behavioral description.

Course Coordinator HOD

 Internal Assessment Mark Split Up

Observation : 2 Marks

Conduction : 6 Marks

Viva : 2 Marks

Total : 10 Marks

IA Exam : 50 Marks
Introduction to Combinational Circuit Design
EXP:0 Design of Logic gates
1.1 Introduction
The purpose of this experiment is to simulate the behavior of several of the basic logic gates and you will
connect several logic gates together to create simple digital model.
1.2 Software tools Requirement
Equipments:
Computer with Modelsim Software
Specifications:
HP Computer P4 Processor – 2.8 GHz, 2GB RAM, 160 GB Hard Disk
Softwares: Modelsim - 5.7c, Xilinx - 6.1i.
Algorithm
STEP 1: Open ModelSim XE II / Starter 5.7C
STEP 2: File -> Change directory -> D:\<register number>
STEP 3: File -> New Library -> ok
STEP 4: File -> New Source -> Verilog
STEP 5: Type the program
STEP 6: File -> Save -> <filename.v>
STEP 7: Compile the program
STEP 8: Simulate -> expand work -> select file -> ok
STEP 9: View -> Signals
STEP 10: Select values -> Edit -> Force -> input values
STEP 11: Add -> Wave -> Selected signals -> Run
STEP 12: Change input values and run again
1.3 Logic Gates and their Properties

Gate Description Truth Table Logic Symbol Pin Diagram

The output is active A B Output
high if any one of the Q
OR 0 0
input is in active high
0 1 0
state, Mathematically,
1 1
Q = A+B 0
1 1
1
1
The output is active A B Output
high only if both the Q
AND 0 0
inputs are in active 0
high state, 0 1
Mathematically, 0
1 0
Q = A.B 0
1 1
1
In this gate the output A Output
is opposite to the input Q
NOT 0
state, Mathematically,
1 1
Q=A
0

The output is active A B Output

high only if both the Q
NOR 0 0
inputs are in active low 1
state, Mathematically, 0 1
1 0
Q = (A+B)’ 0
1 0
1
0
 The output is active A B Output
high only if any one of Q
NAND 0 0
the input is in active
0 1 1
low state,
Mathematically, 1
1 0
Q = (A.B)’ 1
1 1
0
The output is active A B Output
high only if any one of Q
XOR 0 0
the input is in active
0 1 0
high state,
Mathematically, 1 0 1

Q = A.B’ + B.A’ 1 1 1
0 7486

1.4 Pre lab Questions

1. What is truth table?
2. Which gates are called universal gates?
3. What is the difference b/w HDL and software language?
4. Define identifiers.
5. A basic 2-input logic circuit has a HIGH on one input and a LOW on the other input, and the output is
HIGH. What type of logic circuit is it?
6. A logic circuit requires HIGH on all its inputs to make the output HIGH. What type of logic circuit is
it?
7. Develop the truth table for a 3-input AND gate and also determine the total number of possible
combinations for a 4-input AND gate.
VERILOG Program
a) AND Gate
Structural Model Data Flow Model BehaviouralModel
moduleandstr(x,y,z); moduleanddf(x,y,z); module andbeh(x,y,z);
inputx,y; inputx,y; input x,y;
output z; output z; output z;
and g1(z,x,y); assign z=(x&y); reg z;
endmodule endmodule always @(x,y)
z=x&y;
endmodule

b) NAND Gate
Structural Model Data Flow Model BehaviouralModel
modulenandstr(x,y,z); modulenanddf(x,y,z); module nandbeh(x,y,z);
inputx,y; inputx,y; input x,y;
output z; output z; output z;
nand g1(z,x,y); assign z= !(x&y); reg z;
endmodule endmodule always @(x,y)
z=!(x&y);
endmodule

c) OR Gate
Data Flow Model BehaviouralModel
module ordf(x,y,z); module orbeh(x,y,z);
inputx,y; input x,y;
output z; output z;
assign z=(x|y); reg z;
endmodule always @(x,y)
z=x|y;
endmodule

d) NOR Gate
Data Flow Model BehaviouralModel
modulenordf(x,y,z); Modulenorbeh(x,y,z);
inputx,y; input x,y;
output z; output z;
assign z= !(x|y); reg z;
endmodule always @(x,y)
z=!(x|y);
endmodule
 e) XOR Gate
Data Flow Model BehaviouralModel
module xordf(x,y,z); module xorbeh(x,y,z);
inputx,y; input x,y;
output z; output z;
assign z=(x^y); reg z;
endmodule always @(x,y)
z=x^y;
endmodule

f) XNOR Gate
Data Flow Model BehaviouralModel
modulexnordf(x,y,z); module xnorbeh(x,y,z);
inputx,y; input x,y;
output z; output z;
assign z= !(x^y); reg z;
endmodule always @(x,y)
z=!(x^y);
endmodule

g) NOT Gate
Data Flow Model BehaviouralModel
module notdf(x,z); module notbeh(x,z);
input x; input x;
output z; output z;
assign z= !x; reg z;
endmodule always @(x)
z=!x;
endmodule

Post lab Questions

1. What is meant by ports?
2. Write the different types of port modes.
3. What are different types of operators?
4. What is difference b/w <= and := operators?
5. What is meant by simulation?
6. How to give the inputs in modelsim software.
EXP:1 To simplify the given Boolean expressions and realize using
Verilog program.

Introduction
The purpose of this experiment is to introduce the Boolean expression.
Software tools equirement:
Equipments:
Computer with Xilinx Software
Softwares: Xilinx - 9.1i.
Algorithm
1. Define module.
2. Declare inputs and outputs.
3. Describe functionality.
4. End source code.
5. Compile and Run program.

Theory:
A Boolean expression always produces a Boolean value. A Boolean expression is composed of a combination of the
Boolean constants (True or False), Boolean variables and logical connectives. Each Boolean expression represents a
Boolean function.

Boolean Expression:

Y = AB+CD
VERILOG Program

Module Circuit_Boolean_CA(Y, A, B, C, D);

output Y;
input A, B, C, D;
// E = AB + CD
assign Y =( (A&B) |C&D)) ;
endmodule

Results:-
Written and simulated the HDL model for Boolean expression and verified the response with the truth table
and concluded that the Boolean expression is working fine.
EXP: 2 To realize Adder/Subtractor (Full/half) circuits using Verilog
data flow description.
Introduction
The purpose of this experiment is to introduce the design of simple combinational circuits, in this case
half adders, half subtractors, full adders and full subtractors.
Software tools equirement:
Equipments:
Computer with Xilinx Software
Softwares: Xilinx - 6.1i.
Algorithm
1. Define module.
2. Declare inputs and outputs.
3. Describe functionality.
4. End source code.
5. Compile and Run program.

Theory:

ADDER:
An Adder is a circuit which performs addition of binary numbers. Producing sum and carry. An half adder is a
digital circuit which performs addition of two binary numbers which are one bit each and produces a sum and a
carry (one bit each). A full adder is a digital circuit which performs addition of three binary numbers (one bit
each), to produce a sum and a carry (one bit each). Full adders are basic block of any adder circuit as they add
two numbers along with the carry from the previous addition.

SUBTRACTORS:
Subtractors are digital circuits which perform subtraction of binary numbers to produce a difference and a borrow if
any. A half subtractor subtracts two one bit numbers to give their difference and a borrow if any. A full subtractor
subtracts two one bit numbers along with a borrow (from previous stage) to generate a difference and a borrow.

Logic Diagram:
Pre lab Questions
1. What is meant by combinational circuits?
2. Write the sum and carry expression for half and full adder.
3. Write the difference and borrow expression for half and full subtractor.
4. What is signal? How it is declared?
 VERILOG Program:

HALF ADDER: FULL ADDER:

Dataflow model
Module halfaddd (sum,carry,a,b);
Dataflow model
Output sum, carry;
input a,b; Module fulladd (sum,carry,a,b,c);output
assign sum = a ^ b;assign sum,carry;
carry=a&b; Input a,b,c;
endmodule assign sum = a ^ b^c; assign
carry=(a&b) | (b&c) |(c&a);
endmodule

HALF SUBTRACTOR: FULL SUBTRACTOR:

Dataflow Model Dataflow Model
Module halfsub (diff, borrow, a, b); Module fullsub (diff, borrow, a, b, c);
output diff, borrow; output diff, borrow;
input a,b; input a,b,c;
assign diff = a ^ b; assign assign diff = a^b^c;
borrow=(~a&b); assign borrow=(~a&b)|(~(a^b)&c);
endmodule endmodule

Post lab Questions

1. What are the signal assignment statements?
2. What are the concurrent statements?
3. Write short notes on : a) Process statement b) Block statement
4. Write about sequential statements.
5. What is the difference b/w high impedance state of the signal(Z) and unknown state of the signal(X).

Results:-
Written and simulated the HDL model for Adders (Half&Full) and Subtractors (Half&Full) and verified the
response with the truth table and concluded that the adder and subtractor circuit is working fine.
EXP: 3 To realize 4-bit ALU using Verilog program.
Introduction
The purpose of this experiment is to introduce ALU of digital computers is an aspect of logic design with
the objective of developing appropriate algorithms in order to achieve an efficient utilization of the
available hardware.

Software tools requirement:

Equipments:
Computer with Xilinx Software
Specifications:
Softwares: Xilinx - 9.1i.
Algorithm
1. Define module.
2. Declare inputs and outputs.
3. Describe functionality.
4. End source code.
5. Compile and Run program.

Theory:
The ALU, or the arithmetic and logic unit, is the section of the processor that is involved with executing operations of
an arithmetic or logical nature. In ECL, TTL and CMOS, there are available integrated packages which are referred to
as arithmetic and logic units (ALU). The logic circuitry in this units is entirely combinational (i.e. consists of gates
with no feedback and no flip- flops).The ALU is an extremely versatile and useful device since, it makes available, in
single package, facility for performing many different logical and arithmetic operations.
Arithmetic Logic Unit (ALU) is a critical component of a microprocessor and is the core component of central
processing unit. ALU can perform all the 16 possible logic operations or 16 different arithmetic operations on active
HIGH or active LOW operands. . Arithmetic instructions include addition, subtraction, and shifting operations, while
logic instructions include Boolean comparisons, such as AND, OR, XOR, and NOT operations.

OPCODE ALU OPERATION

1 A+B
2 A-B
3 A Complement
4 A*B
5 A and B
6 Not A
7 A1*B1
8 A nand B
9 A xor B
 Black box

a(3 to 0)

b(3 to 0)
ALU y (7 to 0)
opcode (2 to 0)

Truth table:

Operation Opcode a b y
A+B 001 1111 0000 00001111
A-B 010 1110 0010 00001100
Not A 011 1111 0000 11110000
A or B 100 1111 1000 00001111
A and B 101 1001 1000 00001000
A nand B 110 1111 0010 11111101
A xor B 111 0000 0100 00000100

Program:

VERILOG CODE
module ALU ( a, b, s, en, y, y_mul );
input [3:0] a, b;
input [2:0] opcode;
input en;
output [3:0]y;
output [7:0]y_mul;
reg [3:0] y;
reg [7:0]y_mul;
always@( a, b, opcode )
begin
if(en==1)
case(opcode)
3’b001: y=a + b;
3’b010: y=a - b;
3’b011: y= (~a);
3’b100: y= (a | b);
3’b101: y_mul= (a & b);
3’b110: y_mul= ~ (a & b);
3’b111: y= (a ^ b);
default: begin end
endcase
else
y=4’b0;
y_mul=8’b0;
end
endmodule
RESULT: 4 bit ALU operations have been realized and simulated using verilog codes.
EXP:4 To realize the following Code converters using Verilog
Behavioral description a) Gray to binary and vice versa b) Binary to excess3
and vice versa
Introduction
The purpose of this experiment is to write and simulate a VERILOG program for Binary to gray code
conversion and vice versa.

Software tools equirement:

Equipments:
Computer with Xilinx Software
Specifications:
Softwares: Xilinx - 9.1i.
Algorithm
1. Define module.
2. Declare inputs and outputs.
3. Describe functionality.
4. End source code.
5. Compile and Run program.

Theory:
The reflected binary code or Gray code is an ordering of the binary numeral system such that two successive values
differ in only one bit (binary digit). Gray codes are very useful in the normal sequence of binary numbers generated
by the hardware that may cause an error or ambiguity during the transition from one number to the next. So, the
Gray code can eliminate this problem easily since only one bit changes its value during any transition between two
numbers.
Conversion of Binary to Gray Code
Gray codes are used in rotary and optical encoders, Karnaugh maps, and error detection. The hamming distance of
two neighbours Gray codes is always 1 and also first Gray code and last Gray code also has Hamming distance is
always 1, so it is also called Cyclic codes.
Using Exclusive-Or (⊕) operation −
This is very simple method to get Gray code from Binary number. These are following steps for n-bit binary
numbers −
The most significant bit (MSB) of the Gray code is always equal to the MSB of the given Binary code.
Other bits of the output Gray code can be obtained by XORing binary code bit at the index and previous index.
For example, for 3-bit binary number, let Binary digits are b2 , b1 , b0, where b2 is the most significant bit (MSB)
and b0 is the least significant bit (LSB) of Binary. Gray code digits are g2 , g1 , g0, where g2 is the most significant
bit (MSB) and g0 is the least significant bit (LSB) of Gray code.

Binary to Gray Converter Behavioral Modelling Verilog Code:

Binary Number is the default way to store numbers, but in many applications, binary numbers are difficult to use and
a variety of binary numbers is needed. This is where Gray codes are very useful.
Gray code has a property that two successive numbers differ in only one bit because of this property gray code does
the cycling through various states with minimal effort and is used in K-maps, error correction, communication, etc.

How to generate n bit Gray Codes?

n-bit Gray Codes can be generated from a list of (n-1)-bit Gray codes using the following steps.
Let the list of (n-1)-bit Gray codes be L1. Create another list L2 which is the reverse of L1.
Modify the list L1 by prefixing a ‘0’ in all codes of L1.
Modify the list L2 by prefixing a ‘1’ in all codes of L2.
Concatenate L1 and L2. The concatenated list is the required list of n-bit Gray codes.

In computer science many a time we need to convert binary code to gray code and vice versa. This conversion can
be done by applying the following rules :
Binary to Gray conversion :

The Most Significant Bit (MSB) of the gray code is always equal to the MSB of the given binary code.
Other bits of the output gray code can be obtained by XORing binary code bit at that index and previous index.

Binary code to gray code conversion

LOGIC DIAGRAM: TRUTHTABLE:

Program:
module Bin_Gry ( din, dout );
input [2:0]din;
output [2:0]dout;
reg [2:0]dout;
always @ (din)
begin
case (din)
0 : dout = 0;
1 : dout = 1;
2 : dout = 3;
3 : dout = 2;
4 : dout = 6;
5 : dout = 7;
6 : dout = 5;
7 : dout = 4;
default: dout = 3’b xxx;
endcase
end
endmodule

Xillinx Output:
 Gray to binary conversion :

1. The Most Significant Bit (MSB) of the binary code is always equal to the MSB of the given gray code.
2. Other bits of the output binary code can be obtained by checking the gray code bit at that index. If the current
gray code bit is 0, then copy the previous binary code bit, else copy the invert of the previous binary code bit.

LOGIC DIAGRAM:

TRUTH TABLE:
PROGRAM:

module Gray_to_binary ( din ,dout );

output [2:0] dout ;
reg [2:0] dout ;
input [2:0] din ;
always @ (din)
begin
case (din)
0 : dout = 0;
1 : dout = 1;
2 : dout = 3;
3 : dout = 2;
4 : dout = 7;
5 : dout = 6;
6 : dout = 4;
7 : dout = 5;
default : dout = 3’b000;
endcase
end
endmodule

OUTPUT:

Result:

Written and simulated the HDL model for converters (Binary to Gray & vice versa, Binary to Excess3 and Vice Versa)
and verified the response with the truth table.
EXP:5 To realize using Verilog Behavioral description: 8:1 mux, 8:3
encoder, Priority encoder
Introduction
The purpose of this experiment is to write and simulate a VERILOG program for 8:1 mux, 8:3 encoder
and Priority encoder.

Software tools equirement:

Equipments:
Computer with Xilinx Software
Specifications:
Softwares: Xilinx - 9.1i.
Algorithm
1. Define module.
2. Declare inputs and outputs.
3. Describe functionality.
4. End source code.
5. Compile and Run program.

Theory:
A multiplexer is a device that selects one output from multiple inputs. It is also known as a data selector. We refer to
a multiplexer with the terms MUX and MPX.
Multiplexers are used in communication systems to increase the amount of data sent over a network within a certain
amount of time and bandwidth. It allows us to squeeze multiple data lines into one data line.
It switches between one of the many input lines and combines them one by one to the output. It decides which input
line to switch using a control signal.
Physically, a multiplexer has n input pins, one output pin, and m control pins. n = 2^m. Since a multiplexer's job is to
select one of the data input lines and send it to the output, it is also known as a data selector.

Truth table:
Logic Diagram

Figure 8:1 Multiplexer

VERILOG Program
8:1 MUX
BehaviouralModel
Module mux81beh (s,i0,i1,i2,i3,i4,i5,i6,i7,y);
input [2:0] s;
input i0,i1,i2,i3,i4,i5,i6,i7;
output y;
reg y;
always@(i0,i1,i2,i3,i4,i5,i6,i7,s)
begin
case(s)
begin
3'd0:y=i0;
3'd1:y=i1;
3'd2:y=i2;
3'd3:y=i3;
3'd4:y=i4;
3'd5:y=i5;
3'd6:y=i6;
3'd7:y=i7;
endcase
end
endmodule
8:3 ENCODER:
Theory:
An Encoder is a combinational circuit that performs the reverse operation of Decoder.It has maximum
of 2^n input lines and ‘n’ output lines, hence it encodes the information from 2^n inputs into an n-bit code.
It will produce a binary code equivalent to the input, which is active High. Therefore, the encoder encodes
2^n input lines with ‘n’ bits.
LOGIC DIAGRAM:

Figure 8:3 Encoder

VERILOG Program
8:3 Encoder
BehaviouralModel
module enc83beh(din,a,b,c);
input [7:0]din;
output a,b,c;
reg a,b,c;
always@(din)
case(din)
8'b00000001:begin a=1'b0;b=1'b0,c=1'b0;end
8'b00000010:begin a=1'b0;b=1'b0;c=1'b1;end
8'b00000100:begin a=1'b0;b=1'b1;c=1'b0;end
8'b00001000:begin a=1'b0;b=1'b1;c=1'b1;end
8'b00010000:begin a=1'b1;b=1'b0,c=1'b0;end
8'b00100000:begin a=1'b1;b=1'b0,c=1'b1;end
8'b01000000:begin a=1'b1;b=1'b1,c=1'b0;end
8'b10000000:begin a=1'b1;b=1'b1,c=1'b1;end
endcase
endmodule
Verilog Priority Encoder

In Digital System Circuit, an Encoder is a combinational circuit that takes 2n input signal lines and
encodes them into n output signal lines. When the enable is true i.e., the corresponding input signal lines
display the equivalent binary bit output.
For example, 8:3 Encoder has 8 input lines and 3 output lines, 4:2 Encoder has 4 input lines and 2 output
lines, and so on.
An 8:3 Priority Encoder has seven input lines i.e., i0 to i7, and three output lines y2, y1, and y0. In 8:3
Priority Encoder i7 have the highest priority and i0 the lowest.

Truth Table:
Input Output

e i i i i i i i i y y y
n 7 6 5 4 3 2 1 0 2 1 0

0 x x x x x x x x z z z

1 0 0 0 0 0 0 0 1 0 0 0

1 0 0 0 0 0 0 1 x 0 0 1

1 0 0 0 0 0 1 x x 0 1 0

1 0 0 0 0 1 x x x 0 1 1

1 0 0 0 1 x x x x 1 0 0

1 0 0 1 x x x x x 1 0 1

1 0 1 x x x x x x 1 1 0

1 1 x x x x x x x 1 1 1
 VERILOG CODE:

module priorityencoder_83(en,i,y);
input en;
input [7:0]i;
output [2:0]y;
reg [2:0]y;
always @(en,i
begin
if(en==1)
begin
if(i[7]==1) y=3'b111;
else if(i[6]==1) y=3'b110;
else if(i[5]==1) y=3'b101;
else if(i[4]==1) y=3'b100;
else if(i[3]==1) y=3'b011;
else if(i[2]==1) y=3'b010;
else if(i[1]==1) y=3'b001;
else
y=3'b000;
end
else y=3'bzzz;
end
endmodule

Result:

Thus the OUTPUT of 8:1 Mux, 8 to 3 encoder and 8 to 3 priority encoder is verified by simulating the
VERILOG HDL code
EXP:5 To realize using Verilog Behavioral description for 1:8
Demux, 3:8 decoder, 2-bit Comparator

Introduction
The purpose of this experiment is to write and simulate a VERILOG program for 1:8 Demux, 3:8
decoder, 2-bit Comparator.

Software tools equirement:

Equipments:
Computer with Xilinx Software
Specifications:
Softwares: Xilinx - 9.1i.
Algorithm
1. Define module.
2. Declare inputs and outputs.
3. Describe functionality.
4. End source code.
5. Compile and Run program.

Theory:
Decoder:
This Decoder is a combinational logic circuit and its purpose is to decode the data given to it. It is made of n
number of input lines and 2*n number of output lines. For every probable input condition, there are various
output signals and depending on the input only one output signal will produce the logic. So, this n-to-2n
decoder is also called as min-term generator where each output outcomes only at particular input.

Demultiplexer:
This Demultiplexer is kind of same to the decoder, but it contains select lines as well. It is used to send the
single input over the multiple output lines. It accepts data from one input signal and transferred it over the
provided number of output lines. It contains data input line, select lines and output lines.

2-Bit Magnitude Comparator :

A comparator used to compare two binary numbers each of two bits is called a 2-bit magnitude comparator. It
consists of four inputs and three outputs to generate less than, equal to and greater than between two binary
numbers.

The truth table for a 2-bit comparator is given below:

 Truth Table of 2-Bit Comparator

1:8 Demultiplexer
VERILOG Program

1:8 DEMUX
module demux18beh(i, sel, y);
input i;
input [2:0] sel;
output [7 :0] y ;
reg [7:0] y;
always@(i,sel)
begin
y=8'd0;
case(sel)
3'd0:y[0]=i;
3'd1:y[1]=i;
3'd2:y[2]=i;
3'd3:y[3]=i;
3'd4:y[4]=i;
3'd5:y[5]=i;
3'd6:y[6]=i;
default:y[7]=i;
endcase
end
endmodule

3:8 DECODER:

module decoder38beh(sel,out1);
input [2:0] sel;
output [7:0] out1;
reg [7:0] out1;
always @(sel,out1)
begin
case (sel)
3’b000 : out1 =8’b00000001;
3’b001 : out1 =8’b00000010;
3’b010 : out1 =8’b00000100;
3’b011 : out1 =8’b00001000;
3’b100 : out1 =8’b00010000;
3’b101 : out1 =8’b00100000;
3’b110 : out1 =8’b01000000;
default : out1 = 8’b10000000;
end
endcase
endmodule
2- BIT COMPARATOR:

module 2_Mag_Comp( a,b, equal, greater, lower );

input [1:0]a,b;
output equal, greater, lower ;
reg greater, equal, lower;
initial greater = 0, equal = 0, lower = 0;
always @ (a or b)
begin
if (a < b)
begin
greater = 0; equal = 0; lower = 1;
end
else if (a == b)
begin
greater = 0; equal = 1; lower = 0;
end
else
begin
greater = 1; equal = 0; lower = 0;
end
end
endmodule

Result:
Thus the OUTPUT of 1:8 Demux, 3 to 8 decoder and 2 bit comparator is verified by simulating the VERILOG
HDL code.
EXP 7: To realize using Verilog Behavioral description: Flip-flops: a) JK
type b) SR type c) T type and d) D type

Introduction

The purpose of this experiment is to write and simulate a VERILOG program for JK , SR , T and D
type flip-flops.

Software tools equirement:

Equipments:
Computer with Xilinx Software
Specifications:
Softwares: Xilinx - 9.1i.
Algorithm
1. Define module.
2. Declare inputs and outputs.
3. Describe functionality.
4. End source code.
5. Compile and Run program.

Theory:
Flip-Flops Logic diagram and their properties

Flip-flops are synchronous bitable devices. The term synchronous means the output changes state only
when the clock input is triggered. That is, changes in the output occur in synchronization with the clock.
A flip-flop circuit has two outputs, one for the normal value and one for the complement value of the
stored bit. Since memory elements in sequential circuits are usually flip-flops, it is worth summarizing the
behavior of various flip-flop types before proceeding further.
All flip-flops can be divided into four basic types: SR, JK, D and T. They differ in the number of inputs
and in the response invoked by different value of input signals. The four types of flip-flops are defined in
the Table 5.1. Each of these flip-flops can be uniquely described by its graphical symbol, its characteristic
table, its characteristic equation or excitation table. All flip-flops have output signals Q and Q'.
Flip-
Flip-Flop Symbol Characteristic Table Characteristic Equation
Flop
Name

Q(next) = S + R’Q SR = 0
S R Q(next)
0 0 Q

SR 0 1 0
1 0 1
1 1 ?

J K Q(next)
0 0 Q
0 1 0
JK Q(next) = JQ’ + K’Q
1 0 1
1 1 Q’

D Q(next)

D 0 0 Q(next) = D
1 1

Q(next) = TQ’ + T’Q

T Q(next)

T 0 Q
1 Q’

Flip-flops and their properties

Logic Diagram

Figure D- Flip Flop

Figure JK Flip Flop

Figure T Flip Flop

Figure T Flip Flop

Behavioral Modelling:

SR FLIPFLOP: T Flip Flop D Flip Flop JK Flip Flop

module sr_beh(s,r,q,q_n); module t_beh(q,q1,t,c); Module dff_async_reset( module jk(q,q1,j,k,c);

input s, r; output q,q1; data, clk, reset ,q ); output q,q1;
output q, q_n; input t,c; input data, clk, reset ; input j,k,c;
regq, q_n; reg q,q1; output q; reg q,q1;
always@(s,r) initial reg q; initial
begin begin always @ ( posedgeclk or begin
negedge reset)
q,n = ~(s|q); q=1'b1; q=1'b0;
if (~reset)
assign q = ~(r | q_n); q1=1'b0; q1=1'b1;
endmodule begin
end end
q <= 1'b0;
always @ (c) always @ (posedge c)
end
begin begin
else
if(c) case({j,k})
begin
begin {1'b0,1'b0}:begin q=q;
q <= data; q1=q1; end
if (t==1'b0)
end {1'b0,1'b1}: begin q=1'b0;
begin
endmodule q1=1'b1; end
q=q; q1=q1;
{1'b1,1'b0}:begin q=1'b1;
end
q1=1'b0; end
else
{1'b1,1'b1}: begin q=~q;
begin q1=~q1; end
q=~q; q1=~q1; endcase
end end
end endmodule
endmodule

Result:

Thus the OUTPUT of all the flip-flop is verified by simulating the VERILOG HDL code.
EXP 8 : To realize Counters - up/down (BCD and binary) using Verilog
Behavioral description.
Introduction

The purpose of this experiment is to write and simulate a VERILOG program for JK , SR , T and D
type flip-flops.

Software tools equirement:

Equipments:Computer with
Xilinx Software
Specifications:
Softwares: Xilinx - 9.1i.
Algorithm
1. Define module.
2. Declare inputs and outputs.
3. Describe functionality.
4. End source code.
5. Compile and Run program.

Theory:
Counters are used in many different applications. Some count up from zero and provide a change in state of output
upon reaching a predetermined value; others count down from a preset value to zero to provide an output state change.

However, some counters can operate in both up and down count mode, depending on the state of an up/down count
mode input pin. They can be reversed at any point within their count sequence.
• BCD counter: Before the counter recycles, the counter counts from 0000 to 1001.

Logic Diagram

Figure 6.3.1 Updown Counter

4 VERILOG Program
bit binary up/down counter:
module updown (out,clk,reset,updown);
output [3:0]out;
input clk, reset, updown;
reg [3:0]out;
always @(posedgeclk)

begin

if(reset)
out<= 4'b0;
else if(updown)

begin

out<=out+1;
end
else
beginout<=out-1;
end
end
endmodule

4 bit BCD up/down counter:

module BCDupdown(Clk, reset, UpOrDown, Count );

input Clk,reset,UpOrDown;
output [3 : 0] Count;
reg [3 : 0] Count = 0;
always @(posedge(Clk),UpOrDown)
begin
if(reset == 1)
Count <= 0;
else
begin
 if(UpOrDown == 1) // High for Up Counter and Low for Down Counter
begin
if(Count == 15)
Count <= 0;
else
Count <= Count + 1;
end
else
begin
if(Count == 0)
Count <= 15;
else
Count <= Count - 1;
end
end
end

endmodule

Result:

Thus the OUTPUT of counters is verified by simulating the VERILOG HDL code.
EXP 9: Verilog Program to interface a Stepper motor to the FPGA/CPLD and rotate the motor in the specified
direction (by N steps).

module stepper_motor_full_step ( start ,clk ,dout );

output [3:0] dout ;

reg [3:0] dout ;

input start ;
wire start ;
input clk ;
wire clk ;

reg [1:0] m ;

initial m = 0;

always @ (posedge (clk)) begin

if (start)
m <= m + 1;
end

always @ (m) begin

case (m)
0 : dout = 8;
1 : dout = 4;
2 : dout = 2;
default : dout = 1;
endcase
end

endmodule