Gate-Level Modeling

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 INTRODUCTION
• Most digital design is now done at gate level or
higher levels of abstraction.
• At gate level, the circuit is described in terms of
gates (e.g., and, nand).
• Verilog supports basic logic gates as predefined
primitives
• These primitives are instantiated like modules
except that they are predefined in Verilog and do
not need a module definition
Gate Types
 Gate Instantiation of And/Or Gates

// basic gate instantiations.

and a1(OUT, IN1, IN2);
nand na1(OUT, IN1, IN2);
or or1(OUT, IN1, IN2);
nor nor1(OUT, IN1, IN2);

xor x1(OUT, IN1, IN2);

xnor nx1(OUT, IN1, IN2);
// More than two inputs; 3 input
nand gate nand na1_3inp(OUT, IN1,IN2,IN3);

// gate instantiation without instance

name
and (OUT, IN1, IN2); // legal gate
instantiation
Truth Tables for And/Or
 Buf/Not Gates
• Buf/not gates have one scalar input and one or
more scalar outputs.
• The last terminal in the port list is connected
to the input. Other terminals are connected to
the outputs
•Two basic buf/not gate primitives are provided

in Verilog.
buf not
Gate Instantiations of Buf/Not Gates :
// basic gate instantiations.
buf b1(OUT1, IN);
not n1(OUT1, IN);
// More than two outputs
buf b1_2out(OUT1, OUT2, IN);

// gate instantiation without

instance name
not (OUT1, IN);
// legal gateinstantiation
Truth Tables for Buf/Not Gates
 Bufif/notif

• Gates with an additional control signal on buf

and not gates are also available
• bufif1 bufif0
• notif1 notif0
• These gates propagate only if their control
signal is asserted
 Array of Instances

• There are many situations when repetitive

instances are required.
• These instances differ from each other only
by the index of the vector to which they are
connected.
• To simplify specification of such instances,
Verilog HDL allows an array of primitive
instances to be defined
 Simple Array of Primitive Instances
wire [7:0] OUT, IN1, IN2;
// basic gate stantiations.
nand n_gate[7:0](OUT,IN1, IN2);
// This is equivalent to the
Following 8 instantiations
Nand n_gate0(OUT[0], IN1[0], IN2[0]);
nand n_gate1(OUT[1], IN1[1], IN2[1]);
nand n_gate2(OUT[2], IN1[2], IN2[2]);
nand n_gate3(OUT[3], IN1[3], IN2[3]);
nand n_gate4(OUT[4], IN1[4], IN2[4]);
nand n_gate5(OUT[5], IN1[5], IN2[5]);
nand n_gate6(OUT[6], IN1[6], IN2[6]);
nand n_gate7(OUT[7], IN1[7], IN2[7]);
Example 1 :Gate-level multiplexer

Figure : 4-to-1 Multiplexer

Logic Diagram for Multiplexer
 Verilog Description of Multiplexer
module mux4_to_1 (out, i0, i1, i2, i3, s1, s0);

// Port declarations from the I/O diagram

output out;
input i0, i1, i2, i3;
input s1, s0;
// Internal wire declarations
wire s1n, s0n;
wire y0, y1, y2, y3;

// Gate instantiations
// Create s1n and s0n signals.
not (s1n, s1);
not (s0n, s0);

// 3-input and gates instantiated

and (y0, i0, s1n, s0n);
and (y1, i1, s1n, s0);
and (y2, i2, s1, s0n);
and (y3, i3, s1, s0);

// 4-input or gate instantiated

or (out, y0, y1, y2, y3);
endmodule
 Stimulus for Multiplexer
// Define the stimulus module (no ports)
module stimulus;

// Declare variables to be connected

// to inputs
reg IN0, IN1, IN2, IN3;
reg S1, S0;

// Declare output wire

wire OUTPUT;
// Instantiate the multiplexer
mux4_to_1 mymux(OUTPUT, IN0,
IN1, IN2, IN3, S1, S0);
// Stimulate the inputs
// Define the stimulus module (no ports)
initial
Begin
// set input lines
IN0 = 1; IN1 = 0; IN2 = 1; IN3 = 0;
#1 $display("IN0= %b, IN1= %b, IN2= %b, IN3= %b\
n",IN0,IN1,IN2,IN3);

// choose IN0
S1 = 0; S0 = 0;
#1 $display("S1 = %b, S0 = %b, OUTPUT
= %b \n", S1, S0, OUTPUT);
// choose IN1
S1 = 0; S0 = 1;
#1 $display("S1 = %b, S0 = %b, OUTPUT
= %b \n", S1, S0, OUTPUT);

// choose IN2
S1 = 1; S0 = 0;
#1 $display("S1 = %b, S0 = %b, OUTPUT
= %b \n", S1, S0, OUTPUT);

// choose IN3
S1 = 1; S0 = 1;
#1 $display("S1 = %b, S0 = %b, OUTPUT
= %b \n", S1, S0, OUTPUT);
End

endmodule
The output of the simulation is shown below.

IN0= 1, IN1= 0, IN2= 1, IN3= 0

S1=0, S0=0, OUTPUT=1

S1=0, S0=1, OUTPUT=0
S1=1, S0=0, OUTPUT=1
S1=1, S0=1, OUTPUT=0
 Example 2 : 4-bit Ripple Carry Full Adder

•we will implement a ripple carry adder.

•The basic building block is a 1-bit full adder.
•The mathematical equations for a 1-bit full
adder are shown below.

sum = (a xor b xor cin)

c_out = (a and b) xor ( cin and (a xor b))

1-bit Full Adder
 Verilog Description for 1-bit Full Adder
module fulladd(sum, c_out, a, b, c_in);
// I/O port declarations
output sum, c_out;
input a, b, c_in;
// Internal nets
wire s1, c1, s2;
xor (s1, a, b);
and (c1, a, b);
xor (sum, s1, c_in);
and (s2, s1, c_in);
xor (c_out, s2, c1);

endmodule
4-bit Ripple Carry Full Adder
 Verilog Description for 4-bit Ripple Carry Full Adder
// Define a 4-bit full adder
module fulladd4(sum, c_out, a, b, c_in);

// I/O port declarations

output [3:0] sum;
output c_out;
input[3:0] a, b;
input c_in;

// Internal nets
wire c1, c2, c3;

// Instantiate four 1-bit full adders

fulladd fa0(sum[0], c1, a[0], b[0], c_in);
fulladd fa1(sum[1], c2, a[1], b[1], c1);
fulladd fa2(sum[2], c3, a[2], b[2], c2);
fulladd fa3(sum[3], c_out, a[3], b[3],
c3);

endmodule
 Stimulus for 4-bit Ripple Carry Full Adder
// Define the stimulus (top level module)
module stimulus;

// Set up variables
reg [3:0] A, B;
reg C_IN;
wire [3:0] SUM;
wire C_OUT;

// Instantiate the 4-bit full adder. call it FA1_4

fulladd4 FA1_4(SUM, C_OUT, A, B, C_IN);

// Set up the monitoring for the signal values

initial
Begin
$monitor($time," A= %b, B=%b, C_IN= %b, ---
C_OUT= %b,
SUM= %b\n",A, B, C_IN,
C_OUT, SUM);
end
// Stimulate inputs
initial
Begin
A = 4'd0; B = 4'd0; C_IN =
1'b0;

#5 A = 4'd3; B = 4'd4;

#5 A = 4'd2; B = 4'd5;

#5 A = 4'd9; B = 4'd9;

#5 A = 4'd10; B = 4'd15;
#5 A = 4'd10; B = 4'd5; C_IN =
1'b1;
end

endmodule
 The output of the simulation is shown below.

0 A= 0000, B=0000, C_IN= 0, --- C_OUT= 0, SUM= 0000

5 A= 0011, B=0100, C_IN= 0, --- C_OUT= 0, SUM= 0111
10 A= 0010, B=0101, C_IN= 0, --- C_OUT= 0, SUM= 0111
15 A= 1001, B=1001, C_IN= 0, --- C_OUT= 1, SUM= 0010
20 A= 1010, B=1111, C_IN= 0, --- C_OUT= 1, SUM= 1001
25 A= 1010, B=0101, C_IN= 1,, C_OUT= 1, SUM= 0000
 Gate Delays
• Gate delays allow the Verilog user to specify delays through the logic
circuits.
• Pin-to-pin delays can also be specified in Verilog
Rise, Fall, and Turn-off Delays
• There are three types of delays from the inputs to the output of a primitive
gate.
Rise delay
• The rise delay is associated with a gate output transition to a 1 from
another value.
Fall delay
The fall delay is associated with a gate output transition to a 0 from another value

Turn-off delay
The turn-off delay is associated with a gate output transition to the high impedance
value (z) from another value.
 Types of Delay Specification
// Delay of delay_time for all transitions
and #(delay_time) a1(out, i1, i2);
EX:- and #(5) a1(out, i1, i2); //Delay of
5 for all
// Rise and Fall Delay Specification.
and #(rise_val, fall_val) a2(out, i1, i2);
Ex:- and #(4,6) a2(out, i1, i2); // Rise = 4,
Fall = 6

// Rise, Fall, and Turn-off Delay Specification

bufif0 #(rise_val, fall_val, turnoff_val) b1
(out, in,
control);

Ex:- bufif0 #(3,4,5) b1 (out, in, control); // Rise = 3,

Fall =
4,
Turn-off= 5
 Min/Typ/Max Values
•Min value
The min value is the minimum delay value that
the designer expects the gate to have.
•Typ val
The typ value is the typical delay value that the
designer expects the gate to have.
• Max value
The max value is the maximum delay value that the
designer expects the gate to have.
 Examples : Min, Max, and Typical Delay Values

//One delay
// if +mindelays, delay= 4
// if +typdelays, delay= 5
// if +maxdelays, delay= 6
and #(4:5:6) a1(out, i1, i2);
// Two delays
// if +mindelays, rise= 3, fall= 5,
turn-off = min(3,5)
// if +typdelays, rise= 4, fall= 6,
turn-off = min(4,6)
// if +maxdelays, rise= 5, fall= 7, turn-off =min(5,7)
and #(3:4:5, 5:6:7) a2(out, i1, i2);
// Three delays
// if +mindelays, rise= 2 fall= 3 turn-off = 4
// if +typdelays, rise= 3 fall= 4 turn-off = 5
// if +maxdelays, rise= 4 fall= 5 turn-off = 6
and #(2:3:4, 3:4:5, 4:5:6) a3(out, i1,i2);
Delay Example

Figure : Module D
 Verilog Definition for Module D with Delay

// Define a simple combination module called D

module D (out, a, b, c);
// I/O port declarations
output out;
input a,b,c;

// Internal nets
wire e;
// Instantiate primitive gates to build the circuit
and #(5) a1(e, a, b); //Delay of 5 on gate a1
or #(4) o1(out, e,c); //Delay of 4 on gate o1

endmodule
 Stimulus for Module D with Delay

// Stimulus (top-level module)

// Declare variables

// Instantiate the module D

// Stimulate the inputs. Finish the simulation at 40 time units.

#10 A= 1'b1; B= 1'b1; C= 1'b1;

#10 A= 1'b1; B= 1'b0; C= 1'b0;

endmodule
The waveforms from the simulation are shown

Figure : Waveforms for Delay Simulation

Thank you