U S N
Sub: Digital Design and Computer Organization
Sub code: BCS302
Sem:III
SI Questions
No
1 Demonstrate the validity of the following identities by means of truth tables:
DeMorgan’s theorem for three variables: ( x + y + z ) ′ = x ′ y ′ z ′ and ( xyz ) ′ = x ′ + y ′ + z ′
The distributive law: x + yz = ( x + y ) ( x + z )
The associative law: x + ( y + z ) = ( x + y ) + z
2 Simplify the following Boolean expressions to a minimum number of literals:
(x+y)′(x′+y′)′
a ′ bc + abc ′ + abc + a ′ bc ′
(x′+z′)(x+y′+z′)
wxy ′ z + w ′ xz + wxyz
3 Find the complement of the following expressions:
z + z ′ ( v ′ w + xy )
xy ′ + x ′ y
4 List the truth table of the function
F = xy + xy ′ + y ′ z
F = ac + b ′ c ′
5 Simplify the Boolean function using Kmap Method
F(x, y, z)=Σ(0, 2, 4, 5)
F (x, y, z)=Σ(0, 2, 4, 5, 6)
F(x, y, z)=Σ(1, 2, 3, 5, 6, 7)
F(x, y, z)=Σ(3, 4, 5, 6, 7)
F(x,y,z)=x′y′+yz+x′yz′
F(x, y, z)=x′yz+xy′z′+xy′z
F (w, x, y, z)=Σ(1, 4, 5, 6, 12, 14, 15)
F (w, x, y, z)=Σ(1, 3, 4, 5, 6, 7, 9, 11, 13, 15)
F(w, x, y, z)=Σ (0, 2, 4, 6, 8, 10, 11)
F(x, y, z)=Σ(1, 2, 3, 6, 7)
6 Simplify the following Boolean function F, together with the don’t-care conditions d, and then express the
simplified function in sum-of-minterms form:
F (x, y, z) = Σ(0, 1, 4, 5, 6) d(x, y, z)=Σ(2, 3, 7)
F (A, B, C, D)=Σ(5, 6, 7, 12, 14, 15,) d(A, B, C, D)=Σ(0, 6, 8
F (A, B, C, D)=Σ(0, 6, 8, 13, 14) d(A, B, C, D)=Σ(2, 4, 10)
F (A, B, C, D) =Σ(4, 12, 7, 2, 10) d(A, B, C, D)=Σ(3, 9, 11, 15)
F(w, x, y, z) =Σ(4, 5, 6, 7, 12) d(w, x, y, z)=Σ(0, 8, 13).
7 Find all the prime implicants, and essential for the following Boolean functions
F (A, B, C, D) = Σ(0, 2, 3, 5, 7, 8, 10, 11, 14, 15)
F (w, x, y, z) = Σ(0, 1, 2, 5, 7, 8, 10, 15)
F (A, B, C, D)=Σ(0, 2, 3, 5, 7, 8, 10, 11, 14, 15)
F (A, B, C, D)=Σ(0, 1, 3, 7, 8, 9, 10, 13, 15)
F (w, x, y, z)=Σ(0, 1, 2, 4, 5, 6, 7, 10, 15)
F (A, B, C, D)=Σ(2, 3, 4, 5, 6, 7, 9, 11, 12, 13)
F (w, x, y, z)=Σ(0, 1, 2, 5, 7, 8, 10, 15
8 Implement the Boolean function with NAND gates, and draw the logic diagram of the implementation
F (w, x, y, z)=Σ(0, 1, 2, 4, 5, 6, 7, 10, 15)
F (x, y, z) =Σ(0, 1, 3, 5, 6, 7)
F (x, y, z)=Σ(0, 2, 4, 5, 6)
9 Simplify the following functions, and implement them with
two level NOR gate circuits
F (w, x, y, z)=Σ(0, 3, 12, 15)
F=wx′+y′z′+w′yz′
10 Simplify the following Boolean functions:
F (w,x,y,z)=Σ(0, 1, 2, 5, 8, 10, 13)
F (A, B, C, D)=∏(1, 3, 6, 9, 11, 12, 14)
F (A, B, C, D)=∏(1, 3, 5, 7, 13, 15)
11 For the Logic diagram shown Write Verilog Code using Data Flow, Behavioral and Structural style.
12 For the logic diagram shown write the Verilog code considering the delays. Demonstrate with truth table,
test bench and timing diagrams
13 Using Verilog continuous assignments or VHDL signal assignments, write a description of the circuit
specifiedbythefollowing functions:
Out_1=(A+B′)C′(C+D)Out_2=(C′D+BCD+CD′)(A′+B)Out_2= (AB+C)D+B′C Write a testbench.
14 Define Half adder. Write the Truth table and logic diagram
15 For the Logic diagram shown Write Verilog Code using Data Flow, Behavioral and Structural style.
16 Implement Full Adder using two Half Adders
17 Design BCD to Excess 3 Code Converter using truth table and logic diagram
18 For the logic diagram shown write the Verilog code considering the delays. Demonstrate with truth table,
test bench and timing diagrams. Consider OR gate delay as 20ns and AND gate delay as 30ns
19 Define Full Adder. Write truth table and logic diagram with relevant expressions
20 Write VHDLusing structural modelling for the logic diagram given
