RollNo.

ANNA UNIVERSITY (UNIVERSITY D E P A R T M E N T S )

B . E . / B . T e c h / B. A r c h (Full T i m e ) - E N D S E M E S T E R EXAMINATIONS.

Information Technology
S e m e s t e r IV
IT5451 - C O M P U T E R A R C H I T E C T U R E
(Regulation 2019)

Time:3hrs Max.Marks: 100

001 Interpret assembly language instructions.

002 D e s i g n and a n a l y z e ALU c i r c u i t s .
003 Implement a c o n t r o l u n i t as per the functional specification.
C04 D e s i g n and a n a l y z e memory, I/O d e v i c e s and c a c h e s t r u c t u r e s for processor.
COS Evaluate the performance of computer systems.
C06 Point out the hazards present in a pipeline and s u g g e s t remedies.
B L - Bloom's Taxonomy Levels
( L i - R e m e m b e r i n g , L2-Understanding, L3-Applying, L4-Analysing, L5-Evaluating, L6-Creating)

P A R T - A (1Qx2=20Marks)
( A n s w e r all Q u e s t i o n s )

Q. No. Questions Marks CO BL

1 Define Amdahl's law. 2 C01 LI

2 What are the differences behween C I S C & R I S C p r o c e s s o r s ? 2 CGI L2

3 Design 4-bit combinational circuit using 4 full adders. 2 C02 L6

4 What is the difference between the restoring and non restoring 2 C02 L2
method of division?
S Why is the Wait-for-Memory-Function-Completed step needed 2 C03 L4
when reading from or writing to the main memory?

6 How bit-ORing technique u s e d in Microprogram s e q u e n c i n g ? 2 C03 L4

7 What is S R A M and D R A M ? 2 C04 LI

8 What is interrupt handler? List out the types of interrupts. 2 C04 LI

9 Classify Parallel Computers. 2 COS LI

10 What are the properties of Multi- C o r e s y s t e m s ? 2 COS L2

PART-R(5x13=65Marks)
(Restrict to a maximum of 2 subdivisions)

Q. No. Questions Marks CO BL

11 (a) Explain the basic operstional concepts and list the steps needed 9 C01 L3
to execute the machine instruction.
Add L O C A , RO
 S u p p o s e we have two implementation of the s a m e instruction set 4 COT L5
architecture. Machine "A" h a s a clock cycle time of I n s and a C P I
of 2.0 for s o m e program, and machine "B" h a s a clock cycle time
of 2 n s and a C P I of 1.2 for the s a m e program. Which machine is
faster for this program and by how m u c h ?
OR
11 (b) List out u s a g e of addressing modes and explain its types. 9 C01 L3 .
Explain Zero, one, two and three addressing instructions with 4 001 L5
example.

12(a) State the principle of carry look a h e a d adder. 9 002 LI

Consider the binary numbers to be signed, 6-bit values in the 2's 4 002 L3
complement representation. Perform addition and subtraction,
specify whether or not arithmetic overflow occurs. Also convert
the operands and results to decimal sign- and-magnitude .
representation.

100001 II ijj
011101 ^

OR
12(b) Explain the logic circuit arrangement to perform Restonng division 9 C02 LI
and state how it c a n be improved for Non - restoring division
technique.
Solve the following multiplication using Booth's multiplication 4 C02 L3
algorithm. A= 11011 B = 00111

Multiply the following pair of signed 2's complement numbers

using bit-pair receding of the multipliers: A = 1 1 0 1 0 1 , B = 0 1 1 0 1 1 .

13(a) Write the control s e q u e n c e for the following instruction 9 003 L3

considering a single bus organization of the C P U

S U B (R3), R 2

where R 3 is source register and R 2 is destination register.

Draw and explain the Microprogrammed control unit. 4 C06 L2
OR
13(b) Explain the instruction execution and hardware organization of a 9 C03 L3
4-Stage pipeline.

What are the three types of hazards that c a u s e performance 4 006 L2

degradation in pipelined p r o c e s s o r s ? Explain them in detail.

14(a) What is virtual memory concept? Explain the role of T L B in 9 C04 L2

virtual memory organization.

Explain associative and set - associative mapping in c a c h e 4 C04 L2

memory.
OR
14(b) Explain with the block diagram the DMA transfer in a computer 9 C04 L2
system.
List the functions of I/O interface. 4 C04 L2
15(a) Explain the three parts of scoreboard algorithm and how it works 13 005 L3
for the below set of instructions.
L D F 6 , 34 (R2)
L D F 2 , 45 (R3)
M U L T FO, F 2 ,F4
S U B D F 8 , F6, F 2
D l V D F 1 0 , FO, F 6
A D D D F6, F8, F2

OR
15(b) Consider the following instructions: 13 005 L3

L D F 6 , 34 (R2)
L D F 2 , 4 5 (R3)
M U L T FO, F 2 , F 4
S U B D F8, F6, F 2
D l V D F 1 0 , FO, F 6
A D D D F6, F8, F2

Explain what happens in T o m a s u l o ' s algorithm for atleast 5

cycles.

PART-C(1x15=15Marks)
( Q . N o . 1 6 is c o m p u l s o r y )

Q. No. Questions Marks CO BL

16. Consider the following s e q u e n c e of instructions 9 C06 L5

Add#20,R0,R1

Mul#3,R2,R3

Add # 3 , R 1 , R 4

Add R 0 , R 2 , R 5

In all instructions, the destination operand is given last. Initially,

registers RO and R 2 contain 2500 and 100, respectively. T h e s e

instructions are executed in a computer that h a s a four-stage

pipeline. A s s u m e that the first instruction is fetched in clock cycle

1, and that instruction fetch requires only one clock cycle.

i 1
SyJ

Draw the pipeline stages to describe the operation.

Give the contents of the interstage buffers B 1 , B 2 and B 3 during

clock cycles 2 to 5.

Explain in detail the working of a micro programmed control unit 6 COS L3

to implement the general instruction A D D src,dst in which the
source operand c a n be in any of the five a d d r e s s modes.