SINGLE STAGE AMPLIFIER

B A S I C C O N C E P T S , C O M M O N S O U R C E S TA G E , S O U R C E
F O L L O W E R , C O M M O N G AT E S TA G E , C A S C O D E S TA G E

Rekha S S, Assistant Professor, Dept. of ECE 9/11/2024

 Ideal vs Non-ideal Amplifier
2

➢The input and output characteristics of an

amplifier is generally a nonlinear function as
shown in fig.(Nonlinear amplifier)

➢Input and output may be current or voltage

quantities
➢For an ideal amplifier

Rekha S S, Assistant Professor, Dept. of ECE 9/11/2024

 3

 α0 is the “dc bias”(operating point)

 α1 is the “small signal gain”
 As long as α1x(t) << α0 , the bias point is disturbed
negligibly and higher order terms are insignificant.

 y = α1 x, indicating a linear relationship between the

increments at the input and output.
 As x(t) increases in magnitude, higher order terms
manifest themselves. Leading to nonlinearity and
necessitating large signal analysis.
 Causes distortion of signal of interest

Rekha S S, Assistant Professor, Dept. of ECE 9/11/2024

 Analog Design Trade off
(What aspects of the performance of an amplifier are important?)
4
Analog design trade-off:
 While digital circuits entail primarily one trade-off between speed and power
dissipation.
 Analog circuit design must deal with a Multi-dimensional trade-off consisting like
speed, power dissipation, gain, supply voltage, etc.
 Along with gain and speed, other parameters ( like power dissipation,
supply voltage, linearity, noise, gain, voltage swing, speed and
input/output impedance ) are also important for amplifier performance,
as illustrated by the "analog design octagon"
Analog-Design Octagon

Such trade-offs present many challenges

in the design of high-performance
amplifiers, requiring intuition and
experience to arrive at an acceptable
compromise

Rekha S S, Assistant Professor, Dept. of ECE 9/11/2024

 Common-Source stage with Resistive load
5
 By virtue of MOSFET’s transconductance,, a MOSFET changes in its gate-
source voltage to a small-signal drain current, which can pass through a
resistor to generate an output voltage

Rekha S S, Assistant Professor, Dept. of ECE 9/11/2024

 Common-Source stage with Resistive load
6
 For Vin < VTH,
M1is off

 and Vout = VDD
 When Vin is slightly greater then Vth,
 M1is ON and operates in saturation
 If Vin is increased in small amount, there will be large amount
of Vout decreases
➢ As Vin approaches Vth, M1 begins to turn on, drawing current
from Rd and lowering Vout.
➢ M1 turns ON in saturation regardless
of the Values of Vdd and Rd.
𝑉𝑜𝑢𝑡 = 𝑉𝑑𝑑 − 𝐼𝑑𝑅𝑑

Rekha S S, Assistant Professor, Dept. of ECE 9/11/2024

 Common-Source stage with Resistive load
7
 Further increase in Vin, Vout drops more and the transistor continues
to operates in saturation until Vin exceeds Vout by Vth.
 At point A Vout = Vin1 -Vth
 When Vin > Vin1
 M1is ON and operates in Linear / Triode
 Vout decreases

 When Vin is high enough →

Rekha S S, Assistant Professor, Dept. of ECE 9/11/2024

 Common-Source stage with Resistive load
8

 When Vin is high enough →

M1 drive into deep triode region, Vout << 2(vgs-Vth)
and the equivalent circuit is

Rekha S S, Assistant Professor, Dept. of ECE 9/11/2024

 Common-Source stage with Resistive load
9

 Taking derivative of ID equation in saturation region,

small-signal gain is obtained

Using equation (1)

Rekha S S, Assistant Professor, Dept. of ECE 9/11/2024

 Common-Source stage with Resistive load
10

 Same result is obtained from small-signal equivalent circuit

Rekha S S, Assistant Professor, Dept. of ECE 9/11/2024

 Common-Source stage with Resistive load
11

 Since gm itself varies with the input signal according to

the gain of the circuit changes substantially if the signal is large.
 The dependence of the gain upon the signal level leads to
nonlinearity usually an undesirable effect.
 A key result here is that to minimize
 the nonlinearity,
 the gain equation must be a weak function of signal dependent parameters such
as gm.
 For a good stability, gm should not change
 Input impedance of the circuit is very high at a low frequencies.

Rekha S S, Assistant Professor, Dept. of ECE 9/11/2024

 Common-Source stage with Resistive load
12
 How do we maximize the voltage gain of a common source stage?

 Thus, the magnitude of Av can be increased by increasing W/L or VRD or

decreasing ID if other parameters are constant.
 It is important to understand the trade-offs resulting from this equation.
 A larger device size leads to greater device capacitances, and
 A higher VRD limits the maximum voltage swings
 For example, if VDD−VRD = Vin−VTH,
 then M1is at the edge of the triode region, allowing only very small swings at the output (and
input).
 If VRD remains constant and ID is reduced, then RD must increase, thereby
leading to a greater time constant at the output node.
 In other words, as noted in the analog design octagon, the circuit exhibits
trade-offs between gain, bandwidth, and voltage swings.
 Lower supply voltages further tighten these trade-offs

Rekha S S, Assistant Professor, Dept. of ECE 9/11/2024

 Common-Source stage with Resistive load
13
Cut-off Saturation Triode / Linear

Vin < Vth Vin1>Vin > Vth Vin>Vin1

ID = 0

Rekha S S, Assistant Professor, Dept. of ECE 9/11/2024

 Common-Source stage with Resistive load
14
P 1. Sketch the drain current and transconductance of M1in below Fig. as a
function of the input voltage

Rekha S S, Assistant Professor, Dept. of ECE 9/11/2024

 Common-Source stage with Resistive load
15

 For large values of RD, the effect of channel-length modulation in

M1 becomes significant

Rekha S S, Assistant Professor, Dept. of ECE 9/11/2024

 Common-Source stage with Resistive load
16
 Small signal analysis

Rekha S S, Assistant Professor, Dept. of ECE 9/11/2024

 Common-Source stage with Resistive load
17
 For large values of RD, the effect of channel-length modulation in M1becomes
significant

Rekha S S, Assistant Professor, Dept. of ECE 9/11/2024

 Common-Source stage with Resistive load
18
P3. Assuming thatM1in Fig. is biased in saturation, calculate the small-
signal voltage gain of the circuit.
➢ # Since I1 introduces an infinite impedance (RD=∞),
 # the gain is limited by the output resistance of M1

 Called the “intrinsic gain” of a transistor,

this quantity represents the maximum voltage gain
that can be achieved using a single device
 In today’s CMOS technology, gm rO of short-channel devices is between
roughly 5 and 10. We usually assume (1/gm)<< r𝒐

Rekha S S, Assistant Professor, Dept. of ECE 9/11/2024

 Common-Source stage with Resistive load
19
P3. Assuming thatM1in Fig. is biased in saturation, calculate the small-
signal voltage gain of the circuit.
➢ By applying KCL @ Vout node


 Vin appears in the square term and Vout in the linear term.
As Vin increases, Vout must decrease such that the product
remains constant

Rekha S S, Assistant Professor, Dept. of ECE 9/11/2024

 Common-Source stage with Resistive load
20
P4. It is possible to use the bulk (back gate) of a MOSFET as the terminal
controlling the channel. Shown in Fig. Determine the voltage gain if λ=0.

The drain current is given by gmbVin

Thus, Av = − gmb RD.

Rekha S S, Assistant Professor, Dept. of ECE 9/11/2024

 Common-Source stage with
Diode Connected Load
21
MOS as Diode
 When a gate of MOSFET is connected to the drain, it acts like a diode
with characteristics similar to a pn-junction diode.

Rekha S S, Assistant Professor, Dept. of ECE 9/11/2024

 Common-Source stage with
Diode Connected Load
22
MOS as Diode
 When a gate of MOSFET is connected to the drain, it acts like a diode
with characteristics similar to a pn-junction diode.

 When the gate is connected to the drain of an enhancement MOSFET, the

MOSFET is always in the saturation region.

Rekha S S, Assistant Professor, Dept. of ECE 9/11/2024

 Common-Source stage with
Diode Connected Load
23
 In many CMOS technologies, it is difficult to fabricate resistors because it
requires large area on a silicon wafer.
 A MOSFET can operate as a small-signal resistor if its gate and drain are
shorted as shown in fig below
 Called a “Diode connected “ device in analogy with its bipolar
counterpart, this configuration exhibits a small-signal behavior to a two-
terminal resistor.

 Transistor always operates in saturation because the drain and the gate
have the same potential.

Rekha S S, Assistant Professor, Dept. of ECE 9/11/2024

 Common-Source stage with
Diode Connected Load
24

 The voltage gain of CS stage with diode connected (without body effect)
load is

Rekha S S, Assistant Professor, Dept. of ECE 9/11/2024

 Common-Source stage with
Diode Connected Load
25

 Av is lower, but it is less dependent on process parameters

 If body effect exists, then the circuit arrangement for measuring
equivalent resistance of diode-connected MOSFET with body effect is

Rekha S S, Assistant Professor, Dept. of ECE 9/11/2024

 Common-Source stage with
Diode Connected Load
26

Rekha S S, Assistant Professor, Dept. of ECE 9/11/2024

 Common-Source stage with
Diode Connected Load
27

Rekha S S, Assistant Professor, Dept. of ECE 9/11/2024

 Common-Source stage with
Diode Connected Load
28

Input and output characteristics

of nMOS diode connected load

Rekha S S, Assistant Professor, Dept. of ECE 9/11/2024

 Common-Source stage with
Diode Connected Load
29
 The linear behavior of the circuit (nMOS diode connected load) can
also be confirmed by large-signal analysis. Neglecting channel length
modulation for simplicity,
 Current through driver = current through load

 By diff. w.r.t to vin

Rekha S S, Assistant Professor, Dept. of ECE 9/11/2024

 Common-Source stage with
Diode Connected Load
30

Rekha S S, Assistant Professor, Dept. of ECE 9/11/2024

 Common-Source stage with
Diode Connected Load
31

Rekha S S, Assistant Professor, Dept. of ECE 9/11/2024

 Common-Source stage with
Diode Connected Load
32

Rekha S S, Assistant Professor, Dept. of ECE 9/11/2024

 Common-Source stage with
Diode Connected Load
33
 pMOS Diode connected load

 This implies, a high gain requires a strong input device and a weak load
device
 A high gain translates to another important limitation: reduction in
allowable voltage swings
Rekha S S, Assistant Professor, Dept. of ECE 9/11/2024
 Common-Source stage with
Diode Connected Load
34
 pMOS Diode connected load

 ID1 = |ID2|,

 The overdrive voltage of M2 must be gain times that of M1

 The swing is constrained by both the required overdrive voltage and the
threshold voltage. Even with a small overdrive, output level cannot exceed
VDD- |Vth|
 Severely limiting the output swing
 This is example of that trade-off suggested by the analog design
octagon.

Rekha S S, Assistant Professor, Dept. of ECE 9/11/2024

 Common-Source stage with
Diode Connected Load
35

Rekha S S, Assistant Professor, Dept. of ECE 9/11/2024

 CS stage with Source Degeneration
36

 In some applications, the square-law dependence of drain current upon

the overdrive voltage introduces excessive nonlinearity making it
desirable to “soften” the device characteristic
 Source Degeneration can be accomplished by placing a “degeneration”
resistor in series with the source terminal.

Rekha S S, Assistant Professor, Dept. of ECE 9/11/2024

 CS stage with Source Degeneration
37

 As Vin increases, so do Id and the voltage drop across Rs.

 That a, fraction of the Vin appears across the resistor
rather than as the gate source overdrive, thus loading
to a smoother variation of ID
 Intend to make the gain equation a weak function
of gm

The equivalent transconductance of the circuit is Gm

Rekha S S, Assistant Professor, Dept. of ECE 9/11/2024

 CS stage with Source Degeneration
38
The equivalent transconductance of the circuit is Gm

Rekha S S, Assistant Professor, Dept. of ECE 9/11/2024

 CS stage with Source Degeneration
39
 Gain using small-signal approach

Rekha S S, Assistant Professor, Dept. of ECE 9/11/2024

 CS stage with Source Degeneration
40
 The equivalent transconductance of the circuit Gm with body effect and
channel length modulation.

Rekha S S, Assistant Professor, Dept. of ECE 9/11/2024

 CS stage with Source Degeneration
41
 The equivalent transconductance of the circuit Gm with body effect and
channel length modulation.

Rekha S S, Assistant Professor, Dept. of ECE 9/11/2024

 CS stage with Source Degeneration
42
 Gain expression of source degeneration can be rewritten

 From the denominator of the above equation, it is understood that the

series combination of the inverse transconductance of the device and the
explicit resistance seen from the source to ground.
 If the bottom terminal is disconnected from the ground and calculate the
resistance seen “looking up” we obtain Rs + 1/gm
 Numerator is the resistance seen at the drain
 The magnitude of the gain as the resistance seen
at the drain node divided by the total resistance
in the source path.

Rekha S S, Assistant Professor, Dept. of ECE 9/11/2024

 CS stage with Source Degeneration
43
 Assuming λ = γ = 0, calculate the small-signal gain of the circuit shown
in

Rekha S S, Assistant Professor, Dept. of ECE 9/11/2024

 CS stage with Source Degeneration
44
 Drain current and transconductance of a CS device (a) without and (b)
with source degeneration.

Rekha S S, Assistant Professor, Dept. of ECE 9/11/2024

 CS stage with Source Degeneration
45
 Output Resistance of a Degenerated CS stage

Equivalent circuit for calculating the output

resistance of a degenerated CS stage(body
effect also included)

Rekha S S, Assistant Professor, Dept. of ECE 9/11/2024

 CS stage with Source Degeneration
46
Small-signal model of degenerated CS stage with finite output
resistance.

Rekha S S, Assistant Professor, Dept. of ECE 9/11/2024

 Source Follower
47
 The common drain or source follower circuit is able to
provide a very high input impedance and low output
impedance and is used to act as a buffer amplifier.

 In common source stage, a high voltage gain is achieved with

limited supply voltage and the load impedance (RD) must be
as large as possible.

 If such a stage is used to drive a low-impedance load, there

may be a loading effect.
 Hence a buffer must be placed after the amplifier as to drive
the load with negligible loss of the signal level.

Rekha S S, Assistant Professor, Dept. of ECE 9/11/2024

 Source Follower
48
 The source follower can operate as a voltage buffer. Buffer
avoid loading effect.
 The source follower sense the signal at gate and drives the
load at the source, allowing the source potential to follow the
gate voltage.

input-output characteristic
Source follower
example of its role as a buffer

Rekha S S, Assistant Professor, Dept. of ECE 9/11/2024

 Source Follower
49
 Large Signal Behavior

 When Vin < Vth, M1 is off and Vout = 0

 As Vin increases Vin > Vth, M1 is ON and operates in
saturation
 ID flows thro’ Rs, Vout = ID RS

 Diff. w.r.t to Vin

Rekha S S, Assistant Professor, Dept. of ECE 9/11/2024

 Source Follower
50
 Large Signal Behavior

Rekha S S, Assistant Professor, Dept. of ECE 9/11/2024

 Source Follower
51
 Small Signal Behavior

Rekha S S, Assistant Professor, Dept. of ECE 9/11/2024

 Source Follower
52
 Voltage gain of source follower versus input voltage.

 the voltage gain begins from zero for Vin ≈ Vth (that is, gm ≈ 0) and
monotonically increases.
 As the drain current and gm increase, Av approaches
gm/(gm+gmb) = 1/(1+η).
 Since η itself slowly decreases with Vout , Av would eventually become
equal to unity, but for typical allowable source-bulk voltages, η remains
greater than roughly 0.2.

Rekha S S, Assistant Professor, Dept. of ECE 9/11/2024

 Source Follower
53
 From voltage gain of source follower

 Even if RS =∞,
 The voltage gain of a source follower is not equal
to unity (unless body effect is removed as explained later).
 M1 in Fig. remains in saturation if Vin does not
exceed VDD + VT H.

Rekha S S, Assistant Professor, Dept. of ECE 9/11/2024

 Source Follower
54
 The drain current of M1 heavily depends on the input dc level.
For example, if Vin changes from 0.7 V to 1V, ID may increase by a factor
of 2, and hence VGS − VTH by √2
 To alleviate this issue, the resistor can be replaced by a constant current
source as shown in Fig.

 Even if VTH is relatively constant, the increase in VGS

means that Vout (= Vin − VGS) does not follow Vin faithfully,
thereby incurring nonlinearity.
 The current source itself is implemented as an
NMOS transistor operating in the saturation
region

Rekha S S, Assistant Professor, Dept. of ECE 9/11/2024

 Source Follower
55
 Calculation of the output impedance of a source follower

Rekha S S, Assistant Professor, Dept. of ECE 9/11/2024

 Source Follower
56
 Calculation of the output impedance of a source follower

 Body effect decreases the output resistance of source follower.

 Vx decreases by V, so the drain current increases.
 With no body effect, only the gate-source voltage of M1 would increase
by V.
 With body effect, the threshold voltage of the device also decreases
 Thus, in (Vgs-Vth)2 ----- Vgs and Vth . Resulting in a greater change
in the drain current and hence a lower output resistance /impedance.

Rekha S S, Assistant Professor, Dept. of ECE 9/11/2024

 Common Gate Stage
57
 A common-gate (CG) stage senses the input at the source and produces
the output at the drain.
 The gate is connected to a dc voltage to establish proper operating
conditions.

Common-gate stage with CG stage with capacitive

direct coupling at input coupling at input.

 Note that the bias current of M1 flows through the input signal source
 M1 can also be biased by a constant current source, with the signal
capacitive coupled to the circuit.
Rekha S S, Assistant Professor, Dept. of ECE 9/11/2024
 Common Gate Stage
58

Rekha S S, Assistant Professor, Dept. of ECE 9/11/2024

 Common Gate Stage
59

Input-output
characteristics

Rekha S S, Assistant Professor, Dept. of ECE 9/11/2024

 Common Gate Stage
60
 Large signal behavior

➢ For Vin ≥ Vb – Vth

M1 is OFF and Vout = Vdd

➢ For Vin  Vb – Vth

M1 is ON and it will be saturation
Vout = VDD – IDRD

The small signal gain

Rekha S S, Assistant Professor, Dept. of ECE 9/11/2024

 Common Gate Stage
61
 Small signal Analysis

Rekha S S, Assistant Professor, Dept. of ECE 9/11/2024

 Common Gate Stage
62

Rekha S S, Assistant Professor, Dept. of ECE 9/11/2024

 Common Gate Stage
63

• Gain of the common-gate (CG) stage is positive

• Body effect increases the effective transconductance of the stage

• For a given bias current and supply voltage (i.e., a given power budget),
voltage gain of the CG stage can be maximized by – Increasing gm and
Increasing RD

• The minimum allowable value of Vout is VGS-VTH+VI1, where VI1

denotes the minimum voltage required by I

Rekha S S, Assistant Professor, Dept. of ECE 9/11/2024

 Common Gate Stage
64

 With  = 0, the impedance seen at the source of M1 is same as that of

impedance seen at the source of M1 of source follower. Here it is input
impedance and in source follower it is output impedance.

 Thus body effect decreases the input impedance of the CG stage.

Rekha S S, Assistant Professor, Dept. of ECE 9/11/2024

 Common Gate Stage
65
Output Impedance
From the small-signal equivalent circuit,
we can find the output impedance as

• Result is similar to that obtained for a

degenerated CS stage.

Rekha S S, Assistant Professor, Dept. of ECE 9/11/2024

 Cascode Stage
66
 The input signal of a common gate stage may be a current
 A transistor in a common-source arrangement converts a voltage signal
to a current signal
 The cascade of a CS stage and CG stage is called a “Cascode” topology
providing many useful properties.
 Fig below shows the basic configuration: M1 generates a small signal
drain current proportional to Vin and M2 simply routes the current to
RD.
 M1 is called the input device and M2 the
cascode device
 M1 and M2 in this example carry equal
bias and signal currents
– Topology also called as “telescopic cascode”

Rekha S S, Assistant Professor, Dept. of ECE 9/11/2024

 Cascode Stage : Qualitative Analysis
67
 Assume both transistors are in saturation and λ = γ = 0
 If Vin rises by ΔV, then ID1 increases by gm1ΔV
 This change in current flows through the impedance seen at X, i.e., the
impedance seen at the source of M2 , which is equal to 1/gm2
 Thus, VX falls by an amount given by gm1ΔV∙(1/gm2)
 This change in ID1 also flows through RD , producing a drop of gm1ΔVRD
in Vout, just as in a simple CS stage

Rekha S S, Assistant Professor, Dept. of ECE 9/11/2024

 Cascode Stage : Qualitative Analysis
68
 Consider the case when Vin is fixed and Vb increases by ΔV
 Since VGS1 is constant and rO1=∞, M1 can be replaced by an ideal
current source
 For node X, M2 operates as a source follower, it senses an input ΔV at
its gate and generates an output at X
 With λ = γ = 0, the small-signal voltage of the follower is unity
regardless of RD
 VX rises by ΔV, but Vout does not change
since ID2=ID1=constant,
thus voltage gain from Vb to Vout is zero

Rekha S S, Assistant Professor, Dept. of ECE 9/11/2024

 Cascode Stage
69

Rekha S S, Assistant Professor, Dept. of ECE 9/11/2024

 Cascode Stage
70

Rekha S S, Assistant Professor, Dept. of ECE 9/11/2024

 Cascode Stage
71

Rekha S S, Assistant Professor, Dept. of ECE 9/11/2024

 Cascode Stage
72
 Large Signal Behavior

Rekha S S, Assistant Professor, Dept. of ECE 9/11/2024

 Cascode Stage
73
 Large Signal Behavior

Rekha S S, Assistant Professor, Dept. of ECE 9/11/2024

 Cascode Stage
74
 Small-Signal equivalent circuit of Cascode stage

Rekha S S, Assistant Professor, Dept. of ECE 9/11/2024

 Cascode Stage
75
 Calculate the voltage gain of the circuit shown in Fig, if λ = 0.
The small-signal drain current of M1,
gm1Vin, is divided between RP and
the impedance seen looking into the
source of M2, 1/(gm2 + gmb2).

 Thus, the current flowing through M2 is

The voltage gain is therefore given by

Rekha S S, Assistant Professor, Dept. of ECE 9/11/2024

 Shielding Property
76
 If the output-node voltage is changed by V, the resulting change at the
source of the cascode device is much less. In a sense, the cascode
transistor “shields” the input device from voltage variations at the
output. The shielding property of cascodes proves useful in many
circuits.

Rekha S S, Assistant Professor, Dept. of ECE 9/11/2024

 Frequency Response of Amplifier

77

Rekha S S, Assistant Professor, Dept. of ECE Odd-22 [Aug - Dec 2022]

 Miller Effect
78

Miller Effect
➢ MOS device exhibits four capacitances: CGS, CGD, CDB, and CSB.

➢ The transfer function of CMOS circuits is simplified using one of the two

approximations –Miller’s theorem and association of poles with nodes.

➢ The frequency response of an amplifier refers to the band of frequencies or

frequency range that the amplifier designed to amplify

➢ Figure magnitude responses of low pass, high pass and band pass circuit.

Rekha S S, Assistant Professor, Dept. of ECE Odd-22 [Aug - Dec 2022]

 Miller Effect
79

In general for any transfer function H( jω)

(1) The magnitude of a complex number a + jb is given by √a2 + b2.

(2) Zeros and poles are respectively defined as the roots of the numerator
and denominator of the transfer function.

(3) According to Bode’s approximations, the slope of the magnitude of a

transfer function decreases by 20 dB/decade as ω passes a pole
frequency and increase by 20 dB/decade as ω passes a zero frequency.

Rekha S S, Assistant Professor, Dept. of ECE Odd-22 [Aug - Dec 2022]

 Miller Effect
80

“Design of Analog CMOS Integrated Circuits” Second Edition Behzad Razavi

Rekha S S, Assistant Professor, Dept. of ECE Odd-22 [Aug - Dec 2022]
 Miller Effect
81

“Design of Analog CMOS Integrated Circuits” Second Edition Behzad Razavi

Rekha S S, Assistant Professor, Dept. of ECE Odd-22 [Aug - Dec 2022]
 Miller Effect
82

“Design of Analog CMOS Integrated Circuits” Second Edition Behzad Razavi

Rekha S S, Assistant Professor, Dept. of ECE Odd-22 [Aug - Dec 2022]
 Miller Effect
83

“Design of Analog CMOS Integrated Circuits” Second Edition Behzad Razavi

Rekha S S, Assistant Professor, Dept. of ECE Odd-22 [Aug - Dec 2022]
 Miller Effect
84

“Design of Analog CMOS Integrated Circuits” Second Edition Behzad Razavi

Rekha S S, Assistant Professor, Dept. of ECE Odd-22 [Aug - Dec 2022]
 Miller Effect
85

 Calculate the input resistance of the circuit shown in Fig. 6.7(a). Reference

Solution ✓ the voltage gain from X to Y is equal to 1 + (gm + gmb)rO

✓ the input resistance is given by the parallel combination of rO /(1 − Av) and
1/(gm + gmb).
✓ Since Av is usually greater than unity, rO /(1 − Av) is a negative
resistance.

“Design of Analog CMOS Integrated Circuits” Second Edition Behzad Razavi

Rekha S S, Assistant Professor, Dept. of ECE Odd-22 [Aug - Dec 2022]
 Miller Effect
86

 Association of Poles with Nodes

 The circuit exhibits three poles, each of which is determined by the total
capacitance seen from each node to ground multiplied by the total
resistance seen at the node to ground.
 We can therefore associate each pole with one node of the circuit, i.e.,
ωj = τ −1 j , where τ j is the product of the capacitance and resistance seen
at node j to ground.
 From this perspective, we may say that “each node in the circuit
contributes one pole to the transfer function.”
“Design of Analog CMOS Integrated Circuits” Second Edition Behzad Razavi
Rekha S S, Assistant Professor, Dept. of ECE Odd-22 [Aug - Dec 2022]
 Frequency Response of Common-Source Stage
87

➢ The common-source stage driven by a finite source resistance, RS as

shown in Figure.
➢ CGS and CDB are “grounded” capacitances
➢ CGD appears between the input and the output.
➢ In reality, the circuit also drives a load capacitance, which can be
merged with CDB.

“Design of Analog CMOS Integrated Circuits” Second Edition Behzad Razavi

Rekha S S, Assistant Professor, Dept. of ECE Odd-22 [Aug - Dec 2022]
 Frequency Response of Common-Source Stage – Miller effect
(Using Association of poles with nodes – Approximation method)
88

“Design of Analog CMOS Integrated Circuits” Second Edition Behzad Razavi

Rekha S S, Assistant Professor, Dept. of ECE Odd-22 [Aug - Dec 2022]
 Frequency Response of Common-Source Stage - Miller effect
(Using Association of poles with nodes – Approximation method)
89

“Design of Analog CMOS Integrated Circuits” Second Edition Behzad Razavi

Rekha S S, Assistant Professor, Dept. of ECE Odd-22 [Aug - Dec 2022]
Frequency Response of Common-Source Stage - Miller effect
(Using Association of poles with nodes – Approximation method)
90

“Design of Analog CMOS Integrated Circuits” Second Edition Behzad Razavi

Rekha S S, Assistant Professor, Dept. of ECE Odd-22 [Aug - Dec 2022]
Frequency Response of Common-Source Stage - Miller effect
(Using Association of poles with nodes – Approximation method)
91

“Design of Analog CMOS Integrated Circuits” Second Edition Behzad Razavi

Rekha S S, Assistant Professor, Dept. of ECE Odd-22 [Aug - Dec 2022]
 Frequency Response of Common-Source Stage
(Using Direct Analysis)
92

“Design of Analog CMOS Integrated Circuits” Second Edition Behzad Razavi

Rekha S S, Assistant Professor, Dept. of ECE Odd-22 [Aug - Dec 2022]
 Frequency Response of Common-Source Stage
(Using Direct Analysis)
93

“Design of Analog CMOS Integrated Circuits” Second Edition Behzad Razavi

Rekha S S, Assistant Professor, Dept. of ECE Odd-22 [Aug - Dec 2022]
 Frequency Response of Common-Source Stage
(Using Direct Analysis)
94

“Design of Analog CMOS Integrated Circuits” Second Edition Behzad Razavi

Rekha S S, Assistant Professor, Dept. of ECE Odd-22 [Aug - Dec 2022]
 Frequency Response of Common-Source Stage
(Using Direct Analysis)
95

“Design of Analog CMOS Integrated Circuits” Second Edition Behzad Razavi

Rekha S S, Assistant Professor, Dept. of ECE Odd-22 [Aug - Dec 2022]
 Frequency Response of Common-Source Stage
(Using Direct Analysis)
96

Rekha S S, Assistant Professor, Dept. of ECE Odd-22 [Aug - Dec 2022]

 Miller Effect
97

 Conclusion about Miller’s Theorem :

 Miller’s approximation divides a floating impedance by the low-

frequency gain and faces

 the following limitations:

 (1) It may eliminate zeros,

 (2) It may predict additional poles,

 (3) It does not correctly compute the “output” impedance.

“Design of Analog CMOS Integrated Circuits” Second Edition Behzad Razavi

Rekha S S, Assistant Professor, Dept. of ECE Odd-22 [Aug - Dec 2022]
 Miller Effect
98

 Miller’s approximation
➢ The value of Av = VY / VX must be calculated at the frequency of interest.
➢ Assume an amplifier with a finite output resistance as shown in Figure
➢ The equivalent circuit reveals that VY ≠ −AvVX at high frequencies, and
hence CF cannot be simply multiplied by (1+A) to yield the input capacitance.
➢ However, in many cases we use the low-frequency value of VY /VX to gain
insight into the behavior of the circuit. We call this approach “Miller’s
approximation.”

“Design of Analog CMOS Integrated Circuits” Second Edition Behzad Razavi

Rekha S S, Assistant Professor, Dept. of ECE Odd-22 [Aug - Dec 2022]
 Frequency analysis
99

“Design of Analog CMOS Integrated Circuits” Second Edition Behzad Razavi

Rekha S S, Assistant Professor, Dept. of ECE Odd-22 [Aug - Dec 2022]
 Frequency analysis – Direct Analysis
100

“Design of Analog CMOS Integrated Circuits” Second Edition Behzad Razavi

Rekha S S, Assistant Professor, Dept. of ECE Odd-22 [Aug - Dec 2022]
 Frequency analysis – Direct Analysis
101

“Design of Analog CMOS Integrated Circuits” Second Edition Behzad Razavi

Rekha S S, Assistant Professor, Dept. of ECE Odd-22 [Aug - Dec 2022]
 Frequency analysis – using approximation method
102

➢ Miller’s approximation has eliminated the zero and predicted two

poles for the circuit!
➢ Despite these shortcomings, Miller’s approximation can
provide intuition in many cases.

“Design of Analog CMOS Integrated Circuits” Second Edition Behzad Razavi

Rekha S S, Assistant Professor, Dept. of ECE Odd-22 [Aug - Dec 2022]