ACPL-M483-000E ACPL-W483-500E ACPL-W483-000E ACPL-W483-500E ACPL-M483-000E

ACPL-P483-000E
ACPL-M483/P483/W483
Inverted Logic High CMR Intelligent Power Module
and Gate Drive Interface Optocoupler

Data Sheet

Description Features
The ACPL-M483/P483/W483 fast speed optocoupler  Inverted output type (totem pole output)
contains a AlGaAs LED and photo detector with built-in  Truth Table Guaranteed: Vcc from 4.5 V to 30 V
Schmitt trigger to provide logic-compatible waveforms,
eliminating the need for additional wave shaping. The  Performance Specified for Common IPM Applications
totem pole output eliminates the need for a pull up Over Industrial Temperature Range.
resistor and allows for direct drive of Intelligent Power  Short Maximum Propagation Delays
Module or as a gate driver. Minimized propagation delay  Minimized Pulse Width Distortion (PWD)
difference between devices makes these optocouplers
excellent solutions for improving inverter efficiency  Very High Common Mode Rejection (CMR)
through reduced switching dead time.  Hysteresis
 Available in SO-5 (ACPL-M483) and Stretched SO-6
Applications package (ACPCL-P483/W483).
 IPM Interface Isolation  Package Clearance/Creepage at 8 mm (ACPL-W483)
 Isolated IGBT/MOSFET Gate Drive  Safety Approval:
 AC and Brushless DC Motor Drives – UL Recognized with 5000 Vrms (ACPL-W483) for 1
 Industrial Inverters minute per UL1577.
 General Digital Isolation – CSA Approved.
– IEC/EN/DIN EN 60747-5-5 Approved with VIORM =
Functional Diagram 567 Vpeak for ACPL-M483 and VIORM = 891 Vpeak for
ACPL-M483 ACPL-P483 and VIORM = 1140 Vpeak for ACPL-W483,
under option 060.
Anode 1 6 VCC
Note: A 0.1 F bypass
5 VO
capacitor must be con-
Specifications
Cathode 3 SHIELD 4 Ground nected between pins Vcc  Wide operating temperature range: -40°C to 105°C.
and Ground.
 Maximum propagation delay tPHL/tPLH = 120/120 ns
ACPL-P483 & ACPL-W483 Truth Table  Maximum Pulse Width Distortion (PWD) = 50 ns.
(Negative Logic)  Propagation Delay Difference Min/Max = –100/100 ns
Anode 1 6 VCC
LED VO  Wide Operating VCC Range: 4.5 to 30 Volts
N.C. 2 5 VO
ON LOW
Cathode 3 SHIELD 4 Ground  30 kV/s minimum common mode rejection (CMR) at
OFF HIGH
VCM = 1000 V.
Truth Table Guaranteed:
Vcc from 4.5 V to 30 V

CAUTION: It is advised that normal static precautions be taken in handling and assembly
of this component to prevent damage and/or degradation which may be induced by ESD.
Ordering Information
ACPL-M483/P483/W483 is UL recognized with 3750/3750/5000 Vrms/1 minute rating per UL 1577 respectively.
Option IEC/EN/DIN
Part number RoHS Compliant Package Surface Mount Tape & Reel EN 60747-5-5 Quantity
ACPL-M483 -000E SO-5 X 100 per tube
-500E X X 1500 per reel
-060E X X 100 per tube
-560E X X X 1500 per reel
ACPL-P483 -000E Stretched X 100 per tube
ACPL-W483 -500E SO-6 X X 1000 per reel
-060E X X 100 per tube
-560E X X X 1000 per reel

To order, choose a part number from the part number column and combine with the desired option from the option
column to form an order entry.
Example 1:
ACPL-P483-560E to order product of Stretched SO-6 Surface Mount package in Tape and Reel packaging with IEC/EN/
DIN EN 60747-5-5 Safety Approval in RoHS compliant.
Example 2:
ACPL-P483-000E to order product of Stretched SO-6 Surface Mount package in Tube packaging and RoHS compliant.
Example 3:
ACPL-M483-000E to order product of SO-5 Surface Mount package in Tube packaging and RoHS compliant.
Option datasheets are available. Contact your Avago sales representative or authorized distributor for information.

2
Package Outline Drawings
ACPL-M483 SO-5 Package, 5 mm Creepage & Clearance

TYPE NUMBER (LAST 3 DIGITS)

5
6

4
DATE CODE
Land Pattern Recommendation
4.4
(0.17)

4.4 ± 0.1
MXXX 7.0 ± 0.2
(0.173 ± 0.004) XXX (0.276 ± 0.008)
1.3 (0.05)
2.5 (0.10)
1

2.0 (0.080)
0.4 ± 0.05 0.64 (0.025)
(0.016 ± 0.002) 8.27
(0.325)
3.6 ± 0.1*
(0.142 ± 0.004)

0.102 ± 0.102 0.15 ± 0.025

2.5 ± 0.1 (0.004 ± 0.004)
(0.098 ± 0.004) (0.006 ± 0.001)

7° MAX.
1.27 BSC 0.71 MIN
(0.050) (0.028)

MAX. LEAD COPLANARITY

= 0.102 (0.004)
Dimensions in millimeters (inches).
* Maximum Mold flash on each side is 0.15 mm (0.006).
Note: Foating Lead Protrusion is 0.15 mm (6 mils) max.

3
ACPL-P483 Stretched SO-6 Package, 7 mm clearance

4.580 +– 0.254
0 Land Pattern Recommendation
0.381 ±0.127 1.27 (0.050) BSG
(0.015 ±0.005) (0.180 +– 0.010
0.000 ) 0.64 (0.025)

1.27 (0.05)

2.16
10.7 (0.085)
(0.421)

7.62 (0.300)
6.81 (0.268) 1.590 ±0.127 3.180 ±0.127
(0.063 ±0.005) (0.125 ±0.005)
0.45 (0.018)
45°
7° 7°

7°

0.20 ±0.10 7° 0.254 ±0.050

(0.008 ±0.004) (0.010 ±0.002)

1 ±0.250 5° NOM. Floating Lead Protusions max. 0.25 (0.01)

(0.040 ±0.010) Dimensions in Millimeters (Inches)
9.7 ±0.250
(0.382 ±0.010) Lead Coplanarity = 0.1 mm (0.004 Inches)

ACPL-W483 Stretched SO-6 Package, 8 mm clearance

4.580 +– 0.254
0

0.381 ±0.127 1.27 (0.050) BSG (0.180 +– 0.010

0.000 )

(0.015 ±0.005) Land Pattern Recommendation

0.64 (0.025)
1 6
2 5
3 4
1.27 (0.05)

1.905
7.62 (0.300) 12.65 (0.075)
6.807 +– 0.127
0 (0.5)
( 0.268 +– 0.005
0.000 )
1.590 ±0.127 3.180 ±0.127
7° (0.063 ±0.005) (0.125 ±0.005)
45°
0.45 (0.018) 7°

0.20 ±0.10
(0.008 ±0.004)

7° 0.254 ±0.050 7°
0.750 ±0.250 (0.010 ±0.002)
(0.0295 ±0.010)
35° NOM. Floating Lead Protusions max. 0.25 (0.01)
11.500 ±0.25 Dimensions in Millimeters (Inches)
(0.453 ±0.010) Lead Coplanarity = 0.1 mm (0.004 Inches)

4
Recommended Pb-Free IR Profile
Recommended reflow condition as per JEDEC Standard, J-STD-020 (latest revision). Non-Halide Flux should be used.

Regulatory Information
The ACPL-M483/P483/W483 is approved by the following organizations:
IEC/EN/DIN EN 60747-5-5 (Option 060 only)
Approved with Maximum Working Insulation Voltage VIORM = 567 Vpeak for ACPL-M483, VIORM = 891 Vpeak for ACPL-P483,
and VIORM = 1140 Vpeak for ACPL-W483
UL
Approval under UL 1577, component recognition program up to VISO = 3750 VRMS File E55361 for ACPL-M483 and
ACPL-P483;
Approval under UL 1577, component recognition program up to VISO = 5000 VRMS File E55361 for ACPL-W483;
CSA
Approval under CSA Component Acceptance Notice #5, File CA 88324.

Table 1. IEC/EN/DIN EN 60747-5-5 Insulation Characteristics* (ACPL-M483/P483/W483 Option 060)

Description Symbol ACPL-M483 ACPL-P483 ACPL-W483 Unit
Installation classification per DIN VDE 0110/1.89, Table 1
for rated mains voltage ≤ 150 Vrms I – IV I – IV I – IV
for rated mains voltage ≤ 300 Vrms I – IV I – IV I – IV
for rated mains voltage ≤ 450 Vrms I – III I – III I – IV
for rated mains voltage ≤ 600 Vrms I – III I – III I – IV
for rated mains voltage ≤ 1000 Vrms I – III
Climatic Classification 55/105/21 55/105/21 55/105/21
Pollution Degree (DIN VDE 0110/1.89) 2 2 2
Maximum Working Insulation Voltage VIORM 567 891 1140 Vpeak
Input to Output Test Voltage, Method b* VPR 1063 1670 2137 Vpeak
VIORM x 1.875 = VPR, 100% Production Test with tm = 1 sec,
Partial discharge < 5 pC
Input to Output Test Voltage, Method a* VPR 907 1426 1824 Vpeak
VIORM x 1.6 = VPR, Type and Sample Test, tm = 10 sec,
Partial discharge < 5 pC
Highest Allowable Overvoltage VIOTM 6000 6000 8000 Vpeak
(Transient Overvoltage tini = 60 sec)
Safety-limiting values – maximum values allowed in
the event of a failure.
Case Temperature TS 175 175 175 °C
Input Current IS, INPUT 230 230 230 mA
Output Power PS, OUTPUT 600 600 600 mW
Insulation Resistance at TS, VIO = 500 V RS >109 >109 >109 
* Refer to the optocoupler section of the Isolation and Control Components Designer’s Catalog, under Product Safety Regulations section,
(IEC/EN/DIN EN 60747-5-2) for a detailed description of Method a and Method b partial discharge test profiles.

5
Table 2. Insulation and Safety Related Specifications
Parameter Symbol ACPL-M483 ACPL-P483 ACPL-W483 Units Conditions
Minimum External Air Gap L(101) 5.0 7.0 8.0 mm Measured from input terminals to
(External Clearance) output terminals, shortest distance
through air.
Minimum External Tracking L(102) 5.0 8.0 8.0 mm Measured from input terminals to out-
(External Creepage) put terminals, shortest distance path
along body.
Minimum Internal Plastic Gap 0.08 0.08 0.08 mm Through insulation distance conductor
(Internal Clearance) to conductor, usually the straight line
distance thickness between the
emitter and detector.
Tracking Resistance CTI >175 >175 >175 V DIN IEC 112/VDE 0303 Part 1
(Comparative Tracking Index)
Isolation Group IIIa IIIa IIIa Material Group (DIN VDE 0110, 1/89,
Table 1)

Table 3. Absolute Maximum Ratings

Parameter Symbol Min. Max. Units Note
Storage Temperature TS -55 125 °C
Operating Temperature TA -40 105 °C
Average Input Current IF(avg) 10 mA
Peak Transient Input Current IF(tran)
(<1 s pulse width, 300 pps) 1.0 A
(<200 s pulse width, < 1% duty cycle) 40 mA
Reverse Input Voltage VR 5 V
Average Output Current IO 50 mA
Supply Voltage VCC 0 35
Output Voltage VO -0.5 35
Total Package Power Dissipation (ACPL-M483) PT 145 mW 1
Total Package Power Dissipation (Others) PT 210 mW 1
Solder Reflow Temperature Profile See Reflow Thermal Profile.

Table 4. Recommended Operating Conditions

Parameter Symbol Min. Max. Units Note
Power Supply Voltage (1) VCC 4.5 30 V 2
Forward Input Current (ON) IF(ON) 4 7 mA
Forward Input Voltage (OFF) VF(OFF) — 0.8 V
Operating Temperature TA –40 105 °C
Note:
1. Truth Table guaranteed: 4.5 V to 30 V

6
Table 5. Electrical Specifications
Over recommended operating conditions TA = -40°C to 105° C, VCC = +4.5 V to 30 V, IF(ON) = 4 mA to 7 mA, VF(OFF) = 0 V to
0.8 V, unless otherwise specified. All typical values at TA = 25°C.
Parameter Symbol Min. Typ. Max. Units Test Conditions Fig. Note
Logic Low Output Voltage VOL 0.3 V IOL = 3.5 mA 1, 3
0.5 IOL = 6.5 mA
Logic High Output Voltage VOH VCC -0.3 VCC -0.04 V IOH = -3.5 mA 2, 3, 7
VCC -0.5 VCC -0.07 IOH = -6.5 mA
Logic Low Supply Current ICCL 1.5 3.0 mA VCC = 5.5 V, IF = 7 mA, Io = 0 mA
1.7 3.0 mA VCC = 20 V, IF = 7 mA, Io = 0 mA
Logic High Supply Current ICCH 1.5 3.0 mA VCC = 5.5 V, VF = 0 V, Io = 0 mA
1.7 3.0 mA VCC = 30 V, VF = 0 V, Io = 0 mA
Threshold Input Current, IFHL 0.8 2.2 mA
Output High to Low
Threshold Input Voltage VFLH 0.8 V
Output Low to High
Logic Low Short Circuit IOSL 125 200 mA VO = VCC = 5.5 V, IF = 7 mA, VO = GND 3
Output Current
125 200 mA VO = VCC = 20 V, IF = 7 mA, VO = GND
Logic High Short Circuit IOSH -200 -125 mA VCC = 5.5 V, VF = 0 V 3
Output Current
-200 -125 mA VCC = 20 V, VF = 0 V
Input Forward Voltage VF 1.3 1.5 1.7 V TA = 25° C, IF = 4 mA 4
1.85 V IF = 4 mA
Input Reverse Breakdown BVR 5 V IR = 10 A
Voltage
Input Diode Temperature VF/TA 1.7 mV/°C IF = 4 mA
Coefficient
Input Capacitance CIN 60 pF f = 1 MHz, VF = 0 V 4

7
Table 6. Switching Specifications
Over recommended operating conditions TA = -40° C to 105° C, VCC = +4.5 V to 30 V, IF(ON) = 4 mA to 7 mA, VF(OFF) = 0 V
to 0.8 V, unless otherwise specified. All typicals at TA = 25° C.
Parameter Symbol Min. Typ. Max. Units Test Conditions Fig. Note
Propagation Delay Time tPHL 75 120 ns CL = 100pF, VF = 0 V  IF(OFF) = 4 mA 5, 6, 8 6
to Logic Low Output Level 120 Loaded as per Fig. 5
Propagation Delay Time tPLH 75 120 ns CL = 100 pF, IF(OFF) = 4 mA VF = 0 V 5, 6, 8 6
to Logic High Output Level 120 Loaded as per Fig. 5
Pulse Width Distortion |tPHL - tPLH| 50 ns CL = 100 pF 5, 6, 8 9
= PWD 50 Loaded as per Fig. 5
Propagation Delay PDD –100 100 ns CL = 100 pF 5, 6, 8 10
Difference Between
Any 2 Parts –100 100 Loaded as per Fig. 5

Output Rise Time (10-90%) tr 6 ns 5

Output Fall Time (90-10%) tf 6 ns 5
Logic High Common Mode |CMH| 30 kV/s |VCM| = 1000 V, VF = 0 V, 9 7
Transient Immunity VCC = 5 V, TA = 25°C
Logic Low Common Mode |CML| 30 kV/s |VCM| = 1000 V, IF = 4.0 mA, 9 7
Transient Immunity VCC = 5 V, TA = 25°C

Table 7. Package Characteristics

Parameter Symbol Min. Typ. Max. Units Test Conditions Fig. Note
Input-Output Momentary VISO 3750 (ACPL-M483 Vrms RH < 50%, t = 1 min. 5, 8
Withstand Voltage* and P483) TA = 25°C
5000 (ACPL-W483)
Input-Output Resistance RI-O 1012 Ohm VI-O = 500 Vdc 5
Input-Output Capacitance CI-O 0.6 pF f = 1 MHz, VI-O = 0 Vdc 5
* The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous
voltage rating. For the continuous voltage rating, refer to the IEC/EN/DIN EN 60747-5-5 Insulation Characteristics Table (if applicable).

Inverted UVLO
Figures 10a and b show typical output waveforms during Power-up and Power-down processes.
Notes:
1. Derate total package power dissipation, PT, linearly above 70°C free-air temperature at a rate of 4.5mW/°C (ACPL-P483/W483) and linearly above
85°C free-air temperature at a rate of 0.75 mW/°C (ACPL-M483).
2. Detector requires a Vcc of 4.5 V or higher for stable operation as output might be unstable if Vcc is lower than 4.5 V. Be sure to check the power
ON/OFF operation other than the supply current.
3. Duration of output short circuit time should not exceed 500 s.
4. Input capacitance is measured between pin 1 and pin 3.
5. Device considered a two-terminal device: pins 1, 2 and 3 shorted together and pins 4, 5 and 6 shorted together.
6. The tPLH propagation delay is measured from the 50% point on the trailing edge of the input pulse to the 1.3 V point on the leading edge of the
output pulse. The tPHL propagation delay is measured from the 50% point on the leading edge of the input pulse to the 1.3 V point on the trailing
edge of the output pulse. Peaking capacitor, C1 = 120 pF must be connected as shown in Figure 5.
7. CMH is the maximum slew rate of the common mode voltage that can be sustained with the output voltage in the logic high state, VO > 2.0 V.
CML is the maximum slew rate of the common mode voltage that can be sustained with the output voltage in the logic low state, VO < 0.8 V. Note:
Equal value split resistors (Rin/2) must be used at both ends of the LED.
8. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage  4500 VRMS for one second (leakage detection
current limit, II-O < = 5 A). This test is performed before the 100% production test for partial discharge (Method b) shown in the IEC/EN/DIN EN
60747-5-5 Insulation Characteristics Table, if applicable.
9. Pulse Width Distortion (PWD) is defined as |tPHL - tPLH | for any given device.
10. The difference of tPLH and tPHL between any two devices under the same test condition.
11. Use of a 0.1 F bypass capacitor connected between pins Vcc and Ground is recommended.

8
 0.05 0.12

(VCC-VOH) - High Level Output Voltage - V

IF = 4 mA VF = 0 V
VOL - LOW LEVEL OUTPUT VOLTAGE - V
0.045
0.1
0.04
IO = 6.5 mA IO = -6.5 mA
0.035 0.08
0.03
0.025 0.06
IO = 3.5 mA IO = -3.5 mA
0.02
0.04
0.015
0.01 0.02
-40 -10 20 50 80 110 -40 -10 20 50 80 110
TA - TEMPERATURE - °C TA - TEMPERATURE - °C
Figure 1. Typical Logic Low Output Voltage vs. Temperature Figure 2. Typical Logic High Output Voltage vs. Temperature

5 100.00000
IFLH TA = 25° C
IFHL 10.00000

IF - FORWARD CURRENT - mA
4
Vo - OUTPUT VOLTAGE - V

1.00000
3 0.10000
VCC = 4.5 V
TA = 25° C 0.01000
2
0.00100
1
0.00010

0 0.00001
0 0.5 1 1.5 2 1.1 1.2 1.3 1.4 1.5 1.6
IF - INPUT CURRENT - mA VF - FORWARD VOLTAGE - V
Figure 3. Typical Output Voltage vs. Forward Input Current Figure 4. Typical Input Diode Forward Characteristic

PULSE GEN.
tr = tf = 5 ns
f = 100 kHz THE PROBE AND JIG CAPACITANCES ARE
10% DUTY INCLUDED IN C1 AND C2.
CYCLE VCC
Vo = 5 V R1 820 : 560 :
5V
Zo = 50 IF(ON) 4 mA 7 mA
OUTPUT Vo
1 6 MONITORING 619 Ω ALL DIODES ARE EITHER 1N916 OR 1N3064
* NODE IF(ON)
D1 50% IF(ON)
2 5 INPUT IF
0 mA
INPUT D2 tPHL tPLH
MONITORING
NODE 3 SHIELD 4 D3
C2 = 5 kΩ
R1 15 pF
C1 = 120 pF D4 OUTPUT V VOH
1.3 V
VOL (0 V)
*0.1 μF BYPASS – SEE NOTE 11

Figure 5. Circuit for tPLH, tPHL, tr, tf

9
 90 35
Vcc = 4.5 V IF = 4 mA
30 TA = 25° C
Tp - Propagation Delay - ns

80

VO - Output Voltage - V
25

20
70
15
TPHL (If = 4 mA) 10
60 TPLH (If = 4 mA)
TPHL (If = 7 mA) 5
TPLH (If = 7 mA)
50 0
-40 -10 20 50 80 110 0 5 10 15 20 25 30 35
TA - Temperature - °C VCC - Supply Voltage - V
Figure 6. Typical Propagation Delays vs. Temperature Figure 7. Typical Logic High Output Voltage vs. Supply Voltage

90
TA = 25° C TPHL (If = 4 mA)
TPLH (If = 4 mA)
Tp - Propagation Delay - ns

80 TPHL (If = 7 mA)

TPLH (If = 7 mA)

70

60

50
0 5 10 15 20 25 30 35
VCC - Supply Voltage - V
Figure 8. Typical Propagation Delay vs. Supply Voltage

VCC CMH
CML
RIN/2
A VCM
|VCM| (PEAK)
1 6 0V
B 0.1 μF
VFF +
– 2 5
OUTPUT Vo SWITCH AT B: VF = 0 V
RIN/2 MONITORING VOH
3 4 NODE Vo (MIN.)*
SHIELD
OUTPUT Vo
SWITCH AT A: IF = 4 mA
VCM Vo (MAX.)*
VOL
+ –
* SEE NOTE 7

Figure 9. Test Circuit for Common Mode Transient Immunity and Typical Waveforms

10
 Vcc = 2~4 V 10 V
Vcc Vcc = 2~4 V
Vcc = 1.8 V (typ) Vcc = 1.8 V (typ)

0V

Output
High High
Impedance Impedance
state state

1 ms i. LED is OFF Discharge delay,

depending on the
power supply slew rate
Figure 10a. Vcc Ramp when LED is OFF

Vcc = 2~4 V 10 V
Vcc Vcc = 2~4 V
Vcc = 1.8 V (typ) Vcc = 1.8 V (typ)

0V

High High
Impedance Impedance
state state
Output
1 ms ii. LED is ON Discharge delay,
depending on the
power supply slew rate
Figure 10b. Vcc Ramp when LED is ON

11
Thermal Model for ACPL-M483 Thermal Model for ACPL-P483/W483
SO5 Package Optocoupler SO6 Package Optocoupler
Definitions Definitions
R11: Junction to Ambient Thermal Resistance of LED due R11: Junction to Ambient Thermal Resistance of LED due
to heating of LED to heating of LED
R12: Junction to Ambient Thermal Resistance of LED due R12: Junction to Ambient Thermal Resistance of LED due
to heating of Detector (Output IC) to heating of Detector (Output IC)
R21: Junction to Ambient Thermal Resistance of Detector R21: Junction to Ambient Thermal Resistance of Detector
(Output IC) due to heating of LED. (Output IC) due to heating of LED.
R22: Junction to Ambient Thermal Resistance of Detector R22: Junction to Ambient Thermal Resistance of Detector
(Output IC) due to heating of Detector (Output IC). (Output IC) due to heating of Detector (Output IC).
P1: Power dissipation of LED (W). P1: Power dissipation of LED (W).
P2: Power dissipation of Detector/Output IC (W). P2: Power dissipation of Detector/Output IC (W).
T1: Junction temperature of LED (˚C). T1: Junction temperature of LED (˚C).
T2: Junction temperature of Detector (˚C). T2: Junction temperature of Detector (˚C).
Ta: Ambient temperature. Ta: Ambient temperature.
ΔT1: Temperature difference between LED junction and ΔT1: Temperature difference between LED junction and
ambient (˚C). ambient (˚C).
ΔT2: Temperature deference between Detector junction ΔT2: Temperature deference between Detector junction
and ambient. and ambient.
Ambient Temperature: Junction to Ambient Thermal Re- Ambient Temperature: Junction to Ambient Thermal Re-
sistances were measured approximately 1.25cm above sistances were measured approximately 1.25cm above
optocoupler at ~23˚C in still air optocoupler at ~23˚C in still air

Description Description
This thermal model assumes that an 5-pin single-channel This thermal model assumes that an 6-pin single-channel
plastic package optocoupler is soldered into a 7.62 cm x plastic package optocoupler is soldered into a 7.62 cm x
7.62 cm printed circuit board (PCB). The temperature at 7.62 cm printed circuit board (PCB). The temperature at
the LED and Detector junctions of the optocoupler can be the LED and Detector junctions of the optocoupler can be
calculated using the equations below. calculated using the equations below.
T1 = (R11 * P1 + R12 * P2) + Ta -- (1) T1 = (R11 * P1 + R12 * P2) + Ta -- (1)
T2 = (R21 * P1 + R22 * P2) + Ta -- (2) T2 = (R21 * P1 + R22 * P2) + Ta -- (2)

Jedec Specifications R11 R12, R21 R22 Jedec Specifications R11 R12, R21 R22
low K board 191 77, 91 99 low K board 167 64, 81 89
high K board 126 26, 35 51 high K board 117 31, 39 54
Notes: Notes:
1. Maximum junction temperature for above parts: 125°C. 1. Maximum junction temperature for above parts: 125°C.

For product information and a complete list of distributors, please go to our web site: www.avagotech.com

Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries.
Data subject to change. Copyright © 2012–2016 Avago Technologies. All rights reserved.
AV02-3216EN - September 9, 2016
 ACPL-M483-000E ACPL-W483-500E ACPL-W483-000E ACPL-W483-500E ACPL-M483-000E

ACPL-P483-000E

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